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ADCMP562BRQZ

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ADCMP562BRQZ

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Part Number ADCMP562BRQZ
Manufacturer Analog Devices Inc.
Description IC COMPARATOR PECL DUAL 20-QSOP
Datasheet ADCMP562BRQZ Datasheet
Package 20-SSOP (0.154", 3.90mm Width)
In Stock 18,336 piece(s)
Unit Price $ 6.5000 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 26 - Oct 1 (Choose Expedited Shipping)
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Part Number # ADCMP562BRQZ (Linear - Comparators) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADCMP562BRQZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Linear - Comparators
Datasheet ADCMP562BRQZDatasheet
Package20-SSOP (0.154", 3.90mm Width)
Series-
Typewith Latch
Number of Elements2
Output TypeComplementary, Differential, Open-Emitter, PECL
Voltage - Supply, Single/Dual (±)��4.75 V ~ 5.25 V
Voltage - Input Offset (Max)2mV @ -5.2V,5V
Current - Input Bias (Max)3µA @ -5.2V,5V
Current - Output (Typ)30mA
Current - Quiescent (Max)5mA, 28mA, 13mA
CMRR, PSRR (Typ)80dB CMRR, 85dB PSRR
Propagation Delay (Max)0.83ns
Hysteresis��1mV
Operating Temperature-40°C ~ 85°C
Package / Case20-SSOP (0.154", 3.90mm Width)
Mounting TypeSurface Mount
Supplier Device Package20-QSOP

ADCMP562BRQZ Datasheet

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Dual High Speed PECL Comparators Data Sheet ADCMP561/ADCMP562 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Differential PECL-compatible outputs 700 ps propagation delay input to output 75 ps propagation delay dispersion Input common-mode range: –2.0 V to +3.0 V Robust input protection Differential latch control Internal latch pull-up resistors Power supply rejection greater than 85 dB 700 ps minimum pulse width 1.5 GHz equivalent input rise time bandwidth Typical output rise/fall time of 500 ps ESD protection > 4 kV HBM, >200 V MM Programmable hysteresis APPLICATIONS Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Line receivers and signal restoration Clock drivers FUNCTIONAL BLOCK DIAGRAM 04 68 7- 0- 00 1 HYS* *ADCMP562 ONLY NONINVERTING INPUT INVERTING INPUT LATCH ENABLE INPUT Q OUTPUT LATCH ENABLE INPUT Q OUTPUT ADCMP561/ ADCMP562 Figure 1. 04 68 7- 0- 00 2 ADCMP561 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 –INA +INA QA QA VDD VEE LEA LEA –INB +INB QB QB GND VCC LEB LEB Figure 2. ADCMP561 16-Lead QSOP Pin Configuration 04 68 7- 0- 00 3 ADCMP562 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 –INA QA QA VDD VEE LEA LEA VDD +INA HYSA –INB QB QB GND VCC LEB LEB VDD +INB HYSB Figure 3. ADCMP562 20-Lead QSOP Pin Configuration GENERAL DESCRIPTION The ADCMP561/ADCMP562 are high speed comparators fabricated on Analog Devices, Inc., proprietary XFCB process. The devices feature a 700 ps propagation delay with less than 75 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of comparators. A separate programmable hysteresis pin is available on the ADCMP562. A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from −2.0 V to +3.0 V. Outputs are complementary digital signals that are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VDD − 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pull-ups that set the latch in tracking mode when left open. The ADCMP561/ADCMP562 are specified over the industrial temperature range (−40°C to +85°C).

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ADCMP561/ADCMP562 Data Sheet Rev. B | Page 2 of 14 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 Thermal Considerations .............................................................. 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 8 Timing Information ....................................................................... 10 Applications Information ............................................................... 11 Clock Timing Recovery .............................................................. 11 Optimizing High Speed Performance ...................................... 11 Comparator Propagation Delay Dispersion ............................ 11 Comparator Hysteresis .............................................................. 12 Minimum Input Slew Rate Requirement ................................ 12 Typical Application Circuits .......................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 2/2017—Data Sheet Changed from Rev. A to Rev. B Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 7/2004—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specification Table ....................................................... 4 Changes to Figure 14 ........................................................................ 9 Changes to Figure 21 ...................................................................... 12 Changes to Figure 23 ...................................................................... 13 4/2004—Revision 0: Initial Version

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Data Sheet ADCMP561/ADCMP562 Rev. B | Page 3 of 14 SPECIFICATIONS VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = −40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted. Table 1. Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit DC INPUT CHARACTERISTICS Input Voltage Range −2.0 3.0 V Input Differential Voltage −5 +5 V Input Offset Voltage VOS VCM = 0 V −10.0 ±2.0 +10.0 mV Input Offset Voltage Channel Matching ±2.0 mV Offset Voltage Tempco ΔVOS/dT 2.0 µV/°C Input Bias Current IIN −IN = −2 V, +IN = +3 V −10.0 ±3 +10.0 µA Input Bias Current Tempco 0.5 nA/°C Input Offset Current ±1.0 µA Input Capacitance CIN 0.75 pF Input Resistance, Differential Mode 750 kΩ Input Resistance, Common Mode 1800 kΩ Active Gain AV 63 dB Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 80 dB Hysteresis RHYS = ∞ ±1.0 mV LATCH ENABLE CHARACTERISTICS Latch Enable Voltage Range VDD − 2.0 VDD V Latch Enable Differential Voltage Range 0.4 2.0 V Latch Enable Input High Current @ VDD −300 +300 µA Latch Enable Input Low Current @ VDD −2.0 V −300 +300 µA LE Voltage, Open Latch inputs not connected VDD − 0.2 VDD VDD + 0.1 V LE Voltage, Open Latch inputs not connected VDD/2 − 0.2 VDD/2 VDD/2 + 0.2 V Latch Setup Time tS VOD = 250 mV 250 ps Latch Hold Time tH VOD = 250 mV 250 ps Latch-to-Output Delay tPLOH, tPLOL VOD = 250 mV 600 ps Latch Minimum Pulse Width tPL VOD = 250 mV 500 ps DC OUTPUT CHARACTERISTICS Output Voltage—High Level VOH PECL 50 Ω to VDD − 2.0 V VDD − 1.15 VDD − 0.81 V Output Voltage—Low Level VOL PECL 50 Ω to VDD − 2.0 V VDD − 1.95 VDD − 1.54 V Rise Time tR 10% to 90% 550 ps Fall Time tF 10% to 90% 470 ps AC PERFORMANCE Propagation Delay tPD VOD = 1 V 700 ps VOD = 20 mV 830 ps Propagation Delay Tempco ΔtPD /dT VOD = 1 V 0.25 ps/°C Prop Delay Skew—Rising Transition to Falling Transition VOD = 1 V 50 ps Within Device Propagation Delay Skew— Channel-to-Channel VOD = 1 V 50 ps Overdrive Dispersion 20 mV ≤ VOD ≤ 100 mV 75 ps Overdrive Dispersion 100 mV ≤ VOD ≤ 1.5 V 75 ps Slew Rate Dispersion 0.4 V/ns ≤ SR ≤ 1.33 V/ns 50 ps Pulse Width Dispersion 700 ps ≤ PW ≤ 10 ns 25 ps Duty Cycle Dispersion 33 MHz, 1 V/ns, 0.5 V 15 ps Common-Mode Voltage Dispersion 1 V swing, −1.5 V ≤ VCM ≤ +2.5 V 10 ps

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ADCMP561/ADCMP562 Data Sheet Rev. B | Page 4 of 14 Parameter Symbol Conditions Min Typ Max Unit AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth1 BWEQ 0 V to 1 V swing, 2 V/ns 1500 MHz Maximum Toggle Rate >50% output swing 800 MHz Minimum Pulse Width PWMIN ΔtPD < 25 ps 700 ps RMS Random Jitter VOD = 400 mV, 1.3 V/ns, 312 MHz, 50% duty cycle 1.0 ps Unit-to-Unit Propagation Delay Skew 100 ps POWER SUPPLY Positive Supply Current IVCC @ +5.0 V 2 3.2 5 mA Negative Supply Current IVEE @ −5.2 V 10 22 28 mA Logic Supply Current IVDD @ 3.3 V without load 6 9 13 mA Logic Supply Current @ 3.3 V with load 45 60 70 mA Positive Supply Voltage VCC Dual 4.75 5.0 5.25 V Negative Supply Voltage VEE Dual −4.96 −5.2 −5.45 V Logic Supply Voltage VDD Dual 2.5 3.3 5.0 V Power Dissipation PD Dual, without load 130 160 190 mW Power Dissipation Dual, with load 180 220 250 mW DC Power Supply Rejection Ratio—VCC PSRRVCC 85 dB DC Power Supply Rejection Ratio—VEE PSRRVEE 85 dB DC Power Supply Rejection Ratio—VDD PSRRVDD 85 dB HYSTERESIS (ADCMP562 Only) Hysteresis RHYS = 19.5 kΩ 20 mV RHYS = 8.0 kΩ 70 mV 1 Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√ (trCOMP2 – trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.

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Data Sheet ADCMP561/ADCMP562 Rev. B | Page 5 of 14 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltages Positive Supply Voltage (VCC to GND) −0.5 V to +6.0 V Negative Supply Voltage (VEE to GND) −6.0 V to +0.5 V Logic Supply Voltage (VDD to GND) −0.5 V to +6.0 V Ground Voltage Differential −0.5 V to +0.5 V Input Voltages Input Common-Mode Voltage −3.0 V to +4.0 V Differential Input Voltage −7.0 V to +7.0 V Input Voltage, Latch Controls −0.5 V to +5.5 V Output Output Current 30 mA Temperature Operating Temperature, Ambient −40°C to +85°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL CONSIDERATIONS The ADCMP561 QSOP 16-lead package option has a θJA (junction-to-ambient thermal resistance) of 104°C/W in still air. The ADCMP562 QSOP 20-lead package option has a θJA (junction-to-ambient thermal resistance) of 80°C/W in still air. ESD CAUTION

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ADCMP561/ADCMP562 Data Sheet Rev. B | Page 6 of 14 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 04 68 7- 0- 00 2 ADCMP561 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 –INA +INA QA QA VDD VEE LEA LEA –INB +INB QB QB GND VCC LEB LEB Figure 4. ADCMP561 16-Lead QSOP Pin Configuration 04 68 7- 0- 00 3 ADCMP562 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 –INA QA QA VDD VEE LEA LEA VDD +INA HYSA –INB QB QB GND VCC LEB LEB VDD +INB HYSB Figure 5. ADCMP562 20-Lead QSOP Pin Configuration Table 3. Pin Function Descriptions Pin No. ADCMP561 ADCMP562 Mnemonic Function 1 VDD Logic Supply Terminal. 1 2 QA One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. 2 3 QA One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. 3 4 VDD Logic Supply Terminal. 4 5 LEA One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 5 6 LEA One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 6 7 VEE Negative Supply Terminal. 7 8 −INA Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. 8 9 +INA Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. 10 HYSA Programmable Hysteresis Input. 11 HYSB Programmable Hysteresis Input. 9 12 +INB Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. 10 13 −INB Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. 11 14 VCC Positive Supply Terminal. 12 15 LEB One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to placing the comparator in the latch mode. LEB must be driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode.

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Data Sheet ADCMP561/ADCMP562 Rev. B | Page 7 of 14 Pin No. ADCMP561 ADCMP562 Mnemonic Function 13 16 LEB One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to placing the comparator in the latch mode. LEB must be driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode. 14 17 GND Analog Ground. 15 18 QB One of two complementary outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of PIN LEB for more information. 16 19 QB One of two complementary outputs for Channel B. QB is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEB for more information. 20 VDD Logic Supply Terminal.

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ADCMP561/ADCMP562 Data Sheet Rev. B | Page 8 of 14 TYPICAL PERFORMANCE CHARACTERISTICS VCC = +5.0 V, VEE = –5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted. 3.0 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 04 68 7- 0- 01 3 NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0V) IN PU T B IA S C U R R EN T (µ A ) Figure 6. Input Bias Current vs. Input Voltage 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 –40 –20 0 20 40 60 80 04 68 7- 0- 01 4 TEMPERATURE (°C) O FF SE T VO LT A G E (m V) Figure 7. Input Offset Voltage vs. Temperature 575 525 530 535 540 545 550 555 560 565 570 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 04 68 7- 0- 01 5 TEMPERATURE (°C) TI M E (p s) Figure 8. Rise Time vs. Temperature 2.80 2.78 2.76 2.74 2.72 2.70 2.68 2.66 2.64 2.62 2.60 –40 –20 0 20 40 60 80 04 68 7- 0- 01 6 TEMPERATURE (°C) +I N IN PU T B IA S C U R R EN T (µ A ) (+ IN = 3 V, –I N = 0 V) Figure 9. Input Bias Current vs. Temperature 2.6 1.4 1.6 1.8 2.0 2.2 2.4 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 04 68 7- 0- 01 7 TIME (ns) O U TP U T R IS E A N D F A LL (V ) Figure 10. Rise and Fall of Outputs vs. Time 500 450 455 460 465 470 475 480 485 490 495 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 04 68 7- 0- 01 8 TEMPERATURE (°C) TI M E (p s) Figure 11. Fall Time vs. Temperature

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Data Sheet ADCMP561/ADCMP562 Rev. B | Page 9 of 14 715 680 685 690 695 700 705 710 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 04 68 7- 0- 01 9 TEMPERATURE (°C) PR O PA G A TI O N D EL A Y (p s) Figure 12. Propagation Delay vs. Temperature 140 120 100 80 60 40 20 0 0 1.61.41.21.00.80.60.40.2 04 68 7- 0- 02 0 OVERDRIVE VOLTAGE (V) PR O PA G A TI O N D EL A Y ER R O R (p s) Figure 13. Propagation Delay vs. Overdrive Voltage 160 140 120 100 80 60 40 20 0 01020304050 04 68 7- 0- 02 1 RHYS (kΩ) PR O G R A M M ED H YS TE R ES IS (m V) Figure 14. Comparator Hysteresis vs. RHYS 708 706 704 702 700 698 696 694 –2 –1 0 1 2 3 04 68 7- 0- 02 2 INPUT COMMON-MODE VOLTAGE (V) PR O PA G A TI O N D EL A Y (p s) Figure 15. Propagation Delay vs. Common-Mode Voltage 25 –5 0 5 10 15 20 0.7 1.7 2.7 3.7 4.7 5.7 6.7 7.7 8.7 9.7 04 68 7- 0- 02 3 PULSE WIDTH (ns) PR O PA G A TI O N D EL A Y ER R O R (p s) Figure 16. Propagation Delay Error vs. Pulse Width 160 140 120 100 80 60 40 20 0 0 50 100 150 04 68 7- 0- 02 4 IHYS (µA) PR O G R A M M ED H YS TE R ES IS (m V) Figure 17. Comparator Hysteresis vs. IHYS

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Sant*****Perry

August 17, 2020

Worked very well! I would highly recommend buying.

Emil*****homas

August 16, 2020

Worked wonderfully. Went through the instructions to the tea to make sure it was done correctly.

Emmi*****urst

August 16, 2020

Went well this time Now have the IC and very pleased.

Janes*****dkarni

August 12, 2020

2nd time buying these - quite good. Very fast shipping

Hav*****Beil

August 11, 2020

It's so nice to have all these babies. I was using so many for projects, I decided to buy these. They'll definitely last me a while!

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August 10, 2020

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Sea*****udson

August 3, 2020

They worked as I expected. I'll definitely purchase again. Thank you!

Abig*****Wall

July 22, 2020

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Mcke*****Decker

July 14, 2020

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Gabr*****Adams

July 11, 2020

Resonators were genuine Murata components and arrived in 3 days from Hongkong

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