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ADG512BNZ

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ADG512BNZ

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Part Number ADG512BNZ
Manufacturer Analog Devices Inc.
Description IC SWITCH QUAD SPST 16DIP
Datasheet ADG512BNZ Datasheet
Package 16-DIP (0.300", 7.62mm)
In Stock 360 piece(s)
Unit Price $ 7.3300 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # ADG512BNZ (Interface - Analog Switches, Multiplexers, Demultiplexers) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADG512BNZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Analog Switches, Multiplexers, Demultiplexers
Datasheet ADG512BNZDatasheet
Package16-DIP (0.300", 7.62mm)
Series-
Switch CircuitSPST - NO
Multiplexer/Demultiplexer Circuit1:1
Number of Circuits4
On-State Resistance (Max)30 Ohm (Typ)
Channel-to-Channel Matching (ΔRon)-
Voltage - Supply, Single (V+)3 V ~ 5.5 V
Voltage - Supply, Dual (V±)��4.5 V ~ 5.5 V
Switch Time (Ton, Toff) (Max)200ns, 120ns (Typ)
-3db Bandwidth-
Charge Injection11pC
Channel Capacitance (CS(off), CD(off))9pF, 9pF
Current - Leakage (IS(off)) (Max)100pA
Crosstalk-85dB @ 1MHz
Operating Temperature-40°C ~ 85°C (TA)
Package / Case16-DIP (0.300", 7.62mm)
Supplier Device Package16-PDIP

ADG512BNZ Datasheet

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FUNCTIONAL BLOCK DIAGRAMS IN1 IN2 IN3 IN4 S1 D1 S2 D2 S3 D3 S4 D4 ADG511 IN1 IN2 IN3 IN4 S1 D1 S2 D2 S3 D3 S4 D4 ADG512 IN1 IN2 IN3 IN4 S1 D1 S2 D2 S3 D3 S4 D4 ADG513 SWITCHES SHOWN FOR A LOGIC "1" INPUT REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a LC 2MOS Precision 5 V/3 V Quad SPST Switches ADG511/ADG512/ADG513 FEATURES +3 V, +5 V or 5 V Power Supplies Ultralow Power Dissipation (<0.5 W) Low Leakage (<100 pA) Low On Resistance (<50 ) Fast Switching Times Low Charge Injection TTL/CMOS Compatible 16-Lead DIP or SOIC Package APPLICATIONS Battery-Powered Instruments Single Supply Systems Remote Powered Equipment 5 V Supply Systems Computer Peripherals such as Disk Drives Precision Instrumentation Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Sample Hold Systems Communication Systems Compatible with 5 V Supply DACs and ADCs such as AD7840/AD7848, AD7870/AD7871/AD7872/AD7874/ AD7875/AD7876/AD7878 GENERAL DESCRIPTION The ADG511, ADG512 and ADG513 are monolithic CMOS ICs containing four independently selectable analog switches. These switches feature low, well-controlled on resistance and wide analog signal range, making them ideal for precision analog signal switching. These switch arrays are fabricated using Analog Devices’ advanced linear compatible CMOS (LC2MOS) process which offers the additional benefits of low leakage currents, ultralow power dissipation and low capacitance for fast switching speeds with minimum charge injection. These features make the ADG511, ADG512 and ADG513 the optimum choice for a wide variety of signal switching tasks in precision analog signal processing and data acquisition systems. The ability to operate from single +3 V, +5 V or ±5 V bipolar supplies make the ADG511, ADG512 and ADG513 perfect for use in battery-operated instruments, 4–20 mA loop systems and with the new generation of DACs and ADCs from Analog Devices. The use of 5 V supplies and reduced operating currents give much lower power dissipation than devices operating from ±15 V supplies. The ADG511, ADG512 and ADG513 contain four indepen- dent SPST switches. The ADG511 and ADG512 differ only in that the digital control logic is inverted. The ADG511 switch is turned on with a logic low on the appropriate control input, while a logic high is required for the ADG512. The ADG513 contains two switches whose digital control logic is similar to that of the ADG511 while the logic is inverted in the remaining two switches. PRODUCT HIGHLIGHTS 1. 5 Volt Single Supply Operation The ADG511/ADG512/ADG513 offers high performance, including low on resistance and wide signal range, fully specified and guaranteed with +3 V, ±5 V as well as +5 V supply rails. 2. Ultralow Power Dissipation CMOS construction ensures ultralow power dissipation. 3. Low RON 4. Break-Before-Make Switching Switches are guaranteed to have break-before-make opera- tion. This allows multiple outputs to be tied together for multiplexer applications without the possibility of momentary shorting between channels. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

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Dual Supply B Versions T Version –40C to –55C to Parameter 25C +85C 25C +125C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS VDD to VSS V RON 30 30 Ω typ VD = ±3.5 V, IS = –10 mA; 50 50 Ω max VDD = +4.5 V, VSS = –4.5 V LEAKAGE CURRENTS VDD = +5.5 V, VSS = –5.5 V Source OFF Leakage IS (OFF) ± 0.025 ± 0.025 nA typ VD = ±4.5 V, VS = 4.5 V; ± 0.1 ± 2.5 ± 0.1 ± 2.5 nA max Test Circuit 2 Drain OFF Leakage ID (OFF) ± 0.025 ± 0.025 nA typ VD = ±4.5 V, VS = 4.5 V; ± 0.1 ± 2.5 ± 0.1 ± 2.5 nA max Test Circuit 2 Channel ON Leakage ID, IS (ON) ± 0.05 ± 0.05 nA typ VD = VS = ±4.5 V; ± 0.2 ± 5 ± 0.2 ± 5 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Current IINL or IINH 0.005 0.005 µA typ VIN = VINL or VINH ± 0.1 ± 0.1 µA max DYNAMIC CHARACTERISTICS2 tON 200 200 ns typ RL = 300 Ω. CL = 35 pF; 375 375 ns max VS = ±3 V; Test Circuit 4 tOFF 120 120 ns typ RL = 300 Ω. CL = 35 pF; 150 150 ns max VS = ±3 V; Test Circuit 4 Break-Before-Make Time 100 100 ns typ RL = 300 Ω, CL = 35 pF; Delay, tD (ADG513 Only) VS1 = VS2 = 3 V; Test Circuit 5 Charge Injection 11 11 pC typ VS = 0 V, RS = 0 Ω, CL = 10 nF; Test Circuit 6 OFF Isolation 68 68 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk 85 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 CS (OFF) 9 9 pF typ f = 1 MHz CD (OFF) 9 9 pF typ f = 1 MHz CD, CS (ON) 35 35 pF typ f = 1 MHz POWER REQUIREMENTS VDD +4.5/5.5 +4.5/5.5 V min/max VSS –4.5/–5.5 –4.5/–5.5 V min/max IDD 0.0001 0.0001 µA typ VDD = +5.5 V, VSS = –5.5 V 1 1 µA max Digital Inputs = 0 V or 5 V ISS 0.0001 0.0001 µA typ 1 1 µA max NOTES 1Temperature ranges are as follows: B Versions –40°C to +85°C; T Version –55°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. C–2– (VDD = +5 V  10%, VSS = –5 V  10%, GND = 0 V, unless otherwise noted) ADG511/ADG512/ADG513–SPECIFICATIONS1

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Single Supply B Versions T Version –40C to –55C to Parameter 25C +85C 25C +125C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD 0 V to VDD V RON 45 45 Ω typ VD = 3.5 V, IS = –10 mA; 75 75 Ω max VDD = 4.5 V LEAKAGE CURRENTS VDD = 5.5 V Source OFF Leakage IS (OFF) ±0.025 ±0.025 nA typ VD = 4.5/1 V, VS = 14.5 V; ±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2 Drain OFF Leakage ID (OFF) ±0.025 ±0.025 nA typ VD = 4.5/1 V, VS = 14.5 V; ±0.1 ±2.5 ±0.1 ±2.5 nA max Test Circuit 2 Channel ON Leakage ID, IS (ON) ±0.05 ±0.05 nA typ VD = VS = 4.5 V/1 V; ±0.2 ±5 ±0.2 ±5 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Current IINL or IINH 0.005 0.005 µA typ VIN = VINL or VINH ±0.1 ±0.1 µA max DYNAMIC CHARACTERISTICS2 tON 250 250 ns typ RL = 300 Ω, CL = 35 pF; 500 500 ns max VS = 2 V; Test Circuit 4 tOFF 50 50 ns typ RL = 300 Ω, CL = 35 pF; 100 100 ns max VS = 2 V; Test Circuit 4 Break-Before-Make Time 200 200 ns typ RL = 300 Ω, CL = 35 pF; Delay, tD (ADG513 Only) VS1 = VS2 = 2 V; Test Circuit 5 Charge Injection 16 16 pC typ VS = 0 V, RS = 0 Ω, CL = 10 nF; Test Circuit 6 OFF Isolation 68 68 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk 85 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 CS (OFF) 9 9 pF typ f = 1 MHz CD (OFF) 9 9 pF typ f = 1 MHz CD, CS (ON) 35 35 pF typ f = 1 MHz POWER REQUIREMENTS VDD 4.5/5.5 4.5/5.5 V min/max IDD 0.0001 0.0001 µA typ VDD = 5.5 V 1 1 µA max Digital Inputs = 0 V or 5 V NOTES 1Temperature ranges are as follows: B Versions –40°C to +85°C; T Version –55°C to +125°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. (VDD = 5 V  10%, VSS = 0 V, GND = 0 V, unless otherwise noted) ADG511/ADG512/ADG513 REV. C –3–

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Single Supply B Version 0C to Parameter 25C 70C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD V RON 200 Ω typ VD = 1.5 V, IS = –1 mA; 500 Ω max VDD = 3 V LEAKAGE CURRENTS VDD = 3.6 V Source OFF Leakage IS (OFF) ±0.025 nA typ VD = 2.6/1 V, VS = 12.6 V; ±0.1 ±2.5 nA max Test Circuit 2 Drain OFF Leakage ID (OFF) ±0.025 nA typ VD = 2.6/1 V, VS = 12.6 V; ±0.1 ±2.5 nA max Test Circuit 2 Channel ON Leakage ID, IS (ON) ±0.05 nA typ VD = VS = 2.6 V/1 V; ±0.2 ±5 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH 0.005 µA typ VIN = VINL or VINH ±0.1 µA max DYNAMIC CHARACTERISTICS2 tON 600 ns typ RL = 300 Ω, CL = 35 pF; 1200 ns max VS = 1 V; Test Circuit 4 tOFF 100 ns typ RL = 300 Ω, CL = 35 pF; 160 ns max VS = 1 V; Test Circuit 4 Break-Before-Make Time 500 ns typ RL = 300 Ω, CL = 35 pF; Delay, tD (ADG513 Only) VS1 = VS2 = 1 V; Test Circuit 5 Charge Injection 11 pC typ VS = 0 V, RS = 0 Ω, CL = 10 nF; Test Circuit 6 OFF Isolation 68 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 CS (OFF) 9 pF typ f = 1 MHz CD (OFF) 9 pF typ f = 1 MHz CD, CS (ON) 35 pF typ f = 1 MHz POWER REQUIREMENTS VDD 3/3.6 V min/max IDD 0.0001 µA typ VDD = 3.6 V 1 µA max Digital Inputs = 0 V or 3 V NOTES 1Temperature range is as follows: B Version –40°C to +85°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. C–4– ADG511/ADG512/ADG513–SPECIFICATIONS1 (VDD = 3.3 V  10%, VSS = 0 V, GND = 0 V, unless otherwise noted)

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ADG511/ADG512/ADG513 REV. C –5– ABSOLUTE MAXIMUM RATINGS1 (TA = +25°C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V Analog, Digital Inputs2 . . . . . . . . . . VSS – 2 V to VDD + 2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG511/ADG512/ADG513 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model1 Temperature Range2 Package Option3 ADG511BN –40°C to +85°C N-16 ADG511BR –40°C to +85°C R-16A ADG511ABR4 –40°C to +85°C R-16A ADG511TQ4 –55°C to +125°C Q-16 ADG512BN –40°C to +85°C N-16 ADG512BR –40°C to +85°C R-16A ADG512ABR4 –40°C to +85°C R-16A ADG513BN –40°C to +85°C N-16 ADG513BR –40°C to +85°C R-16A ADG513ABR4 –40°C to +85°C R-16A NOTES 1For availability of MIL-STD-883, Class B processed parts, contact factory. 23.3 V specifications apply over 0°C to 70°C temperature range. 3N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip. 4Trench isolated latch-up proof parts. See Trench Isolation section. WARNING! ESD SENSITIVE DEVICE

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ADG511/ADG512/ADG513 REV. C–6– PIN CONFIGURATION (DIP/SOIC) TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN1 D1 S1 VSS GND S4 D4 IN4 IN2 D2 S2 VDD NC S3 D3 IN3 ADG511 ADG512 ADG513 NC = NO CONNECT Truth Table (ADG511/ADG512) ADG511 ADG512 Switch In In Condition 0 1 ON 1 0 OFF Truth Table (ADG513) Switch Switch Logic 1, 4 2, 3 0 OFF ON 1 ON OFF TERMINOLOGY VDD Most Positive Power Supply Potential. VSS Most Negative Power Supply Potential in dual supplies. In single supply applications, it may be connected to GND. GND Ground (0 V) Reference. S Source Terminal. May be an input or output. D Drain Terminal. May be an input or output. IN Logic Control Input. RON Ohmic Resistance between D and S. IS (OFF) Source Leakage Current with the switch “OFF.” ID (OFF) Drain Leakage Current with the switch “OFF.” ID, IS (ON) Channel Leakage Current with the switch “ON.” VD (VS) Analog Voltage on terminals D, S. CS (OFF) “OFF” Switch Source Capacitance. CD (OFF) “OFF” Switch Drain Capacitance. CD, CS (ON) “ON” Switch Capacitance. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tD “OFF” or “ON” time measured between the 90% points of both switches when switching from one address state to another. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching.

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VD OR VS – DRAIN OR SOURCE VOLTAGE – V 50 40 0 –5 5–4 R O N –  –3 –2 –1 0 1 2 3 4 30 20 10 TA = 25C VDD = +3V VSS = –3V VDD = +5V VSS = –5V TPC 1. On Resistance as a Function of VD (VS) Dual Supplies VD OR VS – DRAIN OR SOURCE VOLTAGE – V 50 40 0 –5 5–4 R O N –  –3 –2 –1 0 1 2 3 4 30 20 10 VDD = +5V VSS = –5V 125C 85C 25C TPC 2. On Resistance as a Function of VD (VS) for Different Temperatures VD OR VS – DRAIN OR SOURCE VOLTAGE – V 90 80 20 0 51 R O N –  2 3 4 60 50 40 30 70 TA = 25C VDD = 3V VSS = 0V VDD = 5V VSS = 0V TPC 3. On Resistance as a Function of VD (VS) Single Supply Typical Performance Characteristics–ADG511/ADG512/ADG513 REV. C –7– FREQUENCY – Hz 10mA 10A 10nA 10M10 I S U P P L Y 100 1k 10k 100k 1M 1mA 100A 1A 100nA VDD = +5V VSS = –5V I–, I+ 1 SW 4 SW TPC 4. Supply Current vs. Input Switching Frequency TEMPERATURE – C 10 1 0.001 25 12535 L E A K A G E C U R R E N T – n A 45 55 65 75 85 95 105 115 0.1 0.01 VDD = +5V VSS = –5V VS = 5V VD = 5V ID (OFF) ID (ON) IS (OFF) TPC 5. Leakage Currents as a Function of Temperature FREQUENCY – Hz 120 100 40 100 10M1k O F F I S O L A T IO N – d B 10k 100k 1M 80 60 VDD = +5V VSS = –5V TPC 6. Off Isolation vs. Frequency

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ADG511/ADG512/ADG513 REV. C–8– VD OR VS – DRAIN OR SOURCE VOLTAGE – V 0.006 0.000 –0.006 –5 L E A K A G E C U R R E N T – n A 0.004 0.002 –0.002 –0.004 VDD = +5V VSS = –5V TA = +25C ID (OFF) ID (ON) IS (OFF) –4 –3 –2 –1 0 1 2 3 4 5 TPC 7. Leakage Currents as a Function of VD (VS) FREQUENCY – Hz 110 100 60 100 10M1k C R O S S T A L K – d B 10k 100k 1M 90 80 70 VDD = +5V VSS = –5V TPC 8. Crosstalk vs. Frequency APPLICATION Figure 1 illustrates a precise sample-and-hold circuit. An AD845 is used as the input buffer while the output operational ampli- fier is an OP07. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH. Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG511/ADG512/ ADG513 minimizes this droop due to its low leakage specifica- tions. The droop rate is further minimized by the use of a poly- styrene hold capacitor. The droop rate for the circuit shown is typically 15 µV/µs. A second switch, SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differen- tial effect on the op amp OP07, which will minimize charge injection effects. Pedestal error is also reduced by the compensation network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the ±3 V input range. The acquisition time is 2.5 µs while the settling time is 1.85 µs. +5V –5V 2200pF RC 75 CC 1000pF CH 2200pF VOUT ADG511/ ADG512/ ADG513 SW1 SW2 S S D D +5V –5V AD845 +5V –5V VIN OP07 Figure 1. Accurate Sample-and-Hold TRENCH ISOLATION The MOS devices that make up the ADG511A/ADG512A/ ADG513A are isolated from each other by an oxide layer (trench) (see Figure 2). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of “latch-up” caused by parasitic junctions between CMOS transistors. Latch-up is caused when P-N junctions that are normally reverse biased, become forward biased, causing large currents to flow. This can be destructive. CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation the N and P wells of the CMOS transistors form a diode that is reverse biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR)- type circuit is formed by the two transistors, causing a signifi- cant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up-proof circuit. BURIED OXIDE LAYER SUBSTRATE (BACKGATE) T R E N C H T R E N C H T R E N C H P+ P+ P-CHANNEL N+ N+ N-CHANNEL P–N– VG VDVS VG VDVS Figure 2. Trench Isolation

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ADG511/ADG512/ADG513 REV. C –9– IDS V1 S D VS RON = V1/IDS Test Circuit 1. On Resistance S D VS A VD A IS (OFF) ID (OFF) Test Circuit 2. Off Leakage S D VS VD A ID (ON) Test Circuit 3. On Leakage S D VDD 0.1F VDD IN VS GND VSS RL 300 CL 35pF VOUT 0.1F VSS tON tOFF 3V 50% 50% 50% 50% 3V 90% 90% VIN VIN VOUT ADG511 ADG512 Test Circuit 4. Switching Times S1 D1 0.1F VDD IN1, IN2 VS1 GND VSS RL1 300 CL1 35pF VOUT1 0.1F VS2 VOUT2 RL2 300 CL2 35pF S2 VIN D2 VDD VSS tD tD 3V 50% 50% 90% VIN VOUT1 VOUT2 90% 90%90% 0V 0V 0V Test Circuit 5. Break-Before-Make Time Delay S D VDD IN VS GND VSS CL 10nF VOUT RS VSS VDD 3V VIN VOUT VOUT QINJ = CL  VOUT Test Circuit 6. Charge Injection Test Circuits

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