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ADM4857ARZ

hot ADM4857ARZ

ADM4857ARZ

For Reference Only

Part Number ADM4857ARZ
Manufacturer Analog Devices Inc.
Description IC TXRX RS-485422 10MBPS 8-SOIC
Datasheet ADM4857ARZ Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 3694 piece(s)
Unit Price $ 2.45 *
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ADM4857ARZ

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ADM4857ARZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Drivers, Receivers, Transceivers
Datasheet ADM4857ARZ Datasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
TypeTransceiver
ProtocolRS422, RS485
Number of Drivers/Receivers1/1
DuplexFull
Receiver Hysteresis20mV
Data Rate10Mbps
Voltage - Supply4.75 V ~ 5.25 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

ADM4857ARZ Datasheet

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5 V, Slew Rate Limited, Half-Duplex and Full Duplex RS-485/RS-422 Transceivers Data Sheet ADM4850 to ADM4857 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Electronics industries alliance (EIA) RS-485/RS-422 compliant Data rate options ADM4850/ADM4854: 115 kbps ADM4851/ADM4855: 500 kbps ADM4852/ADM4856: 2.5 Mbps ADM4853/ADM4857: 10 Mbps Half-duplex and full duplex options Reduced slew rates for low electromagnetic interference (EMI) True fail-safe receiver inputs 5 µA (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-Z when disabled or powered off −7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with the MAX308x Specified over the −40°C to +85°C temperature range Available in 8-lead SOIC, 8-lead LFCSP, and 8-lead MSOP Qualified for automotive applications APPLICATIONS Low power RS-485 applications EMI sensitive systems DTE to DCE interfaces Industrial control Packet switching Local area networks Level translators GENERAL DESCRIPTION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 are differential line transceivers suitable for high speed, half-duplex and full duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850/ADM4851/ ADM4852/ADM4853 are half-duplex transceivers that share differential lines and have separate enable inputs for the driver and receiver. The full duplex ADM4854/ADM4855/ADM4856/ ADM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The devices have a 1/8-unit load receiver input impedance, which allows up to 256 transceivers on one bus. Because only one driver must be enabled at any time, the output of a disabled or powered down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. FUNCTIONAL BLOCK DIAGRAMS Figure 1. ADM4850/ADM4851/ADM4852/ADM4853 Functional Block Diagram Figure 2. ADM4854/ADM4855/ADM4856/ADM4857 Functional Block Diagram This guarantees that the receiver outputs are in a known state before communication begins and when communication ends. The driver outputs are slew rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The devices are fully specified over the commercial and industrial temperature ranges and are available in 8-lead SOIC (ADM4850 through ADM4857), 8-lead LFCSP (ADM4850/ADM4852/ ADM4853), and 8-lead MSOP (ADM4850 only) packages. Table 1. Selection Table Device No. Half-Duplex/Full Duplex Data Rate ADM4850 Half 115 kbps ADM4851 Half 500 kbps ADM4852 Half 2.5 Mbps ADM4853 Half 10 Mbps ADM4854 Full 115 kbps ADM4855 Full 500 kbps ADM4856 Full 2.5 Mbps ADM4857 Full 10 Mbps 04 93 1- 00 1 RO RE R DE DI D A B GND VCC ADM4850/ADM4851/ ADM4852/ADM4853 04 93 1- 02 8 RO R A B DI D Z Y GND VCC ADM4854/ADM4855/ ADM4856/ADM4857

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ADM4850 to ADM4857 Data Sheet Rev. F | Page 2 of 16 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 ADM4850/ADM4854 Timing Specifications ........................... 4 ADM4851/ADM4855 Timing Specifications ........................... 4 ADM4852/ADM4856 Timing Specifications ........................... 5 ADM4853/ADM4857 Timing Specifications ........................... 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 9 Test Circuits ..................................................................................... 11 Switching Characteristics .............................................................. 12 Theory of Operation ...................................................................... 13 Slew Rate Control ....................................................................... 13 Receiver Input Filtering ............................................................. 13 Half-Duplex/Full Duplex Operation ....................................... 13 High Receiver Input Impedance .............................................. 14 Three-State Bus Connection ..................................................... 14 Shutdown Mode ......................................................................... 14 Fail-Safe Operation .................................................................... 14 Current Limit and Thermal Shutdown ................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 16 Automotive Product ................................................................... 16 REVISION HISTORY 5/16—Rev. E to Rev. F Changes to Figure 1 .......................................................................... 1 Reformatted and Changes to Pin Configuration and Function Descriptions Section ........................................................................ 7 Added Figure 6, Renumbered Sequentially .................................. 8 2/16—Rev. D to Rev. E Changes to Figure 1 and General Description Section ............... 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 and Table 4 ....................................................... 4 Changes to Table 5 and Table 6 ....................................................... 5 Changes to Figure 3, Figure 4, and Table 8 Caption .................... 7 Added Table 9; Renumbered Sequentially .................................... 7 Changes to Figure 5 and Table 10 Caption ................................... 8 Changes to Figure 6 Caption ........................................................... 9 Changes to Figure 14 Caption and Figure 15 Caption .............. 10 Changes to Figure 21 Caption and Figure 23 Caption .............. 11 Changed Circuit Description Section to Theory of Operation Section .............................................................................................. 13 Changes to Figure 28 ...................................................................... 13 Changes to the Three-State Bus Connection Section and the Shutdown Mode Section ................................................................ 14 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 1/12—Rev. C to Rev. D Change to Features Section .............................................................. 1 Changes to Ordering Guide .......................................................... 15 Added Automotive Products Section .......................................... 15 1/11—Rev. B to Rev. C Change to Table 8, Pin 3 Description ............................................. 7 Changes to Figure 29...................................................................... 12 Changes to Ordering Guide .......................................................... 15 7/09—Rev. A to Rev. B Added MSOP Package ....................................................... Universal Changes to Table 2 ............................................................................. 3 Changes to Table 7 ............................................................................. 6 Inserted Figure 4; Renumbered Sequentially ................................ 7 Moved Typical Performance Characteristics Section ................... 8 Changes to Figure 24 and Figure 27 ............................................ 11 Changes to Figure 29...................................................................... 12 Change to Shutdown Mode Section............................................. 13 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 4/09—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 15 10/04—Revision 0: Initial Version

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Data Sheet ADM4850 to ADM4857 Rev. F | Page 3 of 16 SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage VOD VCC V R = ∞, see Figure 19 1 2.0 5 V R = 50 Ω (RS-422), see Figure 19 1.5 5 V R = 27 Ω (RS-485), see Figure 19 Differential Output Voltage over Common- Mode Range |VOD3| 1.5 5 V VTST = −7 V to +12 V, see Figure 20 Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 19 Common-Mode Output Voltage VOC 3 V R = 27 Ω or 50 Ω, see Figure 19 Δ|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 19 Output Short-Circuit Current −7 V < VOUT < +12 V VOUT = High −200 +200 mA VOUT = Low −200 +200 mA DRIVER INPUT LOGIC CMOS Input Logic Threshold Low 0.8 V High 2.0 V CMOS Logic Input Current (DI) ±1 µA DE Input Resistance to GND 220 kΩ RECEIVER Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V < VOC < +12 V Input Hysteresis 20 mV −7 V < VOC < +12 V Input Resistance (A, B) 96 150 kΩ −7 V < VOC < +12 V Input Current (A, B) 0.125 mA VIN = 12 V −0.1 mA VIN = −7 V CMOS Logic Input Current (RE) ±1 µA CMOS Output Voltage Low 0.4 V IOUT = 4 mA High 4.0 V IOUT = −4 mA Output Short-Circuit Current 7 85 mA VOUT = GND or VCC Three-State Output Leakage Current ±2 µA 0.4 V ≤ VOUT ≤ 2.4 V POWER SUPPLY CURRENT 115 kbps Options (ADM4850/ADM4854) 5 µA DE = 0 V, RE = VCC (shutdown) 36 60 µA DE = 0 V, RE = 0 V 100 160 µA DE = VCC 500 kbps Options (ADM4855) 5 µA DE = 0 V, RE = VCC (shutdown) 80 120 µA DE = 0 V, RE = 0 V 120 200 µA DE = VCC 2.5 Mbps Options (ADM4852/ADM4856) 5 µA DE = 0 V, RE = VCC (shutdown) 250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = VCC 10 Mbps Options (ADM4853/ADM4857) 5 µA DE = 0 V, RE = VCC (shutdown) 250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = VCC 1 Guaranteed by design.

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ADM4850 to ADM4857 Data Sheet Rev. F | Page 4 of 16 ADM4850/ADM4854 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 115 kbps Propagation Delay tPLH, tPHL 600 2500 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 70 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 600 2400 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 2000 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4850 only) Disable Time tLZ, tHZ 2000 ns RL = 500 Ω, CL = 15 pF, see Figure 22 and Figure 27 (ADM4850 only) Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4850 only) RECEIVER Propagation Delay tPLH, tPHL 400 1000 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 255 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4850 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4850 only) Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 (ADM4850 only) Time to Shutdown 50 330 3000 ns ADM4850 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4851/ADM4855 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 500 kbps Propagation Delay tPLH, tPHL 250 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 40 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 200 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 1000 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4851 only) Disable Time tLZ, tHZ 1000 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4851 only) Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4851 only) RECEIVER Propagation Delay tPLH, tPHL 400 1000 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 250 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4851 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4851 only) Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 (ADM4851 only) Time to Shutdown 50 330 3000 ns ADM4851 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.

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Data Sheet ADM4850 to ADM4857 Rev. F | Page 5 of 16 ADM4852/ADM4856 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 5. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 2.5 Mbps Propagation Delay tPLH, tPHL 50 180 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 50 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 140 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 180 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4852 only) Disable Time tLZ, tHZ 180 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4852 only) Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4852 only) RECEIVER Propagation Delay tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 50 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4852 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4852 only) Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 (ADM4852 only) Time to Shutdown 50 330 3000 ns ADM4852 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4853/ADM4857 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 6. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 10 Mbps Propagation Delay tPLH, tPHL 0 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 10 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 35 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4853 only) Disable Time tLZ, tHZ 35 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4853 only) Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4853 only) RECEIVER Propagation Delay tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 30 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4853 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4853 only) Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 (ADM4853 only) Time to Shutdown 50 330 3000 ns ADM4853 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.

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ADM4850 to ADM4857 Data Sheet Rev. F | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating VCC to GND 6 V Digital Input/Output Voltage (DE, RE, DI, RO) −0.3 V to VCC + 0.3 V Driver Output/Receiver Input Voltage −9 V to +14 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C θJA Thermal Impedance 8-Lead SOIC 110°C/W 8-Lead LFCSP 62°C/W 8-Lead MSOP 133.1°C/W Lead Temperature Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

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Data Sheet ADM4850 to ADM4857 Rev. F | Page 7 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. ADM4850, 8-Lead MSOP, Pin Configuration Figure 4. ADM4850/ADM4851/ADM4852/ADM4853, 8-Lead SOIC, Pin Configuration Table 8. ADM4850/ADM4851/ADM4852/ADM4853, 8-Lead MSOP and 8-Lead SOIC, Pin Function Descriptions Pin No. Mnemonic Description 1 RO Receiver Output. When RO is enabled and (A − B) ≥ −30 mV, RO is high. When RO is enabled and (A − B) ≤ −200 mV, RO is low. 2 RE Receiver Output Enable. A low level on RE enables the receiver output (RO). A high level on RE places RO into a high impedance state. 3 DE Driver Output Enable. A high level on DE enables the driver differential outputs (A and B). A low level on DE places the driver differential outputs into a high impedance state. 4 DI Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low. 5 GND Ground. 6 A Noninverting Receiver Input A/Noninverting Driver Output A. 7 B Inverting Receiver Input B/Inverting Driver Output B. 8 VCC 5 V Power Supply. RO VCC DI GND RE B DE A 1 2 3 4 8 7 6 5 04 93 1- 00 2 ADM4850 (Not to Scale) TOP VIEW VCC1 A 8 GND4 5 ADM4850/ ADM4851/ ADM4852/ ADM4853 TOP VIEW (Not to Scale) RO 2 B7 DI 63DE RE 04 93 1- 10 4

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ADM4850 to ADM4857 Data Sheet Rev. F | Page 8 of 16 Figure 5. ADM4850/ADM4852/ADM4853, 8-Lead LFCSP, Pin Configuration Table 9. ADM4850/ADM4852/ADM4853, 8-Lead LFCSP, Pin Function Descriptions Pin No. Mnemonic Description 1 RO Receiver Output. When RO is enabled and (A − B) ≥ −30 mV, RO is high. When RO is enabled and (A − B) ≤ −200 mV, RO is low. 2 RE Receiver Output Enable. A low level on RE enables the receiver output (RO). A high level on RE places RO into a high impedance state. 3 DE Driver Output Enable. A high level on DE enables the driver differential outputs (A and B). A low level places the driver differential outputs into a high impedance state. 4 DI Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low. 5 GND Ground. 6 A Noninverting Receiver Input A/Noninverting Driver Output A. 7 B Inverting Receiver Input B/Inverting Driver Output B. 8 VCC 5 V Power Supply. EPAD Exposed Pad. The exposed paddle on the underside of the package must be soldered to the ground plane to increase the reliability of the solder joints and to maximize the thermal capability of the package. Figure 6. ADM4854/ADM4855/ADM4856/ADM4857, 8-Lead SOIC, Pin Configuration Table 10. ADM4854/ADM4855/ADM4856/ADM4857, 8-Lead SOIC, Pin Function Descriptions Pin No. Mnemonic Description 1 VCC 5 V Power Supply. 2 RO Receiver Output. When RO is enabled and (A − B) ≥ −30 mV, RO is high. When RO is enabled and (A − B) ≤ −200 mV, RO is low. 3 DI Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low. 4 GND Ground. 5 Y Noninverting Driver Output. 6 Z Inverting Driver Output. 7 B Inverting Receiver Input. 8 A Noninverting Receiver Input. 04 93 1- 02 9 NOTES 1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE PACKAGE SHOULD BE SOLDERED TO THE GROUND PLANE TO INCREASE THE RELIABILITY OF THE SOLDER JOINTS AND TO MAXIMIZE THE THERMAL CAPABILITY OF THE PACKAGE. RO RE DE DI B VCC ADM4850/ADM4852/ADM4853 A GND 3 4 1 2 6 5 8 7TOP VIEW (Not to Scale) VCC 1 A8 GND 4 Y5 ADM4854/ ADM4855/ ADM4856/ ADM4857 TOP VIEW (Not to Scale) RO 2 B7 DI Z63 04 93 1- 10 6

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Data Sheet ADM4850 to ADM4857 Rev. F | Page 9 of 16 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Unloaded Supply Current vs. Temperature (ADM4850/ADM4853) Figure 8. Receiver Output Current vs. Receiver Output Low Voltage Figure 9. Receiver Output Current vs. Receiver Output High Voltage Figure 10. Receiver Output Low Voltage vs. Temperature Figure 11. Receiver Output High Voltage vs. Temperature Figure 12. Driver Output Current vs. Differential Output Voltage 400 0 50 100 150 200 250 300 350 –50 –25 0 25 50 75 100 125 04 93 1- 01 4 TEMPERATURE (°C) U N LO A D ED S U PP LY C U R R EN T (μ A ) ADM4853: DE = VCC ADM4853: DE = GND ADM4850: DE = VCC ADM4850: DE = GND 04 93 1- 01 5 50 0 5 10 15 20 25 30 35 40 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 RECEIVER OUTPUT LOW VOLTAGE (V) R EC EI VE R O U TP U T C U R R EN T (m A ) 04 93 1- 01 6 5 0 –5 –10 –15 –20 3.5 4.0 4.5 5.0 5.5 RECEIVER OUTPUT HIGH VOLTAGE (V) R EC EI VE R O U TP U T C U R R EN T (m A ) –50 –25 0 25 50 75 100 125 04 93 1- 01 7 0.40 0.15 0.20 0.25 0.30 0.35 TEMPERATURE (°C) O U TP U T LO W V O LT A G E (V ) –50 –25 0 25 50 75 100 125 04 93 1- 01 8 4.6 4.0 4.1 4.2 4.3 4.4 4.5 TEMPERATURE (°C) O U TP U T H IG H V O LT A G E (V ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04 93 1- 01 9 90 0 10 20 30 40 50 60 70 80 DIFFERENTIAL OUTPUT VOLTAGE (V) D R IV ER O U TP U T C U R R EN T (m A )

ADM4857ARZ Reviews

Average User Rating
5 / 5 (177)
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Kend*****Pitts

December 22, 2019

All resistors exactly -0.01%. Pretty good.

Kar*****Black

December 20, 2019

Great capacitors. very fast post very good communication.

Zaid*****rison

December 16, 2019

This seems to be a good set. I'll update more when I've tested these and can review their working quality.

Alan*****tersen

December 3, 2019

I like this way to add a project, choose existing project to add components. I use this method frequently to keep track of my projects. Thanks Heisener!

Bish*****enitez

September 24, 2019

Perfect, functional, arrived a weeks earlier, excellent Seller. Recommended

Liv*****Issac

August 18, 2019

Fantastic transaction, very fast delivery. Highly recommended. Thank you.

Amaya*****aswamy

June 22, 2019

EVERY OK ...GOOD ITEM AND SUPERFAST SHIPPING

Maxim***** Walter

March 7, 2019

Heisener is on a very short list of companies I highly recommend without any hesitation. From stock, pricing, ease of ordering and great service, they have it all.

Mack*****e Gade

February 8, 2019

Arrived safely. All OK. Thanks

Juni*****Maddox

February 6, 2019

They work great and I hope to find more used for the extra ones.

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We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

ADM4857ARZ Packaging

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