Contact Us
SalesDept@heisener.com 0755-83210559 ext. 805

ADM691ANZ

hotADM691ANZ

ADM691ANZ

For Reference Only

Part Number ADM691ANZ
Manufacturer Analog Devices Inc.
Description IC MPU SUPER 4.65 100MA 16DIP
Datasheet ADM691ANZ Datasheet
Package 16-DIP (0.300", 7.62mm)
In Stock 962 piece(s)
Unit Price $ 3.9200 *
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 29 - Nov 3 (Choose Expedited Shipping)
Request for Quotation

Part Number # ADM691ANZ (PMIC - Supervisors) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For ADM691ANZ specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add ADM691ANZ with quantity into BOM. Heisener.com does NOT require any registration to request a quote of ADM691ANZ.

ADM691ANZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - PMIC - Supervisors
Datasheet ADM691ANZDatasheet
Package16-DIP (0.300", 7.62mm)
Series-
TypeBattery Backup Circuit
Number of Voltages Monitored1
OutputOpen Drain, Push-Pull
ResetActive High/Active Low
Reset Timeout35 ms Minimum
Voltage - Threshold4.65V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeThrough Hole
Package / Case16-DIP (0.300", 7.62mm)
Supplier Device Package16-PDIP

ADM691ANZ Datasheet

Page 1

Page 2

REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADM691A/ADM693A/ADM800L/M One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 Microprocessor Supervisory Circuits FUNCTIONAL BLOCK DIAGRAM CHIP ENABLE OUTPUT CONTROL VBATT VCC CEIN OSC IN OSC SEL WATCHDOG INPUT (WDI) POWER FAIL INPUT (PFI) 1VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M) ADM691A/ADM693A ADM800L/ADM800M 1.25V WATCHDOG TIMER RESET & WATCHDOG TIMEBASE RESET & GENERATOR 4.65V1 BATT ON LOW LINE VOUT CEOUT RESET RESET WATCHDOG OUTPUT (WDO) POWER FAIL OUTPUT (PFO) WATCHDOG TRANSITION DETECTOR FEATURES Low Power Consumption: Precision Voltage Monitor 62% Tolerance on ADM800L/M Reset Time Delay—200 ms, or Adjustable 1 mA Standby Current Automatic Battery Backup Power Switching Fast Onboard Gating of Chip Enable Signals Also Available in TSSOP Package (ADM691A) APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical mP Power Monitoring GENERAL DESCRIPTION The ADM691A/ADM693A/ADM800L/ADM800M family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warning. The family of products provides an upgrade for the MAX691A/93A/800M family of products. All parts are available in 16-pin DIP and SO packages. The ADM691A is also available in a space-saving TSSOP package. The following functionality is provided: 1. Power-on reset output during power-up, power-down and brownout conditions. The circuitry remains operational with VCC as low as 1 V. 2. Battery backup switching for CMOS RAM, CMOS micro- processor or other low power logic. 3. A reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. A 1.25 V threshold detector for power fail warning, low bat- tery detection, or to monitor a power supply other than +5 V. VBATT VCC CMOS RAM CEIN OSC IN OSC SEL BAT ON LOW LINE VOUT CEOUT RESET RESET PFO WDI VCC WDO I/O LINE NMI A0–A15 µP POWER µP ADDRESS DECODE ADM691A ADM693A ADM800L ADM800M GND PFI BATTERY 0.1µF +5V NC R2 R1 INPUT POWER 7805 SYSTEM STATUS INDICATORS Figure 1. Typical Application

Page 3

ADM691A/ADM693A/ADM800L/M–SPECIFICATIONS –2– REV. 0 (VCC = 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) VBATT = +2.8 V, TA = TMIN to TMAX unless otherwise noted) Parameter Min Typ Max Unit Test Conditions/Comments BATTERY BACKUP SWITCHING VCC, VBATT Operating Voltage Range 0 5.5 V VOUT Output Voltage VCC – 0.05 VCC – 0.02 V IOUT = 25 mA VCC – 0.3 VCC – 0.2 V IOUT = 250 mA VCC to VOUT Output Resistance 0.8 1.2 Ω VCC = 4.5 V VOUT in Battery Backup Mode VBATT – 0.3 V VBATT = 4.5 V, IOUT = 20 mA VBATT – 0.25 V VBATT = 2.8 V, IOUT = 10 mA VBATT – 0.15 V VBATT = 2.0 V, IOUT = 5 mA VBATT to VOUT Output Resistance 12 Ω VBATT = 4.5 V 20 Ω VBATT = 2.8 V 25 Ω VBATT = 2.0 V Supply Current (Excludes IOUT) 70 100 µA VCC > (VBATT – 1 V) Supply Current in B. Backup (Excludes IOUT) 0.04 1 µA VCC < (VBATT – 1.2 V), VBATT = 2.8 V Battery Standby Current 5.5 V > VCC > VBATT + 0.2 V (+ = Discharge, – = Charge) –0.1 +0.02 µA (VBATT +0.2 V) < VCC , TA = +25°C –1.0 +0.02 µA (VBATT +0.2 V) < VCC Battery Switchover Threshold VBATT + 0.03 V Power Up VCC–VBATT VBATT – 0.03 V Power Down Battery Switchover Hysteresis 60 mV BATT ON Output Voltage Low 0.1 0.4 V ISINK = 3.2 mA 0.7 1.5 V ISINK = 25 mA BATT ON Output Short Circuit Current 60 mA Sink Current 1 15 100 µA Source Current RESET AND WATCHDOG TIMER Reset Voltage Threshold ADM691A, ADM800L 4.5 4.65 4.75 V ADM693A, ADM800M 4.25 4.40 4.50 V ADM800L, VCC Falling 4.55 4.70 V TA = +25°C ADM800M, VCC Falling 4.3 4.45 V TA = +25°C Reset Threshold Hysteresis 15 mV VCC to RESET Delay 80 µs Power Down LOW LINE to RESET Delay 800 ns Reset Timeout Period Internal Oscillator 140 200 280 ms Power Up Reset Timeout Period External Clock 2048 Cycles Power Up Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period 70 100 140 ms Short Period Watchdog Timeout Period, External Clock 4096 Cycles Long Period 1024 Cycles Short Period Minimum WDI Input Pulse Width 100 ns VIL = 0.4, VIH = 0.75 × VCC RESET Output Voltage 0.004 0.3 V ISINK = 50 µA, VCC = 1 V, VBATT = 0 V 0.1 0.4 V ISINK = 3.2 mA, VCC = 4.25 V 3.5 V ISOURCE = 1.6 mA, VCC = 5 V RESET Output Short Circuit Current 7 20 mA RESET Output Voltage Low 0.1 0.4 V ISINK = 3.2 mA LOW LINE Output Voltage 0.4 V ISINK = 3.2 mA, VCC = 4.25 V 3.5 V ISOURCE = 1 µA, VCC = 5 V LOW LINE Short Circuit Source Current 1 15 100 µA WDO Output Voltage 0.4 V ISINK = 3.2 mA, VCC = 4.25 V 3.5 V ISOURCE = 500 µA, VCC = 5 V WDO Short Circuit Source Current 3 10 mA WDI Input Threshold Logic Low 0.8 V Logic High 0.75 × VCC V WDI Input Current –50 –10 µA WDI = 0 V 20 50 µA WDI = VOUT POWER FAIL DETECTOR PFI Input Threshold ADM69xA 1.2 1.25 1.3 V VCC = 5 V PFI Input Threshold ADM800L/M 1.225 1.25 1.275 V VCC = 5 V PFI Input Current ± 0.01 ± 25 nA PFO Output Voltage 0.4 V ISINK = 3.2 mA 3.5 ISOURCE = 1 µA PFO Short Circuit Source Current 1 15 100 µA PFI to PFO Delay 25 µs VIN = –20 mV 60 µs VIN = 20 mV

Page 4

–3–REV. 0 ADM691A/ADM693A/ADM800L/M Parameter Min Typ Max Units Test Conditions/Comments CHIP ENABLE GATING CEIN Leakage Current ±0.005 ±1 µA Disable Mode CEIN to CEOUT Resistance 40 150 Ω Enable Mode CEIN to CEOUT Propagation Delay 6 10 ns RIN = 50 Ω, CLOAD = 50 pF CEOUT Short-Circuit Current 0.1 0.75 2.0 mA Disable Mode, CEOUT = 0 V CEOUT Output Voltage 3.5 V VCC = 5 V, IOUT = –100 µA 2.7 V VCC = 0 V, VBATT = 2.8 V, IOUT = 1 µA RESET to CEOUT Propagation Delay 12 µs Power Down OSCILLATOR OSC IN Input Current 0.1 ±5 µA OSC SEL = 0 V OSC In Input Pullup Current 10 100 µA OSC SEL = VOUT or Floating OSC SEL Input Pullup Current 10 100 µA OSC SEL = 0 V OSC IN Frequency Range 500 kHz OSC SEL = 0 V OSC IN Threshold Voltage VOUT – 0.4 VOUT – 0.6 V VIH 3.65 2.00 V VIL OSC IN Frequency with Ext Capacitor 100 kHz OSC SEL = 0 V, COSC = 47 pF NOTES 1Either VCC or VBATT can be 0 V if the other > +2.0 V. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (TA = 25°C unless otherwise noted) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V Input Current VCC (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA VCC (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA VBATT (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA VBATT (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW θϑA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .110°W Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. Table I. Product Selection Table Power On Low VCC Watchdog Battery Backup Base Drive Chip Enable Part No. Reset Time Threshold Timeout Switching Ext PNP Signals ADM691A 200 ms or Adj. 4.65 V ± 3% 100 ms, 1.6 s, Adj. Yes Yes Yes ADM693A 200 ms or Adj. 4.4 V ± 3% 100 ms, 1.6 s, Adj. Yes Yes Yes ADM800M 200 ms or Adj. 4.4 V ± 2% 100 ms, 1.6 s, Adj. Yes Yes Yes ADM800L 200 ms or Adj. 4.65 V ± 2% 100 ms, 1.6 s, Adj. Yes Yes Yes ORDERING GUIDE Temperature Package Model Range Option ADM691AAN –40°C to +85°C N-16 ADM691AARN –40°C to +85°C R-16N ADM691AARW –40°C to +85°C R-16W ADM691AARU –40°C to +85°C RU-16 ADM693AAN –40°C to +85°C N-16 ADM693AARN –40°C to +85°C R-16N ADM693AARW –40°C to +85°C R-16W ADM800LAN –40°C to +85°C N-16 ADM800LARN –40°C to +85°C R-16N ADM800LARW –40°C to +85°C R-16W ADM800MAN –40°C to +85°C N-16 ADM800MARN –40°C to +85°C R-16N ADM800MARW –40°C to +85°C R-16W

Page 5

ADM691A/ADM693A/ADM800L/M –4– REV. 0 PIN DESCRIPTIONS Pin Mnemonic Function 1 VBATT Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is not used. 2 VOUT Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest poten- tial. When VCC is higher than VBATT and is also higher than the reset threshold, VCC is switched to VOUT. When VCC is lower than VBATT and below the reset threshold, VBATT is switched to VOUT. Connect VOUT to VCC if a backup battery is not being used. 3 VCC Power Supply Input; +5 V. 4 GND 0 V. Ground reference for all signals. 5 BATT ON Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output may also be used to drive the base (via a resistor) of an ex- ternal PNP transistor to increase the output current above the 250 mA rating of VOUT. 6 LOW LINE Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. 7 OSC IN Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external ca- pacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period. (See Table II and Figure 4.) 8 OSC SEL Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil- lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 10 µA internal pullup. 9 PFI Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than 1.25 V, PFO goes low. Connect PFI to GND or VOUT when not used. 10 PFO Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.25 V. 11 WDI Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch- dog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply. 12 CEOUT Output. CEOUT goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when reset is asserted, CEOUT will remain low for 15 µs or until CEIN goes high, whichever occurs first. 13 CEIN Chip Enable Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. 14 WDO Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI is unconnected. 15 RESET Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after VCC goes above the reset threshold. 16 RESET Logic Output. RESET is an open-drain output. It is the inverse of RESET. PIN CONFIGURATIONS VBATT CEIN OSC IN OSC SEL BATT ON LOW LINE VOUT CEOUT RESET RESET PFO WDI VCC WDO GND PFI 14 13 12 11 16 15 10 98 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) ADM691A ADM693A ADM800L ADM800M

Page 6

ADM691A/ADM693A/ADM800L/M –5–REV. 0 Typical Performance Curves– TEMPERATURE – °C –50 125–25 0 25 50 75 100 100 20 V C C S U P P L Y C U R R E N T – µ A 70 40 30 90 80 60 50 Figure 2. ICC vs. Temperature: Normal Operation TEMPERATURE – °C –50 90–30 –10 10 30 50 70 60 30 B A T T E R Y S U P P L Y C U R R E N T – n A 45 40 35 55 50 Figure 3. IBATT vs. Temperature: Battery Backup Mode TEMPERATURE – °C –50 125–25 0 25 50 75 100 80 20 C E O N R E S IS T A N C E – Ω 50 40 30 70 60 Figure 4. Chip Enable ON-Resistance vs. Temperature TEMPERATURE – °C –50 90–30 –10 10 30 50 70 1.2 0.6 V C C T O V O U T O N R E S IS T A N C E – R 0.9 0.8 0.7 1.1 1.0 Figure 5. VCC to VOUT ON-Resistance vs. Temperature IOUT – mA 80 0 40 120 V C C T O V O U T – m V 60 80 100 70 40 30 20 10 60 50 ROUT = 0.67Ω Figure 6. VCC to VOUT Voltage Drop vs. Current IOUT – mA 70 0 4 10 V B A T T T O V O U T – m V 6 8 60 50 40 20 10 30 ROUT = 7Ω Figure 7. VBATT to VOUT Voltage Drop vs. Current

Page 7

ADM691A/ADM693A/ADM800L/M –6– REV. 0 VCC – V 0 5.00.5 1.0 1.5 2.0 2.5 3.0 10 0 I B A T T – µ A 7 2 1 9 8 6 5 4 3 3.5 4.0 4.5 VBATT = 2.8V Figure 8. Battery Current vs. Input Supply Voltage COSC – pF 100 10 0.1 10 1k100 W A T C H D O G A N D R E S E T T IM E O U T P E R IO D – s 1 LONG WATCHDOG TIMEOUT PERIOD SHORT WATCHDOG TIMEOUT PERIOD RESET ACTIVE TIMEOUT PERIOD = > Figure 9. Watchdog and Reset Timeout Period vs. OSC IN Capacitor TEMPERATURE – °C –50 125–25 0 25 50 75 100 7.0 4.0 P R O P A G A T IO N D E L A Y – n s 5.5 5.0 4.5 6.5 6.0 Figure 10. Chip Enable Propagation Delay vs. Temperature LOAD CAPACITANCE – pF 0 30050 100 150 200 250 16 0 10 4 2 14 12 8 6 P R O P A G A T IO N D E L A Y – n s Figure 11. Chip Enable Propagation Delay vs. Load Capacitance TEMPERATURE – °C –50 90–30 –10 10 30 50 70 230 170 R E S E T D E L A Y – m s 200 220 210 190 180 Figure 12. Reset Timeout Relay vs. Temperature TEMPERATURE – °C –50 130–20 10 40 70 100 1200 0 R E S E T O U T P U T R E S IS T A N C E – Ω 600 1000 800 400 200 VCC = 5V, VBATT = 2.8V SOURCING CURRENT VCC = 0V, VBATT = 2.8V SINKING CURRENT Figure 13. RESET Output Resistance vs. Temperature

Page 8

ADM691A/ADM693A/ADM800L/M –7–REV. 0 10 0% 100 90 400ms1V Figure 14. RESET Output Voltage vs. Supply 10 0% 100 90 10µs1V Figure 15. RESET Response Time POWER FAIL RESET OUTPUT RESET is an active low output that provides a reset signal to the Microprocessor whenever VCC is at an invalid level. When VCC falls below the reset threshold, the RESET output is forced low. The reset voltage threshold is 4.65 V (ADM691A/ ADM800L) or 4.4 V (ADM693A/ADM800M). On power-up RESET will remain low for 200 milliseconds after VCC rises above the appropriate reset threshold. This allows time for the power supply and microprocessor to stabilize. On power- down, the RESET output remains low with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shut- down condition. If RESET is required to be low for voltages be- low 1 V, this may be achieved by connecting a pull-down resistor on the RESET line. The resistor will help maintain RESET low down to VCC = 0 V. Note that this is only necessary if VBATT is below 2 V. With battery voltages ≥2 V RESET will function cor- rectly with VCC from 0 V to +5.5 V. This reset active time is adjustable by using an external oscillator or by connecting an external capacitor to the OSC IN pin. Refer to Table II. The guaranteed minimum and maximum thresholds of the ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaran- teed thresholds of the ADM693A/ADM800M are 4.25 V and 4.5 V. The ADM691A/ADM800L is therefore compatible with 5 V supplies with a +10%, –5% tolerance while the ADM693A/ ADM800M is compatible with 5 V ± 10% supplies. In addition to RESET an active high RESET output is provided. This is the complement of RESET and is useful for processors requiring an active high RESET signal. Watchdog Timer Reset The watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a reset pulse is generated. The watch- dog timeout period may be configured for either a fixed “short” 100 ms or a “long” 1.6 second timeout period or for an adjust- able timeout period. Note that even if the short timeout period is selected, the first time out immediately following a reset is 1.6 sec. This is to allow additional time for the microprocessor to regain control following a reset. The watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on WDI or by VCC falling be- low the reset threshold. The normal (short) timeout period becomes effective following the first transition of WDI after reset has gone inactive. The watchdog timeout period restarts with each transition on the WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be is- sued after each timeout period (1.6 seconds). The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). If floating, an internal resistor network biases WDI to around 1.6 V. CHIP ENABLE OUTPUT CONTROL VBATT VCC CEIN OSC IN OSC SEL WATCHDOG INPUT (WDI) POWER FAIL INPUT (PFI) 1VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M) ADM691A/ADM693A ADM800L/ADM800M 1.25V WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER RESET & WATCHDOG TIMEBASE RESET & GENERATOR 4.65V1 BATT ON LOW LINE VOUT CEOUT RESET RESET WATCHDOG OUTPUT (WDO) POWER FAIL OUTPUT (PFO) Figure 16. Functional Block Diagram Watchdog Output (WDO) The Watchdog Output WDO provides a status output that goes low if the watchdog timer “times out” and remains low until set high by the next transition on the watchdog input. WDO is also set high when VCC goes below the reset threshold. If WDI re- mains high or low indefinitely, RESET and RESET will gener- ate 200 ms pulses every 1.6 sec.

Page 9

ADM691A/ADM693A/ADM800L/M –8– REV. 0 Changing the Watchdog and Reset Timeout The watchdog and reset timeout periods may be controlled us- ing OSC SEL and OSC IN. Please refer to Table II. With both these inputs floating (or connected to VOUT) as in Figure 16, the reset timeout is fixed at 200 ms and the watchdog timeout is fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure 16, the reset timeout period remains at 200 ms but a short (100 ms) watchdog timeout period is selected (except immedi- ately following a reset where it reverts to 1.6 sec). By connecting OSC SEL to GND it is possible to select alternative timeout pe- riods by either connecting a capacitor from OSC IN to GND or by overdriving OSC IN with an external clock. With an external capacitor, the watchdog timeout period is Twd (ms) = 600 (C/47 pF) and the reset active period is Treset (ms) = 1200 (C/47 pF) With an external clock connected to OSC IN, the timeout periods become Twd = 1024 (1/fCLK) Treset = 2048 (1/fCLK) Battery-Switchover Section During normal operation with VCC higher than the reset thresh- old and higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor switch. This switch has a typi- cal on-resistance of 0.75 Ω and can supply up to 250 mA at the VOUT terminal. VOUT is normally used to drive a RAM memory bank which may require instantaneous currents of greater than 250 mA. If this is the case then a bypass capacitor should be connected to VOUT. The capacitor will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used. If the continuous output current requirement at VOUT exceeds 250 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can drive the base of the external transistor. If VCC drops below VBATT and below the reset threshold, battery backup is selected. A 7 Ω MOSFET switch connects the VBATT input to VOUT. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS cir- cuitry. The supply current in battery backup is typically 0.04 µA. High value capacitors, either standard electrolytic or the farad- size double layer capacitors, can also be used for short-term memory backup. If the battery-switchover section is not used, VBATT should be connected to GND and VOUT should be connected to VCC. When VCC is below the reset threshold, the watchdog function is disabled and WDI goes high impedance as it is disconnected from its internal resistor network. The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100 ms watchdog timeout periods. CEIN RESET RESET VCC CEOUT OSC SEL RESET THRESHOLD 80µs tRS 12µs tRS 80µs Figure 17. RESET and Chip Enable Timing OSC SEL OSC IN 7 8 ADM69_A ADM800_ CLOCK 0 TO 250kHz Figure 18a. External Clock Source OSC SEL OSC IN 7 8 ADM69_A ADM800_ NC NC Figure 18b. Internal Oscillator (1.6 s Watchdog) 7 OSC SEL OSC IN 8 ADM69_A ADM800_ COSC Figure 18c. External Capacitor Table II. Reset Pulse Width and Watchdog Timeout Selections Watchdog Timeout Period OSC SEL OSC IN Normal Immediately After Reset Reset Active Period Low External Clock Input 1024 clks 4096 clks 2048 clks Low External Capacitor 600 ms × C/47 pF 2.4 s × C/47 pF 1200 ms × C/47 pF Floating Low 100 ms 1.6 s 200 ms Floating Floating or VOUT 1.6 s 1.6 s 200 ms

Page 10

ADM691A/ADM693A/ADM800L/M –9–REV. 0 7 OSC SEL OSC IN 8 ADM69_A ADM800_ COSC Figure 18d. Internal Oscillator (100 ms Watchdog) WDI WDO t1 RESET t1 = RESET TIME. t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD. t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET. t1 t1 t2 t3 Figure 19. Watchdog Timing CE Gating and RAM Write Protection All products include memory protection circuitry which ensures the integrity of data in memory by preventing write operations when VCC is at an invalid level. There are two additional pins, CEIN and CEOUT, that control the Chip Enable or Write inputs of CMOS RAM. When VCC is present, CEOUT is a buffered rep- lica of CEIN, with a 5 ns propagation delay. When VCC falls be- low the reset voltage threshold, an internal gate forces CEOUT high, independent of CEIN. CEOUT typically drives the CE, CS, or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when VCC is at an in- valid level. Similar protection of EEPROMs can be achieved by using the CEOUT to drive the Store or Write inputs of an EEPROM, EAROM, or NOVRAM. Power Fail Warning Comparator An additional comparator is provided for early warning of fail- ure in the microprocessor’s power supply. The Power Fail Input (PFI) is compared to an internal +1.25 V reference. The Power Fail Output (PFO) goes low when the voltage at PFI is less than 1.3 V. Typically PFI is driven by an external voltage divider that senses either the unregulated dc input to the system’s 5 V regu- lator or the regulated 5 V output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.25 V several milliseconds before the +5 V power supply falls below the reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shut- down proce- dure executed before power is lost. R2 PFO1.25V POWER FAIL INPUT POWER FAIL OUTPUT R1 INPUT POWER Figure 20. Power Fail Comparator Table III. Input and Output Status in Battery Backup Mode Signal Status VBATT Supply Current is <1 µA. VOUT VOUT is connected to VBATT via an internal PMOS switch. VCC Switchover comparator monitors VCC for active switchover. GND 0 V. BATT ON Logic High. The open circuit voltage is equal to VOUT. LOW LINE Logic Low. OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. PFI The Power Fail Comparator remains active in the battery-backup mode for VCC ≥ VBATT –1.2 V. With VCC lower than this, PFO is forced low. PFO The Power Fail Comparator remains active in the battery-backup mode for VCC ≥ VBATT –1.2 V. With VCC lower than this, PFO is forced low. WDI WDI is ignored. CEOUT Logic High. The open circuit voltage is equal to VOUT. CEIN High Impedance. WDO Logic High. The open circuit voltage is equal to VOUT. RESET Logic Low. RESET High Impedance.

ADM691ANZ Reviews

Average User Rating
5 / 5 (89)
★ ★ ★ ★ ★
5 ★
80
4 ★
9
3 ★
0
2 ★
0
1 ★
0

Write a Review

Not Rated
Thanks for Your Review!

Hal*****Patil

August 21, 2020

quick delivery, received with well packaged, exactly as listed - Thanks

Bray*****Narang

August 17, 2020

Great website. Well organized and easy to search products.

ADM691ANZ Guarantees

Service Guarantee

Service Guarantees

We guarantee 100% customer satisfaction.

Our experienced sales team and tech support team back our services to satisfy all our customers.

Quality Guarantee

Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

ADM691ANZ Packaging

Verify Products
Customized Labels
Professional Packaging
Sealing
Packing
Insepction

ADM691ANZ Related Products

SIT1602BI-71-30E-35.840000E SIT1602BI-71-30E-35.840000E SiTIME, -40 TO 85C, 2016, 20PPM, 3.0V, 3, -, - View
B32669C3155K B32669C3155K EPCOS (TDK), CAP FILM 1.5UF 10% 250VAC AXIAL, Axial, - View
2N7051_D10Z 2N7051_D10Z Fairchild/ON Semiconductor, TRANS NPN DARL 100V 1.5A TO-92, TO-226-3, TO-92-3 (TO-226AA) (Formed Leads), - View
XC6122E650MR-G XC6122E650MR-G Torex Semiconductor Ltd, IC WATCHDOG TIMER SOT-25, SC-74A, SOT-753, - View
MXPLAD18KP130CAE3 MXPLAD18KP130CAE3 Microsemi Corporation, TVS DIODE 209VC 87A PLAD, Nonstandard SMD, - View
TNPW06032K03BEEA TNPW06032K03BEEA Vishay Dale, RES SMD 2.03KOHM 0.1% 1/10W 0603, 0603 (1608 Metric), - View
ESQT-102-02-F-S-310 ESQT-102-02-F-S-310 Samtec Inc., ELEVATED 2MM SOCKETS, -, - View
CA3101E24-5P CA3101E24-5P ITT Cannon, LLC, CONN RCPT 16POS INLINE W/PINS, -, - View
TVS06RK-15-35JN TVS06RK-15-35JN Amphenol Aerospace Operations, CONN PLUG FMALE 37POS GOLD CRIMP, -, - View
D38999/24WB4SA D38999/24WB4SA Souriau, CONN RCPT 4POS JAM NUT W/SCKT, -, - View
D38999/20FJ24PC D38999/20FJ24PC Souriau, CONN RCPT 24POS WALL MNT W/PINS, -, - View
TV06DZ-25-19HE-LC TV06DZ-25-19HE-LC Amphenol Aerospace Operations, CONN PLUG HSG MALE 19POS INLINE, -, - View
Payment Methods
Delivery Services

Quick Inquiry

ADM691ANZ

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

View the Certificates

Do you have any question about ADM691ANZ?

0755-83210559 ext. 805 SalesDept@heisener.com heisener007 3008774228 Send Message

ADM691ANZ Tags

  • ADM691ANZ
  • ADM691ANZ PDF
  • ADM691ANZ datasheet
  • ADM691ANZ specification
  • ADM691ANZ image
  • Analog Devices Inc.
  • Analog Devices Inc. ADM691ANZ
  • buy ADM691ANZ
  • ADM691ANZ price
  • ADM691ANZ distributor
  • ADM691ANZ supplier
  • ADM691ANZ wholesales

ADM691ANZ is Available in