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ADN2806ACPZ

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ADN2806ACPZ

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Part Number ADN2806ACPZ
Manufacturer Analog Devices Inc.
Description IC CLK/DATA REC 622MBPS 32-LFCSP
Datasheet ADN2806ACPZ Datasheet
Package 32-WFQFN Exposed Pad, CSP
In Stock 425 piece(s)
Unit Price $ 17.8069 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 6 - Jul 11 (Choose Expedited Shipping)
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Part Number # ADN2806ACPZ (Clock/Timing - Application Specific) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADN2806ACPZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Clock/Timing - Application Specific
Datasheet ADN2806ACPZDatasheet
Package32-WFQFN Exposed Pad, CSP
Series-
PLLYes
Main PurposeSONET/SDH
InputCML
OutputLVDS
Number of Circuits1
Ratio - Input:Output1:2
Differential - Input:OutputYes/Yes
Frequency - Max622MHz
Voltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case32-WFQFN Exposed Pad, CSP
Supplier Device Package32-LFCSP-WQ (5x5)

ADN2806ACPZ Datasheet

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622 Mbps Clock and Data Recovery IC Data Sheet ADN2806 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved. FEATURES Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 359 mW typical 5 mm × 5 mm, 32-lead LFCSP, Pb free APPLICATIONS BPON ONT SONET OC-12 WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers GENERAL DESCRIPTION The ADN2806 provides the receiver functions for clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2806 automatically locks to 622 Mbps data without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode, TIA preamplifier, and a lim amp can implement a highly integrated, low cost, low power fiber optic receiver. The ADN2806 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM 2 LOL DATAOUTP/ DATAOUTN CLKOUTP/ CLKOUTN ADN2806 2 VCC VEECF1 CF2 PIN NIN VREF BUFFER VCOPHASESHIFTER PHASE DETECT FREQUENCY DETECT DATA RE-TIMING LOOP FILTER LOOP FILTER REFCLKP/REFCLKN (OPTIONAL) 05 83 1- 00 1 Figure 1.

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ADN2806 Rev. C | Page 2 of 20 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Jitter Specifications....................................................................... 3  Output and Timing Specifications ............................................. 4  Absolute Maximum Ratings............................................................ 5  Thermal Characteristics .............................................................. 5  ESD Caution.................................................................................. 5  Timing Characteristics..................................................................... 6  Pin Configuration and Function Descriptions............................. 7  I2C Interface Timing and Internal Register Description............. 8  Jitter Specifications......................................................................... 10  Theory of Operation ...................................................................... 11  Functional Description.................................................................. 13  Frequency Acquisition............................................................... 13  Input Buffer Amplifier............................................................... 13  Lock Detector Operation .......................................................... 13  SQUELCH Modes ...................................................................... 13  I2C Interface ................................................................................ 14  Reference Clock (Optional) ...................................................... 15  Applications Information .............................................................. 17  PCB Design Guidelines ............................................................. 17  Outline Dimensions ....................................................................... 20  Ordering Guide .......................................................................... 20  REVISION HISTORY 4/12—Rev. B to Rev. C Change to General Description Section ........................................ 1 Change to Output Clock Range Parameter, Table 1 .................... 3 Changed Pin 1 from VCC to TEST1 and Pin 32 from VCC to TEST2 Throughout; Changes to Figure 5 and Table 5............ 7 Changes to Table 6 and Table 10..................................................... 9 Changes to Ordering Guide; Updated Outline Dimensions .... 20 5/10—Rev. A to Rev. B Changes to Figure 5 and Table 5......................................................7 Changes to Figure 19...................................................................... 17 2/09—Rev. 0 to Rev. A Updated Outline Dimensions....................................................... 20 Changes to Ordering Guide .......................................................... 20 2/06—Revision 0: Initial Version

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ADN2806 Rev. C | Page 3 of 20 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DATA INPUTS—DC CHARACTERISTICS Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V DATA INPUTS—AC CHARACTERISTICS Data Rate 622 Mbps S11 @ 622 MHz −15 dB Output Clock Range Locked to 622 Mbps input data 622 MHz Input Resistance Differential 100 Ω Input Capacitance 0.65 pF LOSS-OF-LOCK (LOL) DETECT VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time OC-12 200 μs ACQUISITION TIME Lock to Data Mode OC-12 2.0 ms Optional Lock to REFCLK Mode 20.0 ms DATA RATE READBACK ACCURACY Fine Readback In addition to REFCLK accuracy OC-12 100 ppm POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V POWER SUPPLY CURRENT Locked to 622.08 Mbps 109 mA OPERATING TEMPERATURE RANGE –40 +85 °C JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer Bandwidth OC-12 75 130 kHz Jitter Peaking OC-12 0 0.03 dB Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms 0.011 0.026 UI p-p Jitter Tolerance OC-12, 223 − 1 PRBS 30 Hz1 100 UI p-p 300 Hz1 44 UI p-p 25 kHz 2.5 UI p-p 250 kHz1 1.0 UI p-p 1 Jitter tolerance of the ADN2806 at these jitter frequencies is better than what the test equipment is able to measure.

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ADN2806 Rev. C | Page 4 of 20 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High VOH (see Figure 3) 1475 mV Output Voltage Low VOL (see Figure 3) 925 mV Differential Output Swing VOD (see Figure 3) 250 320 400 mV Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV Output Impedance Differential 100 Ω LVDS Outputs’ Timing Rise Time 20% to 80% 115 220 ps Fall Time 80% to 20% 115 220 ps Setup Time TS (see Figure 2), OC-12 760 800 840 ps Hold Time TH (see Figure 2), OC-12 760 800 840 ps I2C INTERFACE DC CHARACTERISTICS LVCMOS Input High Voltage VIH 0.7 VCC V Input Low Voltage VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 μA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 10 SCK Clock Frequency 400 kHz SCK Pulse Width High tHIGH 600 ns SCK Pulse Width Low tLOW 1300 ns Start Condition Hold Time tHD;STA 600 ns Start Condition Setup Time tSU;STA 600 ns Data Setup Time tSU;DAT 100 ns Data Hold Time tHD;DAT 300 ns SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb1 300 ns Stop Condition Setup Time tSU;STO 600 ns Bus Free Time Between a Stop and a Start tBUF 1300 ns REFCLK CHARACTERISTICS Optional lock to REFCLK mode Input Voltage Range @ REFCLKP or REFCLKN VIL 0 V VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 10 160 MHz Required Accuracy 100 ppm LVTTL DC INPUT CHARACTERISTICS Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input High Current IIH, VIN = 2.4 V 5 μA Input Low Current IIL, VIN = 0.4 V −5 μA LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage VOH, IOH = −2.0 mA 2.4 V Output Low Voltage VOL, IOL = +2.0 mA 0.4 V 1 Cb = total capacitance of one bus line in picofarads. If used with Hs-mode devices, faster fall times are allowed.

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ADN2806 Rev. C | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, unless otherwise noted. Table 4. Parameter Rating Supply Voltage (VCC) 4.2 V Minimum Input Voltage (All Inputs) VEE − 0.4 V Maximum Input Voltage (All Inputs) VCC + 0.4 V Maximum Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 32-lead LFCSP, 4-layer board with exposed paddle soldered to VEE, θJA = 28°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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ADN2806 Rev. C | Page 6 of 20 TIMING CHARACTERISTICS CLKOUTP DATAOUTP/ DATAOUTN TS TH 0 58 31 -0 02 Figure 2. Output Timing |VOD| VOH DIFFERENTIAL CLKOUTP/N, DATAOUTP/N VOS VOL 05 83 1- 03 2 Figure 3. Differential Output Specifications SIMPLIFIED LVDS OUTPUT STAGE RLOAD 100Ω 100Ω 5mA 5mA VDIFF 0 58 31 -0 3 3 Figure 4. Differential Output Stage

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ADN2806 Rev. C | Page 7 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 0 5 8 3 1 -0 0 4NOTES 1. NC = NO CONNECT. 2. THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. 1TEST1 2 3 VCC VREF TOP VIEW (Not to Scale) 24 VCC 23 VEE 22 NC 21 SDA 32 T E S T 2 20 SCK 19 SADDR5 18 VCC 17 VEE N C 9 R E F C L K P 1 0 R E F C L K N 1 1 V C C 1 2 V E E 1 3 C F 2 14 C F 1 15 L O L 1 6 NIN 4 PIN 5 NC 6 NC 7 VEE 8 31 V C C 30 V E E 29 D A T A O U T P 28 D A T A O U T N 27 S Q U E L C H 26 C L K O U T P 25 C L K O U T N ADN2806 PIN 1 INDICATOR Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 TEST1 AI Connect to VCC. 2 VCC P Power for Limiting Amplifier, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6 NC No Connect. 7 NC No Connect. 8 VEE P GND for Limiting Amplifier, LOS. 9 NC No Connect. 10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz. 11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz. 12 VCC P VCO Power. 13 VEE P VCO GND. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss-of-Lock Indicator. LVTTL active high. 17 VEE P FLL Detector GND. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 20 SCK DI I2C Clock Input. 21 SDA DI I2C Data Input. 22 NC No Connect. 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. LVDS. 26 CLKOUTP DO Differential Recovered Clock Output. LVDS. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL. 28 DATAOUTN DO Differential Recovered Data Output. LVDS. 29 DATAOUTP DO Differential Recovered Data Output. LVDS. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. 32 TEST2 AI Connect to VCC. Exposed Pad Pad P Connect to GND. Works as a heat sink. 1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

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ADN2806 Rev. C | Page 8 of 20 I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 A5 0 0 0 0 0 X MSB = 1 SET BY PIN 19 0 = WR 1 = RD SLAVE ADDRESS [6...0] R/W CTRL. 05 83 1- 00 7 Figure 6. Slave Address Configuration S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA 05 8 31 -0 0 8 Figure 7. I2C Write Data Transfer S S = START BIT P = STOP BIT A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(M) = LACK OF ACKNOWLEDGE BY MASTER SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M) 05 83 1 -0 09 Figure 8. I2C Read Data Transfer START BIT S STOP BIT PACKACKWR ACK D0D7A0A7A5A6 SLADDR[4...0] SLAVE ADDRESS SUB ADDRESS DATA SUB ADDR[6...1] DATA[6...1] SCK SDA 05 83 1- 01 0 Figure 9. I2C Data Transfer Timing tBUFSDA S S SCK tF tLOW tR tF tHD;STA tHD;DAT tSU;DAT tHIGH tSU;STA tSU;STO tHD;STA tR P S 05 83 1- 0 11 Figure 10. I2C Port Timing Diagram

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ADN2806 Rev. C | Page 9 of 20 Table 6. Internal Register Map1 Reg Name R/W Addr D7 D6 D5 D4 D3 D2 D1 D0 FREQ0 R 0x0 MSB LSB FREQ1 R 0x1 MSB LSB FREQ2 R 0x2 0 MSB LSB MISC R 0x4 x x LOS status Static LOL LOL status Data rate measurement complete x x CTRLA W 0x8 FREF range Data rate/DIV_FREF ratio Measure data rate Lock to reference CTRLB W 0x9 Config LOL Reset MISC[4] System reset 0 Reset MISC[2] 0 0 0 CTRLC W 0x11 0 0 0 0 0 Config LOS SQUELCH mode 0 1 All writeable registers default to 0x00. Table 7. Miscellaneous Register, MISC Static LOL LOL Status Data Rate Measurement Complete D7 D6 D5 D4 D3 D2 D1 D0 x x x 0 = Waiting for next LOL 0 = Locked 0 = Measuring data rate x x 1 = Static LOL until reset 1 = Acquiring 1 = Measurement complete Table 8. Control Register, CTRLA1 FREF Range Data Rate/Div_FREF Ratio Measure Data Rate Lock to Reference D7 D6 D5 D4 D3 D2 D1 D0 0 0 19.44 MHz 0 1 0 1 32 Set to 1 to measure data rate 0 = Lock to input data 0 1 38.88 MHz 0 1 0 1 32 1 = Lock to reference clock 1 0 77.76 MHz 0 1 0 1 32 1 1 155.52 MHz 0 1 0 1 32 1 Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the R section). eference Clock (Optional) Table 9. Control Register, CTRLB Config LOL Reset MISC[4] System Reset Reset MISC[2] D7 D6 D5 D4 D3 D2 D1 D0 0 = LOL pin normal operation 1 = LOL pin is static LOL Write a 1 followed by 0 to reset MISC[4] Write a 1 followed by 0 to reset ADN2806 Set to 0 Write a 1 followed by 0 to reset MISC[2] Set to 0 Set to 0 Set to 0 Table 10. Control Register, CTRLC Config LOS SQUELCH Mode Output Boost D7 D6 D5 D4 D3 D2 D1 D0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 0 = Active high LOS 1 = Active low LOS 0 = Squelch data outputs and clock outputs 1 = Squelch data outputs or clock outputs 0 (Default output swing)

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Alai*****wers

June 8, 2020

I recently became very interested in electronics and I have used several of them. They work great.

Mcke*****Robles

June 2, 2020

Used for a solar project. Working as hoped. I'd buy again.

Pete*****vant

May 31, 2020

Fantastic quality products with fair and prompt shipping. Would save much time crossing all the features. Thank you for all your effort.

Rebe*****Hayer

May 28, 2020

To be honest, I think you are doing an outstanding job.

Rosa*****Chacko

May 21, 2020

Parts received and tested, all can work, thank you

Gabri*****urohit

May 18, 2020

Items as described, quick dispatch, took a while with shipment.

Cayso*****tractor

May 12, 2020

They work great and I hope to find more used for the extra ones.

Mar*****annan

May 5, 2020

They worked great. Not much to say - as far as I can tell they adhere to the specs, and did the job I needed them to. Good transistors for higher current situations.

Gene*****Yates

May 5, 2020

I wish I had come across Heisener first, no one could help me for 2 days. You are now saved into the TOP of my favorites web list. Thank you very much.

Luk*****oke

May 2, 2020

Boundless range of products, ease of search and fast delivery continue to impress. Heisener is always my first stop for electronic components.

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