ADP1755ACPZ-R7

Page 1

Page 2

1.2 A, Low VIN, Low Dropout Linear Regulator Data Sheet ADP1754/ADP1755 FEATURES Maximum output current: 1.2 A Input voltage range: 1.6 V to 3.6 V Low shutdown current: <2 µA Very low dropout voltage: 105 mV at 1.2 A load Initial accuracy: ±1% Accuracy over line, load, and temperature: ±2% 7 fixed output voltage options with soft start 0.75 V to 2.5 V (ADP1754) Adjustable output voltage option with soft start 0.75 V to 3.3 V (ADP1755) High PSRR 65 dB at 1 kHz 65 dB at 10 kHz 54 dB at 100 kHz 23 μV rms at 0.75 V output Stable with small 4.7 µF ceramic output capacitor Excellent load and line transient response Current-limit and thermal overload protection Power-good indicator Logic-controlled enable Reverse current protection APPLICATIONS Server computers Memory components Telecommunications equipment Network equipment DSP/FPGA/microprocessor supplies Instrumentation equipment/data acquisition systems TYPICAL APPLICATION CIRCUITS TOP VIEW (Not to Scale) ADP1754 1 2 3 4 VIN VIN100kΩ 4.7µF 4.7µF VIN = 1.8V VOUT = 1.5V VIN EN 12 11 10 9 VOUT VOUT VOUT SENSE 5 6 7 8 PG GND SS NC PG 16 15 14 13 VIN VIN VOUT VOUT 10nF 07 72 2- 00 1 Figure 1. ADP1754 with Fixed Output Voltage, 1.5 V TOP VIEW (Not to Scale) ADP1755 1 2 3 4 VIN VIN100kΩ 4.7µF 4.7µF VIN = 1.8V VOUT = 0.5V(1 + R1/R2) VIN EN 12 11 10 9 VOUT VOUT VOUT ADJ 5 6 7 8 PG GND SS NC PG 16 15 14 13 VIN VIN VOUT VOUT 10nF R2 R1 07 72 2- 00 2 Figure 2. ADP1755 with Adjustable Output Voltage, 0.75 V to 3.3 V GENERAL DESCRIPTION The ADP1754/ADP1755 are low dropout (LDO) CMOS linear regulators that operate from 1.6 V to 3.6 V and provide up to 1.2 A of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced proprietary architecture, the ADP1754/ ADP1755 provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7 µF ceramic output capacitor. The ADP1754 is available in seven fixed output voltage options. The ADP1755 is the adjustable version, which allows output voltages that range from 0.75 V to 3.3 V via an external divider. The ADP1754/ADP1755 allow an external soft start capacitor to be connected to program the startup. A digital power-good output allows power system monitors to check the health of the output voltage. The ADP1754/ADP1755 are available in a 16-lead, 4 mm × 4 mm LFCSP, making them not only very compact solutions, but also providing excellent thermal performance for applications that require up to 1.2 A of output current in a small, low profile footprint. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

Page 3

ADP1754/ADP1755 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuits ............................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Input and Output Capacitor, Recommended Specifications .. 4 Absolute Maximum Ratings ............................................................ 5 Thermal Data ................................................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 11 Soft Start Function (ADP1754/ADP1755) ............................. 11 Adjustable Output Voltage (ADP1755) ................................... 12 Enable Feature ............................................................................ 12 Power-Good Feature .................................................................. 12 Reverse Current Protection Feature ........................................ 13 Applications Information .............................................................. 14 Capacitor Selection .................................................................... 14 Undervoltage Lockout ............................................................... 15 Current-Limit and Thermal Overload Protection ................. 15 Thermal Considerations ............................................................ 15 PCB Layout Considerations ...................................................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19 REVISION HISTORY 4/14—Rev. F to Rev. G Changes to Figure 1 and Figure 2 ................................................... 1 Change to Table 4 ............................................................................. 5 Changes to Figure 3 and Figure 4 ................................................... 6 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 8/13—Rev. E to Rev. F Changes to Ordering Guide .......................................................... 19 6/13—Rev. D to Rev. E Changed Adjustable Output Voltage Option with Soft Start (ADP1755) from 0.75 V to 3.0 V to 0.75 V to 3.3 V (Throughout) .................................................................................... 1 Updated Outline Dimensions ....................................................... 19 12/12—Rev. C to Rev. D Added Junction Temperature of 150°C, Table 3 ........................... 5 9/12—Rev. B to Rev. C Changes to Absolute Maximum Ratings, Table 3......................... 5 Changes to Ordering Guide .......................................................... 19 2/10—Rev. A to Rev. B Changes to Table 4 ............................................................................ 5 Changes to Ordering Guide .......................................................... 19 4/09—Rev. 0 to Rev. A Changes to Adjustable Output Voltage Accuracy (ADP1755) Parameter, Table 1 ............................................................................. 3 Changes to Table 3 ............................................................................. 5 10/08—Revision 0: Initial Version Rev. G | Page 2 of 20

Page 4

Data Sheet ADP1754/ADP1755 SPECIFICATIONS VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE VIN TJ = −40°C to +125°C 1.6 3.6 V OPERATING SUPPLY CURRENT1 IGND IOUT = 500 μA 90 µA IOUT = 100 mA 400 µA IOUT = 100 mA, TJ = −40°C to +125°C 800 µA IOUT = 1.2 A 1.1 mA IOUT = 1.2 A, TJ = −40°C to +125°C 1.4 mA SHUTDOWN CURRENT IGND-SD EN = GND, VIN = 1.6 V 2 6 µA EN = GND, VIN = 1.6 V, TJ = −40°C to +85°C 30 µA EN = GND, VIN = 3.6 V, TJ = −40°C to +85°C 100 µA OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy (ADP1754) VOUT IOUT = 10 mA −1 +1 % IOUT = 10 mA to 1.2 A −1.5 +1.5 % 10 mA < IOUT < 1.2 A, TJ = −40°C to +125°C −2 +2 % Adjustable Output Voltage Accuracy (ADP1755)2 VADJ IOUT = 10 mA 0.495 0.5 0.505 V IOUT = 10 mA to 1.2 A 0.495 0.505 V 10 mA < IOUT < 1.2 A, TJ = −40°C to +125°C 0.490 0.510 V LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 0.4 V) to 3.6 V, TJ = −40°C to +125°C −0.3 +0.3 %/V LOAD REGULATION3 ∆VOUT/∆IOUT IOUT = 10 mA to 1.2 A, TJ = −40°C to +125°C 0.6 %/A DROPOUT VOLTAGE4 VDROPOUT IOUT = 100 mA, VOUT ≥ 1.8 V 10 mV IOUT = 100 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C 16 mV IOUT = 1.2 A, VOUT ≥ 1.8 V 105 mV IOUT = 1.2 A, VOUT ≥ 1.8 V, TJ = −40°C to +125°C 200 mV START-UP TIME5 tSTART-UP CSS = 0 nF, IOUT = 10 mA 200 µs CSS = 10 nF, IOUT = 10 mA 5.2 ms CURRENT-LIMIT THRESHOLD6 ILIMIT 1.5 2 5 A THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C PG OUTPUT LOGIC LEVEL PG Output Logic High PGHIGH 1.6 V ≤ VIN ≤ 3.6 V, IOH < 1 µA 1.0 V PG Output Logic Low PGLOW 1.6 V ≤ VIN ≤ 3.6 V, IOL < 2 mA 0.4 V PG Output Delay from EN Transition Low to High 1.6 V ≤ VIN ≤ 3.6 V, CSS = 10 nF 5.5 ms PG OUTPUT THRESHOLD Output Voltage Falling PGFALL 1.6 V ≤ VIN ≤ 3.6 V −10 % Output Voltage Rising PGRISE 1.6 V ≤ VIN ≤ 3.6 V −6.5 % EN INPUT EN Input Logic High VIH 1.6 V ≤ VIN ≤ 3.6 V 1.2 V EN Input Logic Low VIL 1.6 V ≤ VIN ≤ 3.6 V 0.4 V EN Input Leakage Current VI-LEAKAGE EN = VIN or GND 0.1 1 µA UNDERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLORISE TJ = −40°C to +125°C 1.58 V Input Voltage Falling UVLOFALL TJ = −40°C to +125°C 1.25 V Hysteresis UVLOHYS TJ = 25°C 100 mV SOFT START CURRENT ISS 1.6 V ≤ VIN ≤ 3.6 V 0.6 0.9 1.2 µA ADJ INPUT BIAS CURRENT (ADP1755) ADJI-BIAS 1.6 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +125°C 10 150 nA SENSE INPUT BIAS CURRENT SNSI-BIAS 1.6 V ≤ VIN ≤ 3.6 V 10 µA Rev. G | Page 3 of 20

Page 5

ADP1754/ADP1755 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VOUT = 0.75 V 23 µV rms 10 Hz to 100 kHz, VOUT = 2.5 V 65 µV rms POWER SUPPLY REJECTION RATIO PSRR VIN = VOUT + 1 V, IOUT = 10 mA 1 kHz, VOUT = 0.75 V 65 dB 1 kHz, VOUT = 2.5 V 56 dB 10 kHz, VOUT = 0.75 V 65 dB 10 kHz, VOUT = 2.5 V 56 dB 100 kHz, VOUT = 0.75 V 54 dB 100 kHz, VOUT = 2.5 V 51 dB 1 Minimum output load current is 500 μA. 2 Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of resistors used. 3 Based on an end-point calculation using 10 mA and 1.2 A loads. See Figure 6 for typical load regulation performance. 4 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.6 V. 5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 95% of its nominal value. 6 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE1 CMIN TA = −40°C to +125°C 3.3 µF CAPACITOR ESR RESR TA = −40°C to +125°C 0.001 0.1 Ω 1 The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with this LDO. Rev. G | Page 4 of 20

Page 6

Data Sheet ADP1754/ADP1755 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VIN to GND −0.3 V to +4.0 V VOUT to GND −0.3 V to VIN EN to GND −0.3 V to VIN SS to GND −0.3 V to VIN PG to GND −0.3 V to +4.0 V SENSE/ADJ to GND −0.3 V to VIN Storage Temperature Range −65°C to +150°C Junction Temperature Range −40°C to +125°C Junction Temperature 150°C Soldering Conditions JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP1754/ADP1755 may be damaged if the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θJA). TJ is calculated using the following formula: TJ = TA + (PD × θJA) Junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified values of θJA are based on a 4-layer, 4 in × 3 in circuit board. Refer to JEDEC JESD51-7 for detailed information about board construction. For more information, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). ΨJB is the junction-to-board thermal characterization parameter with units of °C/W. ΨJB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12 document, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than through a single path as in thermal resistance, θJB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and the power dissipation (PD) using the following formula: TJ = TB + (PD × ΨJB) Refer to the JEDEC JESD51-8 and JESD51-12 documents for more detailed information about ΨJB. THERMAL RESISTANCE θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type θJA ΨJB Unit 16-Lead LFCSP with Exposed Pad (CP-16-23) 42 25.5 °C/W ESD CAUTION Rev. G | Page 5 of 20

Page 7

ADP1754/ADP1755 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO THE GROUND PLANE ON THE BOARD. 07 72 2- 00 3 12 11 10 1 3 4 9 2 65 7 8 16 15 14 13 VIN VIN VIN EN VOUT VO U T VO U T VI N VI N VOUT VOUT SENSE PG G N D SS N C ADP1754 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO THE GROUND PLANE ON THE BOARD. 07 72 2- 00 4 12 11 10 1 3 4 9 2 65 7 8 16 15 14 13 VIN VIN VIN EN VOUT VO U T VO U T VI N VI N VOUT VOUT ADJ PG G N D SS N C ADP1755 TOP VIEW (Not to Scale) Figure 3. ADP1754 Pin Configuration Figure 4. ADP1755 Pin Configuration Table 5. Pin Function Descriptions ADP1754 Pin No. ADP1755 Pin No. Mnemonic Description 1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all five VIN pins must be connected to the source. 4 4 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to VIN. 5 5 PG Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal output voltage, PG immediately transitions low. 6 6 GND Ground. 7 7 SS Soft Start. A capacitor connected to this pin determines the soft start time. 8 8 NC Not Connected. No internal connection. 9 N/A SENSE Sense. This pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. N/A 9 ADJ Adjust. A resistor divider from VOUT to ADJ sets the output voltage. 10, 11, 12, 13, 14 10, 11, 12, 13, 14 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that all five VOUT pins must be connected to the load. 17 (EPAD) 17 (EPAD) Exposed paddle (EPAD) The exposed pad on the bottom of the LFCSP package enhances thermal performance and is electrically connected to GND inside the package. It is recommended that the exposed pad be connected to the ground plane on the board. Rev. G | Page 6 of 20

Page 8

Data Sheet ADP1754/ADP1755 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 1.9 V, VOUT = 1.5 V, IOUT = 10 mA, CIN = 4.7 µF, COUT = 4.7 µF, TA = 25°C, unless otherwise noted. 1.520 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 –40 –5 25 85 125 O U TP U T VO LT A G E (V ) JUNCTION TEMPERATURE (°C) LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A 07 72 2- 00 5 Figure 5. Output Voltage vs. Junction Temperature 1.520 1.515 1.505 1.495 1.510 1.500 1.490 1.485 1.480 10 100 1k 10k O U TP U T VO LT A G E (V ) LOAD CURRENT (mA) 07 72 2- 00 6 Figure 6. Output Voltage vs. Load Current 1.8 3.63.43.23.02.82.62.42.22.0 INPUT VOLTAGE (V) LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A 1.520 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 O U TP U T VO LT A G E (V ) 07 72 2- 00 7 Figure 7. Output Voltage vs. Input Voltage 1200 0 200 400 600 800 1000 –40 –5 25 85 125 G R O U N D C U R R EN T (µ A ) JUNCTION TEMPERATURE (°C) LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A 07 72 2- 00 8 Figure 8. Ground Current vs. Junction Temperature 1200 1000 800 600 400 200 0 10 100 1k 10k G R O U N D C U R R EN T (µ A ) LOAD CURRENT (mA) 07 72 2- 00 9 Figure 9. Ground Current vs. Load Current 1200 1000 800 600 400 200 0 1.8 3.63.43.23.02.82.62.42.22.0 G R O U N D C U R R EN T (µ A ) INPUT VOLTAGE (V) LOAD = 400mA LOAD = 800mA LOAD = 10mA LOAD = 100mA LOAD = 1.2A 07 72 2- 01 0 Figure 10. Ground Current vs. Input Voltage Rev. G | Page 7 of 20

Page 9

ADP1754/ADP1755 Data Sheet Rev. G | Page 8 of 20 100 90 70 80 60 50 40 30 20 10 0 –40 85603510–15 S H U T D O W N C U R R E N T ( µ A ) TEMPERATURE (°C) 1.9V 2.0V 2.4V 2.6V 3.0V 3.6V 07 72 2- 01 1 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 1 10 100 1k 10k LOAD CURRENT (mA) D R O P O U T V O L T A G E ( V ) 1.6V 2.5V 07 72 2- 01 2 Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V 2.60 2.45 2.55 2.50 2.40 2.35 2.30 2.25 2.20 2.3 2.5 2.72.4 2.6 2.8 O U T P U T V O L T A G E ( V ) INPUT VOLTAGE (V) LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A 07 72 2- 01 3 Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V 4500 2500 4000 3500 3000 2000 1500 1000 500 0 2.3 2.5 2.72.4 2.6 2.8 G R O U N D C U R R E N T ( µ A ) INPUT VOLTAGE (V) LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A 07 72 2- 01 4 Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V CH1 500mA Ω BW CH2 50mV BW M10µs A CH1 380mA 1 2 T 10.40% T ILOAD 1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV VOUT 50mV/DIV VIN = 3.6V VOUT = 1.5V 07 72 2- 01 5 Figure 15. Load Transient Response, CIN = 4.7 μF, COUT = 4.7 μF CH1 500mA Ω BW CH2 20mV BW M10µs A CH1 340mA 1 2 T 10.20% T ILOAD 1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV VOUT 20mV/DIV VIN = 3.6V VOUT = 1.5V 07 72 2- 01 6 Figure 16. Load Transient Response, CIN = 22 μF, COUT = 22 μF

Page 10

Data Sheet ADP1754/ADP1755 Rev. G | Page 9 of 20 1 2 T CH1 500mV BW CH2 5mV BW M10µs A CH4 800mV T 9.60% VIN 3V TO 3.5V INPUT VOLTAGE STEP, 2V/µs VOUT 5mV/DIV VOUT = 1.5V CIN = COUT = 4.7µF 07 72 2- 01 7 Figure 17. Line Transient Response, Load Current = 1200 mA 70 0 10 20 30 40 50 60 0.0001 0.001 0.01 0.1 1 10 N O IS E (µ V rm s) LOAD CURRENT (A) 0.75V 1.5V 2.5V 07 72 2- 01 8 Figure 18. Noise vs. Load Current and Output Voltage 10 1 0.1 0.01 10 100 1k 10k 100k N O IS E SP EC TR A L D EN SI TY (µ V/ H z) FREQUENCY (Hz) 07 08 1- 01 9 0.75V 1.5V 2.5V Figure 19. Noise Spectral Density vs. Output Voltage, ILOAD = 10 mA 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 10 100 1k 10k 100k 1M 10M PS R R (d B ) FREQUENCY (Hz) 1.2A 800mA 400mA 100mA 10mA 07 72 2- 02 0 Figure 20. Power Supply Rejection Ratio vs. Frequency, VOUT = 0.75 V, VIN = 1.75 V 10 100 1k 10k 100k 1M 10M PS R R (d B ) FREQUENCY (Hz) 1.2A 800mA 400mA 100mA 10mA 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 07 72 2- 12 1 Figure 21. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V, VIN = 2.5 V 0 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 10 100 1k 10k 100k 1M 10M PS R R (d B ) FREQUENCY (Hz) 1.2A 800mA 400mA 100mA 10mA 07 72 2- 12 2 Figure 22. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.5 V, VIN = 3.5 V