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ADSP-2187NKSTZ-320

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ADSP-2187NKSTZ-320

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Part Number ADSP-2187NKSTZ-320
Manufacturer Analog Devices Inc.
Description IC DSP CONTROLLER 16BIT 100LQFP
Datasheet ADSP-2187NKSTZ-320 Datasheet
Package 100-LQFP
In Stock 829 piece(s)
Unit Price $ 48.0900 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # ADSP-2187NKSTZ-320 (Embedded - DSP (Digital Signal Processors)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADSP-2187NKSTZ-320 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Embedded - DSP (Digital Signal Processors)
Datasheet ADSP-2187NKSTZ-320Datasheet
Package100-LQFP
SeriesADSP-21xx
TypeFixed Point
InterfaceHost Interface, Serial Port
Clock Rate80MHz
Non-Volatile MemoryExternal
On-Chip RAM160kB
Voltage - I/O1.8V, 2.5V, 3.3V
Voltage - Core1.80V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case100-LQFP
Supplier Device Package100-LQFP (14x14)

ADSP-2187NKSTZ-320 Datasheet

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a ICE-Port is a trademark of Analog Devices, Inc. DSP Microcomputer ADSP-218xN Series Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. PERFORMANCE FEATURES 12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus- tained performance Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle Multifunction instructions Power-down mode featuring low CMOS standby power dissi- pation with 200 CLKIN cycle recovery from power-down condition Low power dissipation in idle mode INTEGRATION FEATURES ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions Up to 256K byte of on-chip RAM, configured Up to 48K words program memory RAM Up to 56K words data memory RAM Dual-purpose program memory for both instruction and data storage Independent ALU, multiplier/accumulator, and barrel shifter computational units Two independent data address generators Powerful program sequencer provides zero overhead loop- ing conditional instruction execution Programmable 16-bit interval timer with prescaler 100-lead LQFP and 144-ball BGA SYSTEM INTERFACE FEATURES Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation All inputs tolerate up to 3.6 V regardless of mode 16-bit internal DMA port for high-speed access to on-chip memory (mode selectable) 4M-byte memory interface for storage of data tables and pro- gram overlays (mode selectable) 8-bit DMA to byte memory for transparent program and data memory transfers (mode selectable) Programmable memory strobe and separate I/O memory space permits “glueless” system design Programmable wait state generation Two double-buffered serial ports with companding hardware and automatic data buffering Automatic booting of on-chip program memory from byte- wide external memory, for example, EPROM, or through internal DMA Port Six external interrupts 13 programmable flag pins provide flexible system signaling UART emulation through software SPORT reconfiguration ICE-Port™ emulator interface supports debugging in final systems Figure 1. Functional Block Diagram ARITHMETIC UNITS SHIFTERMACALU PROGRAM MEMORY ADDR ESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA POWER-DOWN CONTROL MEMOR Y PROGRAM MEMORY UP TO 48K  24-BIT EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER SPORT0 SERIAL PORTS SPORT1 PROGRAMMABLE I/O AND FLAGS TIMER HOST MODE OR EXTERNAL DATA BUS INTER NAL DMA PORT DAG1 DATA ADDRESS GENERATORS DAG2 PROGRAM SEQUENCER ADSP-2100 BASE ARCHITECTURE DATA MEMORY UP TO 56K  16-BIT FULL MEMORY MODE

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Rev. A | Page 2 of 48 | August 2006 ADSP-218xN TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Modes Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Low-power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . 22 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Surface Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 REVISION HISTORY 8/06—Rev. 0 to Rev. A Miscellaneous Format Updates. . . . . . . . . . . . . . . . . . . . . . . . . . Universal Applied Corrections or Additional Information to: Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ADSP-2185 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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ADSP-218xN Rev. A | Page 3 of 48 | August 2006 GENERAL DESCRIPTION The ADSP-218xN series consists of six single chip microcom- puters optimized for digital signal processing applications. The high-level block diagram for the ADSP-218xN series members appears on the previous page. All series members are pin-com- patible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compati- bility, provides a great deal of flexibility in the design decision. Specific family members are shown in Table 1. ADSP-218xN series members combine the ADSP-2100 family base architecture (three computational units, data address gen- erators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. ADSP-218xN series members integrate up to 256K bytes of on- chip memory configured as up to 48K words (24-bit) of pro- gram RAM, and up to 56K words (16-bit) of data RAM. Power- down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-218xN is available in a 100-lead LQFP package and 144-ball BGA. Fabricated in a high-speed, low-power, 0.18 μm CMOS process, ADSP-218xN series members operate with a 12.5 ns instruction cycle time. Every instruction can execute in a single pro- cessor cycle. The ADSP-218xN’s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. In one processor cycle, ADSP-218xN series members can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation This takes place while the processor continues to: • Receive and transmit data through the two serial ports • Receive and/or transmit data through the internal DMA port • Receive and/or transmit data through the byte DMA port • Decrement timer ARCHITECTURE OVERVIEW The ADSP-218xN series instruction set provides flexible data moves and multifunction (one or two data moves with a com- putation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-218xN assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The functional block diagram is an overall block diagram of the ADSP-218xN series. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multi- ply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denor- malization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, ADSP-218xN series members execute looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and pro- gram memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possi- ble modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Five internal buses provide efficient data transfer: • Program Memory Address (PMA) Bus • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus • Data Memory Data (DMD) Bus • Result (R) Bus Table 1. ADSP-218xN DSP Microcomputer Family Device Program Memory (K words) Data Memory (K words) ADSP-2184N 4 4 ADSP-2185N 16 16 ADSP-2186N 8 8 ADSP-2187N 32 32 ADSP-2188N 48 56 ADSP-2189N 32 48

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Rev. A | Page 4 of 48 | August 2006 ADSP-218xN The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permit- ting ADSP-218xN series members to fetch two operands in a single cycle, one from program memory and one from data memory. ADSP-218xN series members can fetch an operand from program memory and the next instruction in the same cycle. In lieu of the address and data bus for external memory connec- tion, ADSP-218xN series members may be configured for 16-bit Internal DMA port (IDMA port) connection to external sys- tems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSP’s on-chip program and data RAM. An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with pro- grammable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-218xN to continue running from on-chip memory. Nor- mal execution mode requires the processor to halt while buses are granted. ADSP-218xN series members can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORT), the BDMA port, and the power-down circuitry. There is also a mas- ter RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hard- ware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. ADSP-218xN series members provide up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports ADSP-218xN series members incorporate two complete syn- chronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Following is a brief list of the capabilities of the ADSP-218xN SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • SPORTs can use an external serial clock or generate their own serial clock internally. • SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally gen- erated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. • SPORTs support serial data word lengths from 3 bits to 16 bits and provide optional A-law and μ-law companding, according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. • SPORT0 has a multichannel interface to selectively receive and transmit a 24 word or 32-word, time-division multi- plexed, serial bitstream. • SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration.

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ADSP-218xN Rev. A | Page 5 of 48 | August 2006 MODES OF OPERATION The ADSP-218xN series modes of operation appear in Table 2. Setting Memory Mode Memory Mode selection for the ADSP-218xN series is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive Configuration Passive Configuration involves the use of a pull-up or pull- down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down resistance, on the order of 10 kΩ, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the pro- cessor’s output driver. For minimum power consumption during power-down, reconfigure PF2 to be an input, as the pull- up or pull-down resistance will hold the pin in a known state, and will not switch. Active Configuration Active Configuration involves the use of a three-statable exter- nal driver connected to the Mode C pin. A driver’s output enable should be connected to the DSP’s RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is deasserted, the driver should be three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. This ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver’s level hover around the logic switching point. IDMA ACK Configuration Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be “wire-OR’ed.” Mode D = 1 and in host mode: IACK is an open drain and requires an external pull-down, but multiple IACK pins can be “wire-OR’ed” together. INTERRUPTS The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. ADSP-218xN series members provide four dedicated external interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7–4 pins). In addition, SPORT1 may be reconfig- ured for IRQ0, IRQ1, FI, and FO, for a total of six external interrupts. The ADSP-218xN also supports internal interrupts from the timer, the byte DMA port, the two serial ports, soft- ware, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table 3. Table 2. Modes of Operation Mode D Mode C Mode B Mode A Booting Method X 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.1 X 0 1 0 No automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations. 0 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. IACK has active pull-down. (Requires additonal hardware.) 0 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until the host writes to internal program memory location 0. Chip is configured in Host Mode. IACK has active pull-down.1 1 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires external pull-down. (Requires additonal hardware.) 1 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until the host writes to internal program memory location 0. Chip is configured in Host Mode. IACK requires external pull-down.1 1 Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

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Rev. A | Page 6 of 48 | August 2006 ADSP-218xN Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Inter- rupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. ADSP-218xN series members mask all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nest- ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are 12 levels deep to allow interrupt, loop, and subroutine nest- ing. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK: ENA INTS; DIS INTS; Disabling the interrupts does not affect serial port autobuffering or DMA. When the processor is reset, interrupt servicing is enabled. LOW-POWER OPERATION ADSP-218xN series members have three low-power modes that significantly reduce the power dissipation when the device oper- ates under standby conditions. These modes are: • Power-Down • Idle • Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down ADSP-218xN series members have a low-power feature that lets the processor enter a very low-power dormant state through hardware or software control. Following is a brief list of power- down features. Refer to the ADSP-218x DSP Hardware Refer- ence, “System Interface” chapter, for detailed information about the power-down feature. • Quick recovery from power-down. The processor begins executing instructions in as few as 200 CLKIN cycles. • Support for an externally generated TTL or CMOS proces- sor clock. The external clock can continue running during power-down without affecting the lowest power rating and 200 CLKIN cycle recovery. • Support for crystal operation includes disabling the oscilla- tor to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle start-up. • Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power- down interrupt also can be used as a nonmaskable, edge- sensitive interrupt. • Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. • The RESET pin also can be used to terminate power-down. • Power-down acknowledge pin (PWDACK) indicates when the processor has entered power-down. Idle When the ADSP-218xN is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruc- tion. In Idle mode IDMA, BDMA, and autobuffer cycle steals still occur. Slow Idle The IDLE instruction is enhanced on ADSP-218xN series mem- bers to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is: IDLE (n); where n = 16, 32, 64, or 128. This instruction keeps the proces- sor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, Table 3. Interrupt Priority and Interrupt Vector Addresses Source Of Interrupt Interrupt Vector Address (Hex) Reset (or Power-Up with PUCR = 1) 0x0000 (Highest Priority) Power-Down (Nonmaskable) 0x002C IRQ2 0x0004 IRQL1 0x0008 IRQL0 0x000C SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 IRQE 0x0018 BDMA Interrupt 0x001C SPORT1 Transmit or IRQ1 0x0020 SPORT1 Receive or IRQ0 0x0024 Timer 0x0028 (Lowest Priority)

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ADSP-218xN Rev. A | Page 7 of 48 | August 2006 such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the stan- dard idle state is increased by n, the clock divisor. When an enabled interrupt is received, ADSP-218xN series members remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming nor- mal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE Figure 2 shows typical basic system configurations with the ADSP-218xN series, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (mode-selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. ADSP-218xN series members also provide four external inter- rupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals. Figure 2. Basic System Interface In ser t s yst em in ter fac e d iag ram he re 1/2  CLOCK OR CRYSTAL FL0–2 CLKIN XTAL SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT1 SERIAL DEVICE A0–A21 DATA BYTE MEMORY I/O SPACE (PERIPHERALS) DATA ADDR DATA ADDR 2048 LOCATIONS OVERLAY MEMORY TWO 8K PM SEGMENTS D23–0 A13–0 D23–8 A10–0 D15–8 D23–16 A13–014 24 SCLK0 RFS0 TFS0 DT0 DR0 SPORT0 DATA23–0 ADSP-218xN CS CS 1/2  CLOCK OR CRYSTAL CLKIN XTAL FL0–2 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT1 16 IDMA PORT IRD/D6 IS/D4 IAL/D5 IACK/D3 IAD15-0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 SPORT0 1 16 A0 DATA23–8 IOMS BMS DMS CMS BR BG BGH PWD PWDACK HOST MEMORY MODEFULL MEMORY MODE MODE D/PF3 MODE C/PF2 MODE B/PF1 MODE A/PF0 IRQ2/PF7 IRQE/PF4 IRQL0/PF5 MODE D/PF3 MODE C/PF2 MODE B/PF1 MODE A/PF0 WR RD SYSTEM INTERFACE OR µCONTROLLER IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 IOMS BMS PMS CMS BR BG BGH PWD PWDACK WR RD ADSP-218xN DMS TWO 8K DM SEGMENTS PMS ADDR13–0 IRQL1/PF6 IWR/D7

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Rev. A | Page 8 of 48 | August 2006 ADSP-218xN Clock Signals ADSP-218xN series members can be clocked by either a crystal or a TTL-compatible clock signal. The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during normal oper- ation. The only exception is while the processor is in the power- down state. For additional information, refer to the ADSP-218x DSP Hardware Reference, for detailed information on this power-down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL pin must be left unconnected. ADSP-218xN series members use an input clock with a fre- quency equal to half the instruction rate; a 40 MHz input clock yields a 12.5 ns processor cycle (which is equivalent to 80 MHz). Normally, instructions are executed in a single pro- cessor cycle. All device timing is relative to the internal instruc- tion clock rate, which is indicated by the CLKOUT signal when enabled. Because ADSP-218xN series members include an on-chip oscil- lator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. To provide an adequate feedback path around the internal amplifier circuit, place a resistor in parallel with the circuit, as shown in Figure 3. A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. RESET The RESET signal initiates a master reset of the ADSP-218xN. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the mini- mum pulse-width specification (tRSP). The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an exter- nal Schmitt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on- chip program memory location 0x0000 once boot loading completes. POWER SUPPLIES ADSP-218xN series members have separate power supply con- nections for the internal (VDDINT) and external (VDDEXT) power supplies. The internal supply must meet the 1.8 V requirement. The external supply can be connected to a 1.8 V, 2.5 V, or 3.3 V supply. All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6 V, regardless of the external supply voltage. This feature pro- vides maximum flexibility in mixing 1.8 V, 2.5 V, or 3.3 V components. Figure 3. External Crystal Connections C LK IN C L K O U TX TA L D S P 1M 

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ADSP-218xN Rev. A | Page 9 of 48 | August 2006 MEMORY ARCHITECTURE The ADSP-218xN series provides a variety of memory and peripheral interface options. The key functional groups are Pro- gram Memory, Data Memory, Byte Memory, and I/O. Refer to Figure 4 through Figure 9, Table 4 on Page 11, and Table 5 on Page 11 for PM and DM memory allocations in the ADSP- 218xN series. Figure 4. ADSP-2184 Memory Architecture Figure 5. ADSP-2185 Memory Architecture Figure 6. ADSP-2186 Memory Architecture PROGRAM MEMORY PM OVERLAY 1,2 (EXTERNAL PM) INTERNAL PM PM OVERLAY 0 (RESERVED) RESERVED MODEB = 0 0x3FFF 0x2000 0x0000 0x0FFF 0x1000 0x1FFF 0x3FFF 0x2000 0x0000 0x3FE0 0x3FDF 0x3000 0x2FFF 0x1FFF DATA MEMORY DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL DM 32 MEMORY-MAPPED CONTROL REGISTERS 4064 RESERVED WORDS DM OVERLAY 0 (RESERVED) PROGRAM MEMORY RESERVED EXTERNAL PM MODEB = 1 0x3FFF 0x2000 0x0000 0x1FFF PROGRAM MEMORY PM OVERLAY 1,2 (EXTERNAL PM) INTERNAL PM PM OVERLAY 0 (INTERNAL PM) MODEB = 0 0x3FFF 0x2000 0x0000 0x1FFF 0x3FFF 0x2000 0x0000 0x3FE0 0x3FDF 0x1FFF DATA MEMORY DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL DM 32 MEMORY-MAPPED CONTROL REGISTERS DM OVERLAY 0 (INTERNAL DM) PROGRAM MEMORY RESERVED EXTERNAL PM MODEB = 1 0x3FFF 0x2000 0x0000 0x1FFF PROGRAM MEMORY PM OVERLAY 1,2 (EXTERNAL PM) INTERNAL PM PM OVERLAY 0 (RESERVED) MODEB = 0 0x3FFF 0x2000 0x0000 0x1FFF 0x3FFF 0x2000 0x0000 0x3FE0 0x3FDF 0x1FFF DATA MEMORY DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL DM 32 MEMORY-MAPPED CONTROL REGISTERS DM OVERLAY 0 (RESERVED) PROGRAM MEMORY RESERVED EXTERNAL PM MODEB = 1 0x3FFF 0x2000 0x0000 0x1FFF

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