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ADSP-BF548BBCZ-5A

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ADSP-BF548BBCZ-5A

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Part Number ADSP-BF548BBCZ-5A
Manufacturer Analog Devices Inc.
Description IC DSP 16BIT 533MHZ 400CSBGA
Datasheet ADSP-BF548BBCZ-5A Datasheet
Package 400-LFBGA, CSPBGA
In Stock 386 piece(s)
Unit Price $ 41.2200 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jan 30 - Feb 4 (Choose Expedited Shipping)
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Part Number # ADSP-BF548BBCZ-5A (Embedded - DSP (Digital Signal Processors)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADSP-BF548BBCZ-5A Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Embedded - DSP (Digital Signal Processors)
Datasheet ADSP-BF548BBCZ-5ADatasheet
Package400-LFBGA, CSPBGA
SeriesBlackfin?
TypeFixed Point
InterfaceCAN, SPI, SSP, TWI, UART, USB
Clock Rate533MHz
Non-Volatile MemoryExternal
On-Chip RAM260kB
Voltage - I/O2.50V, 3.30V
Voltage - Core1.25V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case400-LFBGA, CSPBGA
Supplier Device Package400-CSPBGA (17x17)

ADSP-BF548BBCZ-5A Datasheet

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Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin Embedded Processor ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs RISC-like register and instruction model Wide range of operating voltages and flexible booting options Programmable on-chip voltage regulator 400-ball CSP_BGA, RoHS compliant package MEMORY Up to 324K bytes of on-chip memory comprised of instruction SRAM/cache; dedicated instruction SRAM; data SRAM/cache; dedicated data SRAM; scratchpad SRAM External sync memory controller supporting either DDR SDRAM or mobile DDR SDRAM External async memory controller supporting 8-/16-bit async memories and burst flash devices NAND flash controller 4 memory-to-memory DMA pairs, 2 with ext. requests Memory management unit providing memory protection Code security with Lockbox secure technology and 128-bit AES/ARC4 data encryption One-time-programmable (OTP) memory PERIPHERALS High speed USB On-the-Go (OTG) with integrated PHY SD/SDIO controller ATA/ATAPI-6 controller Up to 4 synchronous serial ports (SPORTs) Up to 3 serial peripheral interfaces (SPI-compatible) Up to 4 UARTs, two with automatic H/W flow control Up to 2 CAN (controller area network) 2.0B interfaces Up to 2 TWI (2-wire interface) controllers 8- or 16-bit asynchronous host DMA interface Multiple enhanced parallel peripheral interfaces (EPPIs), supporting ITU-R BT.656 video formats and 18-/24-bit LCD connections Media transceiver (MXVR) for connection to a MOST network Pixel compositor for overlays, alpha blending, and color conversion Up to eleven 32-bit timers/counters with PWM support Real-time clock (RTC) and watchdog timer Up/down counter with support for rotary encoder Up to 152 general-purpose I/O (GPIOs) On-chip PLL capable of frequency multiplication Debug/JTAG interface Figure 1. ADSP-BF549 Functional Block Diagram CAN (0-1) TWI (0-1) TIMERS(0-10) KEYPAD COUNTER RTC HOST DMA JTAG TEST AND EMULATION UART (2-3) EXTERNAL PORT NOR, DDR, MDDR SPI (2) SPORT (0-1) SD / SDIO WATCHDOG TIMER BOOT ROM 32 16 PIXEL COMPOSITOR VOLTAGE REGULATOR EPPI (0-2) SPORT (2-3) SPI (0-1) UART (0-1) P O R T S PAB USB 16-BIT DMA 32-BIT DMA INTERRUPTS L2 SRAM L1 INSTR ROM L1 INSTR SRAM L1 DATA SRAM DAB1 DAB0 P O R T S OTP 16 16 DDR/MDDR ASYNC 16 NAND FLASH CONTROLLER ATAPI MXVR DCB 32 EAB 64 DEB 32 B

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Rev. E | Page 2 of 102 | March 2014 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TABLE OF CONTENTS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Low Power Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Blackfin Processor Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Blackfin Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Up/Down Counter and Thumbwheel Interface . . . . . . . . . . 11 Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . . . . . . . . . . . 11 UART Ports (UARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Controller Area Network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TWI Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pixel Compositor (PIXC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Enhanced Parallel Peripheral Interface (EPPI) . . . . . . . . . . . 13 USB On-the-Go Dual-Role Device Controller . . . . . . . . . . . . 13 ATA/ATAPI-6 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Keypad Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Secure Digital (SD)/SDIO Controller . . . . . . . . . . . . . . . . . . . . . . . 14 Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Media Transceiver MAC Layer (MXVR) . . . . . . . . . . . . . . . . . . 14 Dynamic Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MXVR Board Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Related Signal Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Lockbox Secure Technology Disclaimer . . . . . . . . . . . . . . . . . . . . 23 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 400-Ball CSP_BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Surface-Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 REVISION HISTORY 03/14—Rev. D to Rev. E Updated Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Corrected SPI2 pin count in Port B configuration in Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Corrected typographical error of parameter name in External DMA Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Added note to Table 42 in Serial Ports—Enable and Three-State . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Corrected tWL and tWH minimum specifications from tSCLK +1 to 1 × tSCLK in Timer Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Added/changed package dimensions to Figure 88 in Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Added low Alpha Package model to Ordering Guide . . . . . 101

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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Rev. E | Page 3 of 102 | March 2014 GENERAL DESCRIPTION The ADSP-BF54x Blackfin® processors are members of the Blackfin family of products, incorporating the Analog Devices/ Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. Specific performance, memory configurations, and features of ADSP-BF54x Blackfin processors are shown in Table 1. Specific peripherals for ADSP-BF54x Blackfin processors are shown in Table 2. Table 1. ADSP-BF54x Processor Features Processor Features A D S P -B F 5 4 9 A D S P -B F 5 4 8 A D S P -B F 5 4 7 A D S P -B F 5 4 4 A D S P -B F 5 4 2 Lockbox® 1code security 1 Lockbox is a registered trademark of Analog Devices, Inc. 1 1 1 1 1 128-bit AES/ ARC4 data encryption 1 1 1 1 1 SD/SDIO controller 1 1 1 – 1 Pixel compositor 1 1 1 1 1 18- or 24-bit EPPI0 with LCD 1 1 1 1 – 16-bit EPPI1, 8-bit EPPI2 1 1 1 1 1 Host DMA port 1 1 1 1 – NAND flash controller 1 1 1 1 1 ATAPI 1 1 1 – 1 High speed USB OTG 1 1 1 – 1 Keypad interface 1 1 1 – 1 MXVR 1 – – – – CAN ports 2 2 – 2 1 TWI ports 2 2 2 2 1 SPI ports 3 3 3 2 2 UART ports 4 4 4 3 3 SPORTs 4 4 4 3 3 Up/down counter 1 1 1 1 1 Timers 11 11 11 11 8 General-purpose I/O pins 152 152 152 152 152 Memory Configura- tions (K Bytes) L1 Instruction SRAM/cache 16 16 16 16 16 L1 Instruction SRAM 48 48 48 48 48 L1 Data SRAM/cache 32 32 32 32 32 L1 Data SRAM 32 32 32 32 32 L1 Scratchpad SRAM 4 4 4 4 4 L1 ROM2 2 This ROM is not customer-configurable. 64 64 64 64 64 L2 128 128 128 64 – L3 Boot ROM2 4 4 4 4 4 Maximum core instruction rate (MHz) 533 533 600 533 600 Table 2. Specific Peripherals for ADSP-BF54x Processors Module A D S P -B F 5 4 9 A D S P -B F 5 4 8 A D S P -B F 5 4 7 A D S P -B F 5 4 4 A D S P -B F 5 4 2 EBIU (async) P P P P P NAND flash controller P P P P P ATAPI P P P – P Host DMA port (HOSTDP) P P P P – SD/SDIO controller P P P – P EPPI0 P P P P – EPPI1 P P P P P EPPI2 P P P P P SPORT0 P P P – – SPORT1 P P P P P SPORT2 P P P P P SPORT3 P P P P P SPI0 P P P P P SPI1 P P P P P SPI2 P P P – – UART0 P P P P P UART1 P P P P P UART2 P P P – – UART3 P P P P P High speed USB OTG P P P – P CAN0 P P – P P CAN1 P P – P – TWI0 P P P P P TWI1 P P P P – Timer 0–7 P P P P P Timer 8–10 P P P P – Up/down counter P P P P P Keypad interface P P P – P MXVR P – – – – GPIOs P P P P P

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Rev. E | Page 4 of 102 | March 2014 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The ADSP-BF54x Blackfin processors are completely code- and pin-compatible. They differ only with respect to their perfor- mance, on-chip memory, and selection of I/O peripherals. Specific performance, memory, and feature configurations are shown in Table 1. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like program- mability, multimedia support, and leading-edge signal processing in one integrated package. LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature on-chip dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Reducing both voltage and frequency can result in a substantial reduction in power consumption as compared to reducing only the frequency of operation. This translates into longer battery life for portable appliances. SYSTEM INTEGRATION The ADSP-BF54x Blackfin processors are highly integrated system-on-a-chip solutions for the next generation of embed- ded network connected applications. By combining industry- standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a high speed USB OTG (On-the-Go) controller with integrated PHY, CAN 2.0B controllers, TWI controllers, UART ports, SPI ports, serial ports (SPORTs), ATAPI controller, SD/SDIO controller, a real-time clock, a watchdog timer, LCD controller, and multiple enhanced parallel peripheral interfaces. BLACKFIN PROCESSOR PERIPHERALS The ADSP-BF54x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see Figure 1 on Page 1). The general- purpose peripherals include functions such as UARTs, SPI, TWI, timers with pulse width modulation (PWM) and pulse measurement capability, general-purpose I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. The ADSP- BF54x processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on- chip peripherals or external sources, and power management control functions to tailor the performance and power charac- teristics of the processor and system to many application scenarios. All of the peripherals, except for general-purpose I/O, CAN, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external DDR (either standard or mobile, depending on the device) and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF54x Blackfin processors include an on-chip volt- age regulator in support of the dynamic power management capability. The voltage regulator provides a range of core volt- age levels when supplied from VDDEXT. The voltage regulator can be bypassed at the user’s discretion. BLACKFIN PROCESSOR CORE As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- tation units process 8-, 16-, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16- or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and pop- ulation count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-over- head looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify,

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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Rev. E | Page 5 of 102 | March 2014 length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory manage- ment unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. Figure 2. Blackfin Processor Core SEQUENCER ALIGN DECODE LOOP BUFFER 16 16 88 8 8 40 40 A0 A1 BARREL SHIFTER DATA ARITHMETIC UNIT CONTROL UNIT R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L ASTAT 40 40 32 32 32 32 32 32 32LD0 LD1 SD DAG0 DAG1 ADDRESS ARITHMETIC UNIT I3 I2 I1 I0 L3 L2 L1 L0 B3 B2 B1 B0 M3 M2 M1 M0 SP FP P5 P4 P3 P2 P1 P0 DA1 DA0 32 32 32 PREGRAB 32 T O M E M O R Y

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Rev. E | Page 6 of 102 | March 2014 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 MEMORY ARCHITECTURE The ADSP-BF54x processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3 on Page 6. The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip mem- ory system, accessed through the external bus interface unit (EBIU), provides expansion with flash memory, SRAM, and double-rate SDRAM (standard or mobile DDR), optionally accessing up to 768M bytes of physical memory. Most of the ADSP-BF54x Blackfin processors also include an L2 SRAM memory array which provides up to 128K bytes of high speed SRAM, operating at one half the frequency of the core and with slightly longer latency than the L1 memory banks (for information on L2 memory in each processor, see Table 1). The L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The Blackfin cores share a dedicated low latency 64-bit data path port into the L2 SRAM memory. The memory DMA controllers (DMAC1 and DMAC0) provide high-bandwidth data-movement capability. They can perform block transfers of code or data between the internal memory and the external memory spaces. Internal (On-Chip) Memory The ADSP-BF54x processors have several blocks of on-chip memory providing high bandwidth access to the core. The first block is the L1 instruction memory, consisting of 64K bytes of SRAM, of which 16K bytes can be configured as a four-way set-associative cache or as SRAM. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, con- sisting of 64K bytes of SRAM, of which 32K bytes can be configured as a two-way set-associative cache or as SRAM. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM, which runs at the same speed as the L1 memories. It is only accessible as data SRAM and cannot be configured as cache memory. The fourth memory block is the factory programmed L1 instruction ROM, operating at full processor speed. This ROM is not customer-configurable. The fifth memory block is the L2 SRAM, providing up to 128K bytes of unified instruction and data memory, operating at one half the frequency of the core. Finally, there is a 4K byte boot ROM connected as L3 memory. It operates at full SCLK rate. External (Off-Chip) Memory Through the external bus interface unit (EBIU), the ADSP-BF54x Blackfin processors provide glueless connectivity to external 16-bit wide memories, such as DDR and mobile DDR SDRAM, SRAM, NOR flash, NAND flash, and FIFO devices. To provide the best performance, the bus system of the DDR and mobile DDR interface is completely separate from the other parallel interfaces. Furthermore, the DDR controller sup- ports either standard DDR memory or mobile DDR memory. See the Ordering Guide on Page 101 for details. Throughout this document, references to “DDR” are intended to cover both the standard and mobile DDR standards. Figure 3. ADSP-BF547/ADSP-BF548/ADSP-BF549 Internal/External Memory Map1 1 For ADSP-BF544 processors, L2 SRAM is 64K Bytes (0xFEB0000–0xFEB0FFFF). For ADSP-BF542 processors, there is no L2 SRAM. RESERVED CORE MMR REGISTERS (2M BYTES) RESERVED SCRATCHPAD SRAM (4K BYTES) INSTRUCTION BANK B SRAM (16K BYTES) SYSTEM MMR REGISTERS (2M BYTES) RESERVED RESERVED DATA BANK B SRAM / CACHE (16K BYTES) DATA BANK B SRAM (16K BYTES) DATA BANK A SRAM / CACHE (16K BYTES) ASYNC MEMORY BANK 3 (64M BYTES) ASYNC MEMORY BANK 2 (64M BYTES) ASYNC MEMORY BANK 1 (64M BYTES) ASYNC MEMORY BANK 0 (64M BYTES) DDR MEM BANK 0 (8M BYTES to 256M BYTES) INSTRUCTION SRAM / CACHE (16K BYTES) IN T E R N A L M E M O R Y M A P E X T E R N A L M E M O R Y M A P FFFF FFFF FEB0 0000 FFB0 0000 FFA2 4000 FFA1 0000 FF90 8000 FF90 4000 FF80 8000 FF80 4000 3000 0000 2C00 0000 2800 0000 2400 0000 2000 0000 EF00 0000 0000 0000 FFC0 0000 FFB0 1000 FFA0 0000 DATA BANK A SRAM (16K BYTES) FF90 0000 FF80 0000 RESERVED RESERVED C000 FFA0 8000 INSTRUCTION BANK A SRAM (32K BYTES) RESERVED BOOT ROM (4K BYTES) EF00 1000 FFE0 0000 FEB2 0000 FFA1 4000 L1 ROM (64K BYTE) L2 SRAM (128K BYTES) DDR MEM BANK 1 (8M BYTES to 256M BYTES) RESERVEDTOP OF LAST DDR PAGE RESERVED FFA0 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x

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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Rev. E | Page 7 of 102 | March 2014 The DDR memory controller can gluelessly manage up to two banks of double-rate synchronous dynamic memory (DDR and mobile DDR SDRAM). The 16-bit interface operates at the SCLK frequency, enabling a maximum throughput of 532M bytes/s. The DDR and mobile DDR controller is augmented with a queuing mechanism that performs efficient bursts into the DDR and mobile DDR. The controller is an industry stan- dard DDR and mobile DDR SDRAM controller with each bank supporting from 64M bit to 512M bit device sizes and 4-, 8-, or 16-bit widths. The controller supports up to 256M bytes per external bank. With 2 external banks, the controller supports up to 512M bytes total. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. Traditional 16-bit asynchronous memories, such as SRAM, EPROM, and flash devices, can be connected to one of the four 64M byte asynchronous memory banks, represented by four memory select strobes. Alternatively, these strobes can function as bank-specific read or write strobes preventing further glue logic when connecting to asynchronous FIFO devices. See the Ordering Guide on Page 101 for a list of specific products that provide support for DDR memory. In addition, the external bus can connect to advanced flash device technologies, such as: • Page-mode NOR flash devices • Synchronous burst-mode NOR flash devices • NAND flash devices Customers should consult the Ordering Guide when selecting a specific ADSP-BF54x component for the intended application. Products that provide support for mobile DDR memory are noted in the ordering guide footnotes. NAND Flash Controller (NFC) The ADSP-BF54x Blackfin processors provide a NAND Flash Controller (NFC) as part of the external bus interface. NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. Because of this, NAND flash is often used for read-only code storage. In this case, all DSP code can be stored in NAND flash and then transferred to a faster memory (such as DDR or SRAM) before execution. Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file system may be used to manage reading and writing of the NAND flash device. The file system selects memory seg- ments for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address loca- tions. Hardware features of the NFC include: • Support for page program, page read, and block erase of NAND flash devices, with accesses aligned to page boundaries. • Error checking and correction (ECC) hardware that facili- tates error detection and correction. • A single 8-bit or 16-bit external bus interface for com- mands, addresses, and data. • Support for SLC (single level cell) NAND flash devices unlimited in size, with page sizes of 256 bytes and 512 bytes. Larger page sizes can be supported in software. • The ability to release external bus interface pins during long accesses. • Support for internal bus requests of 16 bits or 32 bits. • A DMA engine to transfer data between internal memory and a NAND flash device. One-Time-Programmable Memory The ADSP-BF54x Blackfin processors have 64K bits of one- time-programmable (OTP) non-volatile memory that can be programmed by the developer only one time. It includes the array and logic to support read access and programming. Addi- tionally, its pages can be write protected. OTP enables developers to store both public and private data on-chip. In addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-definable data such as a customer ID, product ID, or a MAC address. By using this feature, generic parts can be shipped, which are then programmed and protected by the developer within this non-volatile memory. The OTP memory can be accessed through an API provided by the on-chip ROM. I/O Memory Space The ADSP-BF54x Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one containing the control MMRs for all core functions and the other containing the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The ADSP-BF54x Blackfin processors contain a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF54x Blackfin processors are configured to boot from boot ROM memory space, the processor starts exe- cuting from the on-chip boot ROM. For more information, see Booting Modes on Page 18. Event Handling The event controller on the ADSP-BF54x Blackfin processors handles all asynchronous and synchronous events to the proces- sors. The ADSP-BF54x Blackfin processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultane- ously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event.

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Rev. E | Page 8 of 102 | March 2014 ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 The controller provides support for five different types of events: • Emulation. An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset. This event resets the processor. • Non-maskable interrupt (NMI). The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions. Events that occur synchronously to program flow (that is, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts. Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF54x Blackfin processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all sys- tem events. Conceptually, interrupts from the peripherals enter into the SIC and are then routed directly into the general-pur- pose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority inter- rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF54x Blackfin processors. Table 3 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. System Interrupt Controller (SIC) The system interrupt controller provides the mapping and rout- ing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF54x Blackfin processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). The ADSP-BF54x Hardware Reference Manual, “System Interrupts” chapter describes the inputs into the SIC and the default mappings into the CEC. Event Control The ADSP-BF54x Blackfin processors provide the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC interrupt latch register (ILAT). The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. • CEC interrupt mask register (IMASK). The IMASK regis- ter controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, prevent- ing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. Note that general-purpose interrupts can be globally enabled and dis- abled with the STI and CLI instructions, respectively. • CEC interrupt pending register (IPEND). The IPEND reg- ister keeps track of all nested events. A set bit in the IPEND register indicates that the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in the ADSP-BF54x Hardware Reference Manual, “System Interrupts” chapter. Table 3. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0 Emulation/Test Control EMU 1 Reset RST 2 Nonmaskable Interrupt NMI 3 Exception EVX 4 Reserved — 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15

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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Rev. E | Page 9 of 102 | March 2014 • SIC interrupt mask registers (SIC_IMASKx). These regis- ters control the masking and unmasking of each peripheral interrupt event. When a bit is set in a register, that periph- eral event is unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. • SIC interrupt status registers (SIC_ISRx). As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. • SIC interrupt wakeup enable registers (SIC_IWRx). By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled or in Sleep mode when the event is generated. (For more information, see Dynamic Power Management on Page 15.) Because multiple interrupt sources can map to a single general- purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND reg- ister contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected. (Detection requires two core clock cycles.) The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the proces- sor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general- purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. DMA CONTROLLERS ADSP-BF54x Blackfin processors have multiple, independent DMA channels that support automated data transfers with min- imal overhead for the processor core. DMA transfers can occur between the ADSP-BF54x processors’ internal memories and any of the DMA-capable peripherals. Additionally, DMA trans- fers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including DDR and asynchronous memory controllers. While the USB controller and MXVR have their own dedicated DMA controllers, the other on-chip peripherals are managed by two centralized DMA controllers, called DMAC1 (32-bit) and DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA controller manages 12 independent peripheral DMA channels, as well as two independent memory DMA streams. The DMAC1 controller masters high-bandwidth peripherals over a dedicated 32-bit DMA access bus (DAB32). Similarly, the DMAC0 controller masters most serial interfaces over the 16-bit DAB16 bus. Individual DMA channels have fixed access prior- ity on the DAB buses. DMA priority of peripherals is managed by a flexible peripheral-to-DMA channel assignment scheme. All four DMA controllers use the same 32-bit DCB bus to exchange data with L1 memory. This includes L1 ROM, but excludes scratchpad memory. Fine granulation of L1 memory and special DMA buffers minimize potential memory conflicts when the L1 memory is accessed simultaneously by the core. Similarly, there are dedicated DMA buses between the external bus interface unit (EBIU) and the three DMA controllers (DMAC1, DMAC0, and USB) that arbitrate DMA accesses to external memories and the boot ROM. The ADSP-BF54x Blackfin processors’ DMA controllers sup- port both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de- interleaved on the fly. Examples of DMA types supported by the ADSP-BF54x Black- fin processors’ DMA controllers include: • A single, linear buffer that stops upon completion • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer • 1D or 2D DMA using a linked list of descriptors • 2D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, the DMAC1 and DMAC0 controllers each feature two memory DMA channel pairs for transfers between the various memories of the ADSP-BF54x Blackfin processors. This enables transfers of blocks of data between any of the memories—including external DDR, ROM, SRAM, and flash memory—with minimal processor intervention. Like peripheral DMAs, memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. The memory DMA channels of the DMAC1 controller (MDMA2 and MDMA3) can be controlled optionally by the external DMA request input pins. When used in conjunction with the External Bus Interface Unit (EBIU), this handshaked memory DMA (HMDMA) scheme can be used to efficiently exchange data with block-buffered or FIFO-style devices con- nected externally. Users can select whether the DMA request pins control the source or the destination side of the memory DMA. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is program- mable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core.

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