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ADV7341BSTZ

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ADV7341BSTZ

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Part Number ADV7341BSTZ
Manufacturer Analog Devices Inc.
Description IC ENCODER VIDEO HDTV 64LQFP
Datasheet ADV7341BSTZ Datasheet
Package 64-LQFP
In Stock 1,175 piece(s)
Unit Price $ 33.6400 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # ADV7341BSTZ (Interface - Encoders, Decoders, Converters) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADV7341BSTZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Encoders, Decoders, Converters
Datasheet ADV7341BSTZDatasheet
Package64-LQFP
Series-
TypeVideo Encoder
ApplicationsDVD, Blu-Ray
Voltage - Supply, Analog3.3V
Voltage - Supply, Digital1.8V
Mounting TypeSurface Mount
Package / Case64-LQFP
Supplier Device Package64-LQFP (10x10)

ADV7341BSTZ Datasheet

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Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS Data Sheet ADV7340/ADV7341 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006-2012 Analog Devices, Inc. All rights reserved. FEATURES 74.25 MHz 20-/30-bit high definition input support Compliant with SMPTE 274 M (1080i), 296 M (720p), and 240 M (1035i) 6 Noise Shaped Video® (NSV) 12-bit video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 YCrCb (ED and HD) 4:4:4 RGB (SD, ED, and HD) Multiformat video output support Composite (CVBS) and S-Video (Y-C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD) Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Simultaneous SD and ED/HD operation EIA/CEA-861B compliance support Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation On-board voltage reference (optional external input) Programmable features Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (FSC) and phase Luma delay High definition (HD) programmable features (720p/1080i/1035i) 4× oversampling (297 MHz) Internal test pattern generator Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS (720p/1080i) and CGMS Type B (720p/1080i) Undershoot limiter Dual data rate (DDR) input support Enhanced definition (ED) programmable features (525p/625p) 8× oversampling (216 MHz output) Internal test pattern generator Black bar, hatch, flat field/frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) (ADV7340 only) CGMS (525p/625p) and CGMS Type B (525p) Dual data rate (DDR) input support Standard definition (SD) programmable features 16× oversampling (216 MHz) Internal test pattern generator Color and black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAF filter with programmable gain/attenuation PrPb SSAF Separate pedestal control on component and composite/S-Video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 (ADV7340 only) Copy generation management system (CGMS) Wide screen signaling (WSS) Closed captioning Serial MPU interface with I2C compatibility 3.3 V analog operation 1.8 V digital operation 1.8 V or 3.3 V I/O operation Temperature range: −40°C to +85°C APPLICATIONS DVD recorders and players High definition Blu-ray DVD players

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ADV7340/ADV7341 Data Sheet Rev. C | Page 2 of 108 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Revision History ............................................................................... 4 General Description ......................................................................... 5 Functional Block Diagram .............................................................. 6 Specifications ..................................................................................... 7 Power Supply and Voltage Specifications .................................. 7 Voltage Reference Specifications ................................................ 7 Input Clock Specifications .......................................................... 7 Analog Output Specifications ..................................................... 8 Digital Input/Output Specifications—3.3 V ............................. 8 Digital Input/Output Specifications—1.8 V ............................. 8 Digital Timing Specifications—3.3 V ........................................ 9 Digital Timing Specifications—1.8 V ...................................... 10 MPU Port Timing Specifications ............................................. 11 Power Specifications .................................................................. 11 Video Performance Specifications ........................................... 12 Timing Diagrams ............................................................................ 13 Absolute Maximum Ratings .......................................................... 21 Thermal Resistance .................................................................... 21 ESD Caution ................................................................................ 21 Pin Configuration and Function Descriptions ........................... 22 Typical Performance Characteristics ........................................... 24 MPU Port Description ................................................................... 29 I2C Operation .............................................................................. 29 Register Map Access ....................................................................... 31 Register Programming ............................................................... 31 Subaddress Register (SR7 to SR0) ............................................ 31 Input Configuration ....................................................................... 49 Standard Definition Only .......................................................... 49 Enhanced Definition/High Definition Only .......................... 51 Simultaneous Standard Definition and Enhanced Definition/High Definition ....................................................... 51 Enhanced Definition Only (at 54 MHz) ................................. 52 Output Configuration .................................................................... 53 Design Features ............................................................................... 54 Output Oversampling ................................................................ 54 HD Interlace External P_HSYNC and P_VSYNC Considerations ............................................................................ 54 ED/HD Timing Reset ................................................................ 55 SD Subcarrier Frequency Lock ................................................. 55 SD VCR FF/RW Sync ................................................................ 55 Vertical Blanking Interval ......................................................... 55 SD Subcarrier Frequency Control ............................................ 56 SD Noninterlaced Mode ............................................................ 56 SD Square Pixel Mode ............................................................... 56 Filters............................................................................................ 57 ED/HD Test Pattern Color Controls ....................................... 58 Color Space Conversion Matrix ............................................... 59 SD Luma and Color Scale Control ........................................... 60 SD Hue Adjust Control .............................................................. 60 SD Brightness Detect ................................................................. 61 SD Brightness Control ............................................................... 61 SD Input Standard Autodetection ............................................ 61 Double Buffering ........................................................................ 62 Programmable DAC Gain Control .......................................... 62 Gamma Correction .................................................................... 62 ED/HD Sharpness Filter and Adaptive Filter Controls ........ 64 ED/HD Sharpness Filter and Adaptive Filter Application Examples ...................................................................................... 65 SD Digital Noise Reduction ...................................................... 66 SD Active Video Edge Control ................................................. 67 External Horizontal and Vertical Synchronization Control . 69 Low Power Mode ........................................................................ 70 Cable Detection .......................................................................... 70 DAC Autopower-Down ............................................................. 70 Sleep Mode .................................................................................. 71 Pixel and Control Port Readback ............................................. 71 Reset Mechanism........................................................................ 71 SD Teletext Insertion ................................................................. 71 Printed Circuit Board Layout and Design .................................. 73 Unused Pins ................................................................................ 73 DAC Configurations .................................................................. 73 Voltage Reference ....................................................................... 73 Video Output Buffer and Optional Output Filter .................. 73 Printed Circuit Board (PCB) Layout ....................................... 74 Typical Application Circuit ....................................................... 76 Copy Generation Management System ....................................... 77 SD CGMS .................................................................................... 77 ED CGMS .................................................................................... 77

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Data Sheet ADV7340/ADV7341 Rev. C | Page 3 of 108 HD CGMS .................................................................................... 77 CGMS CRC Functionality ......................................................... 77 SD Wide Screen Signaling .............................................................. 80 SD Closed Captioning .................................................................... 81 Internal Test Pattern Generation ................................................... 82 SD Test Patterns ........................................................................... 82 ED/HD Test Patterns .................................................................. 82 SD Timing ........................................................................................ 83 HD Timing ....................................................................................... 89 Video Output Levels ....................................................................... 90 SD YPrPb Output Levels—SMPTE/EBU N10 ........................ 90 ED/HD YPrPb Output Levels ................................................... 91 SD/ED/HD RGB Output Levels ................................................ 92 SD Output Plots .......................................................................... 93 Video Standards .............................................................................. 94 Configuration Scripts ..................................................................... 96 Standard Definition .................................................................... 96 Enhanced Definition ................................................................ 100 High Definition ......................................................................... 104 Outline Dimensions ...................................................................... 108 Ordering Guide ......................................................................... 108

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ADV7340/ADV7341 Data Sheet Rev. C | Page 4 of 108 REVISION HISTORY 3/12—Rev. B to Rev. C Change to Features Section ............................................................. 1 Deleted Endnote 1 from Table 1 ..................................................... 5 Added Conditions to Digital Input/Output Specifications—1.8 V Section ............................................................................................................. 8 Changes to Pin 48 Description, Table 15 ..................................... 22 Changes to Table 21 ........................................................................ 35 Added Register 0x3A to Table 24 .................................................. 38 Changes to Table 29 ........................................................................ 42 Changes to Subaddress 0x87, Bit 7 = 1 Section .......................... 49 Deleted ED/HD Nontandard Timing Mode Section, Figure 59, Figure 60, Figure 61, and Table 42................................................ 53 Added External Sync Polarity Section ......................................... 54 Deleted Subcarrier Phase Reset (SCR) Mode and Timing Reset (TR) Mode Sections ....................................................................... 54 Renamed SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and Timing Reset Section to SD Subcarrier Frequency Lock Section .................................................................................... 55 Changes to ED/HD Test Patterns Section ................................... 82 9/11—Rev. A to Rev. B Changes to MPU Port Description Section ................................ 28 3/09—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Deleted Detailed Features Section, Changes to Table 1............... 4 Changes to Figure 1 .......................................................................... 5 Changes to Table 6 ............................................................................ 7 Added Digital Input/Output Specifications—1.8 V Section and Table 7 ................................................................................................ 7 Changes to Digital Timing Specifications—3.3 V Section and Table 8 ................................................................................................ 8 Added Table 9 .................................................................................... 9 Changes to MPU Port Timing Specifications Section, Default Conditions ......................................................................... 10 Deleted Figure 20 ............................................................................ 19 Changes to Table 13 ........................................................................ 20 Changes to Table 15 ........................................................................ 21 Changes to MPU Port Description Section ................................ 28 Changes to I2C Operation Section ............................................... 28 Added Table 16 ............................................................................... 28 Added Figure 49 ............................................................................. 29 Changes to Table 17 ....................................................................... 30 Changes to Table 18 ....................................................................... 30 Changes to Table 21, 0x30 Bit Description ................................. 34 Added Table 23 ............................................................................... 36 Changes to Table 29 ....................................................................... 41 Changes to Table 30 ....................................................................... 42 Changes to Table 31, 0xA0 Register Name ................................. 44 Changes to Table 32 ....................................................................... 46 Added Table 33 ............................................................................... 46 Added Table 34 ............................................................................... 47 Changes to Standard Definition Only Section ........................... 48 Changes to Figure 57...................................................................... 51 Renamed Features Section to Design Features Section ............. 53 Changes to ED/HD Nonstandard Timing Mode Section ......... 53 Added HD Interlace External P_HSYNC and P_VSYNC Considerations Section .................................................................. 54 Changes to SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and Timing Reset Section .................................................. 54 Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 56 Changes to Programming the FSC Section ................................... 56 Changes to Subaddress 0x82, Bit 4 Section ................................. 56 Added SD Manual CSC Matrix Adjust Feature Section ............ 59 Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 60 Changes to SD Brightness Detect Section ................................... 61 Changes to Figure 71...................................................................... 63 Added Sleep Mode Section ........................................................... 71 Changes to Pixel and Control Port Readback Section .............. 71 Changes to Reset Mechanism Section ......................................... 71 Added SD Teletext Insertion Section ........................................... 71 Added Figure 86 and Figure 87 .................................................... 73 Added Unused Pins Section .......................................................... 73 Changes to Power Supply Sequencing Section ........................... 75 Changes to Figure 94...................................................................... 78 Changes to SD Wide Screen Signaling Section .......................... 80 Changes to Internal Test Pattern Generation Section ............... 82 Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = XXXXX000) Section .................................. 83 Added Configuration Scripts Section .......................................... 96 10/06—Revision 0: Initial Version

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Data Sheet ADV7340/ADV7341 Rev. C | Page 5 of 108 GENERAL DESCRIPTION The ADV7340/ADV7341 are high speed, digital-to-analog video encoders in a 64-lead LQFP package. Six high speed, NSV, 3.3 V, 12-bit video DACs provide support for composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high definition (HD) video formats. The ADV7340/ADV7341 have a 30-bit pixel input port that can be configured in a variety of ways. SD video formats are supported over an SDR interface, and ED/HD video formats are supported over SDR and DDR interfaces. Pixel data can be supplied in either the YCrCb or RGB color space. The parts also support embedded EAV/SAV timing codes, external video synchronization signals, and I2C® communication protocol. In addition, simultaneous SD and ED/HD input and output are supported. Full-drive DACs ensure that external output buffering is not required, while 216 MHz (SD and ED) and 297 MHz (HD) oversampling ensures that external output filtering is not required. Cable detection and DAC autopower-down features keep power consumption to a minimum. Table 1 lists the video standards directly supported by the ADV7340/ADV7341. Table 1. Standards Directly Supported by the ADV7340/ ADV7341 Active Resolution I/P1 Frame Rate (Hz) Clock Input (MHz) Standard 720 × 240 P 59.94 27 720 × 288 P 50 27 720 × 480 I 29.97 27 ITU-R BT.601/656 720 × 576 I 25 27 ITU-R BT.601/656 640 × 480 I 29.97 24.54 NTSC Square Pixel 768 × 576 I 25 29.5 PAL Square Pixel 720 × 483 P 59.94 27 SMPTE 293M 720 × 483 P 59.94 27 BTA T-1004 720 × 483 P 59.94 27 ITU-R BT.1358 720 × 576 P 50 27 ITU-R BT.1358 720 × 483 P 59.94 27 ITU-R BT.1362 720 × 576 P 50 27 ITU-R BT.1362 1920 × 1035 I 30 74.25 SMPTE 240M 1920 × 1035 I 29.97 74.1758 SMPTE 240M 1280 × 720 P 60, 50, 30, 25, 24 74.25 SMPTE 296M 1280 × 720 P 23.97, 59.94, 29.97 74.1758 SMPTE 296M 1920 × 1080 I 30, 25 74.25 SMPTE 274M 1920 × 1080 I 29.97 74.1758 SMPTE 274M 1920 × 1080 P 30, 25, 24 74.25 SMPTE 274M 1920 × 1080 P 23.98, 29.97 74.1758 SMPTE 274M 1920 × 1080 P 24 74.25 ITU-R BT.709-5 1 I = interlaced, P = progressive.

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ADV7340/ADV7341 Data Sheet Rev. C | Page 6 of 108 FUNCTIONAL BLOCK DIAGRAM Figure 1. R GND_IO VDD_IO 8-/10-/16-/20-/ 24-/30-BIT SD VIDEO DATA VIDEO DATA S_HSYNCP_HSYNC P_VSYNC P_BLANK S_VSYNC 12-BIT DAC 1 DAC 1 12-BIT DAC 2 DAC 2 12-BIT DAC 3 DAC 3 12-BIT DAC 4 DAC 4 12-BIT DAC 5 DAC 5 12-BIT DAC 6 DAC 6 M U LT IP LE XE R REFERENCE AND CABLE DETECT 16x/4x OVERSAMPLING DAC PLLVIDEO TIMING GENERATOR POWER MANAGEMENT CONTROL CLKIN (2) PVDD PGND EXT_LF (2) VREF COMP (2) RSET (2) SDR/DDR ED/HD INPUT 4:2:2 TO 4:4:4 DEINTERLEAVE PROGRAMMABLE HDTV FILTERS SHARPNESS AND ADAPTIVE FILTER CONTROL YCbCr HDTV TEST PATTERN GENERATOR G/B RGB ASYNC BYPASS RGB DGND (2) VDD (2) SCL SDA ALSB SFL MPU PORT SUBCARRIER FREQUENCY LOCK (SFL) YCrCb TO RGB PROGRAMMABLE CHROMINANCE FILTER ADD BURST RGB TO YCrCb MATRIX 4:2:2 TO 4:4:4 SD DEINTERLEAVE SIN/COS DDS BLOCK 16× FILTER 16× FILTER 4× FILTER AGND VAA ADD SYNC VBI DATA SERVICE INSERTION PROGRAMMABLE LUMINANCE FILTER 06 39 8- 00 1 ADV7340/ADV7341 8-/10-/16-/20-/ 24-/30-BIT ED/HD YCbCr TO RGB MATRIX

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Data Sheet ADV7340/ADV7341 Rev. C | Page 7 of 108 SPECIFICATIONS POWER SUPPLY AND VOLTAGE SPECIFICATIONS All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 2. Parameter Min Typ Max Unit SUPPLY VOLTAGES VDD 1.71 1.8 1.89 V VDD_IO 1.71 3.3 3.63 V PVDD 1.71 1.8 1.89 V VAA 2.6 3.3 3.465 V POWER SUPPLY REJECTION RATIO 0.002 %/% VOLTAGE REFERENCE SPECIFICATIONS All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 3. Parameter Min Typ Max Unit Internal Reference Range, VREF 1.186 1.248 1.31 V External Reference Range, VREF 1.15 1.235 1.31 V External VREF Current1 ±10 µA 1 External current required to overdrive internal VREF. INPUT CLOCK SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 1.71 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 4. Parameter Conditions1 Min Typ Max Unit fCLKIN_A SD/ED 27 MHz fCLKIN_A ED (at 54 MHz) 54 MHz fCLKIN_A HD 74.25 MHz fCLKIN_B ED 27 MHz fCLKIN_B HD 74.25 MHz CLKIN_A High Time, t9 40 % of one clock cycle CLKIN_A Low Time, t10 40 % of one clock cycle CLKIN_B High Time, t9 40 % of one clock cycle CLKIN_B Low Time, t10 40 % of one clock cycle CLKIN_A Peak-to-Peak Jitter Tolerance 2 ±ns CLKIN_B Peak-to-Peak Jitter Tolerance 2 ±ns 1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.

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ADV7340/ADV7341 Data Sheet Rev. C | Page 8 of 108 ANALOG OUTPUT SPECIFICATIONS VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 1.71 V to 3.63 V. VREF = 1.235 V (driven externally). All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 5. Parameter Conditions Min Typ Max Unit Full-Drive Output Current (Full-Scale) RSET = 510 Ω, RL = 37.5 Ω 33 34.6 37 mA DAC 1, DAC 2, DAC 3 enabled1 RSET = 510 Ω, RL = 37.5 Ω 33 33.5 37 mA DAC 1 enabled only2 Low-Drive Output Current (Full-Scale)3 RSET = 4.12 kΩ, RL = 300 Ω 4.1 4.3 4.5 mA DAC-to-DAC Matching DAC 1 to DAC 6 1.0 % Output Compliance, VOC 0 1.4 V Output Capacitance, COUT DAC 1, DAC 2, DAC 3 10 pF DAC 4, DAC 5, DAC 6 6 pF Analog Output Delay4 DAC 1, DAC 2, DAC 3 8 ns DAC 4, DAC 5, DAC 6 6 ns DAC Analog Output Skew DAC 1, DAC 2, DAC 3 2 ns DAC 4, DAC 5, DAC 6 1 ns 1 Applicable to full-drive capable DACs only, that is, DAC 1, DAC 2, DAC 3. 2 The recommended method of bringing this typical value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12. 3 Applicable to all DACs. 4 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition. DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 6. Parameter Conditions Min Typ Max Unit Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Input Leakage Current, IIN VIN = VDD_IO ±10 µA Input Capacitance, CIN 4 pF Output High Voltage, VOH ISOURCE = 400 µA 2.4 V Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V Three-State Leakage Current VIN = 0.4 V, 2.4 V ±1.0 µA Three-State Output Capacitance 4 pF DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V When VDD_IO is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, VS, should use 1.8 V levels. VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 1.71 V to 1.89 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 7. Parameter Conditions Min Typ Max Unit Input High Voltage, VIH 0.7 VDD_IO V Input Low Voltage, VIL 0.3 VDD_IO V Input Capacitance, CIN 4 pF Output High Voltage, VOH ISOURCE = 400 µA VDD_IO – 0.4 V Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V Three-State Output Capacitance 4 pF

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Data Sheet ADV7340/ADV7341 Rev. C | Page 9 of 108 DIGITAL TIMING SPECIFICATIONS—3.3 V VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 8. Parameter Conditions1 Min Typ Max Unit VIDEO DATA AND VIDEO CONTROL PORT2, 3 Data Input Setup Time, t114 SD 2.1 ns ED/HD-SDR 2.3 ns ED/HD-DDR 2.3 ns ED (at 54 MHz) 1.7 ns Data Input Hold Time, t124 SD 1.0 ns ED/HD-SDR 1.1 ns ED/HD-DDR 1.1 ns ED (at 54 MHz) 1.0 ns Control Input Setup Time, t114 SD 2.1 ns ED/HD-SDR or ED/HD-DDR 2.3 ns ED (at 54 MHz) 1.7 ns Control Input Hold Time, t124 SD 1.0 ns ED/HD-SDR or ED/HD-DDR 1.1 ns ED (at 54 MHz) 1.0 ns Control Output Access Time, t134 SD 12 ns ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 10 ns Control Output Hold Time, t144 SD 4.0 ns ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 3.5 ns PIPELINE DELAY5 SD1 CVBS/YC Outputs (2×) SD oversampling disabled 68 Clock cycles CVBS/YC Outputs (16×) SD oversampling enabled 67 Clock cycles Component Outputs (2×) SD oversampling disabled 78 Clock cycles Component Outputs (16×) SD oversampling enabled 84 Clock cycles ED1 Component Outputs (1×) ED oversampling disabled 41 Clock cycles Component Outputs (8×) ED oversampling enabled 46 Clock cycles HD1 Component Outputs (1×) HD oversampling disabled 40 Clock cycles Component Outputs (4×) HD oversampling enabled 44 Clock cycles 1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. 2 Video data: C[9:0], Y[9:0], and S[9:0]. 3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design.

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November 6, 2020

Items arrived well pakaged, reasonable postage and as described. Top seller

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November 1, 2020

Item works as described, fast delivery, nice contact!

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October 20, 2020

Awesome!!! great prices, easy to order and great service, thank you!

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October 11, 2020

So far so good. I need to see how they hold up.

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October 11, 2020

FAST POSTING TOP CONDITION RECORD HAVE A GREAT CHRISTMAS

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October 10, 2020

Good communication and fast shipping! Recommended!

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