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AP7175SP-13

hot AP7175SP-13

AP7175SP-13

For Reference Only

Part Number AP7175SP-13
Manufacturer Diodes Incorporated
Description IC REG LINEAR POS ADJ 3A 8SO
Datasheet AP7175SP-13 Datasheet
Package 8-SOIC (0.154", 3.90mm Width) Exposed Pad
In Stock 8194 piece(s)
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AP7175SP-13

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AP7175SP-13 Specifications

ManufacturerDiodes Incorporated
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Linear
Datasheet AP7175SP-13 Datasheet
Package8-SOIC (0.154", 3.90mm Width) Exposed Pad
Series-
Output ConfigurationPositive
Output TypeAdjustable
Number of Regulators1
Voltage - Input (Max)3.65V
Voltage - Output (Min/Fixed)0.8V
Voltage - Output (Max)3.23V
Voltage Dropout (Max)0.42V @ 3A
Current - Output3A
Current - Supply1.5mA
Control FeaturesEnable, Power Good
Protection FeaturesOver Current, Over Temperature, Power On Reset (POR), Short Circuit, Soft Start
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width) Exposed Pad
Supplier Device Package8-SO-EP

AP7175SP-13 Datasheet

Page 1

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AP7175 Document number: DS35606 Rev. 4 - 3 1 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART 3A ULTRA LOW DROPOUT LINEAR REGULATOR WITH ENABLE Description The AP7175 is a 3.0A ultra low-dropout (LDO) linear regulator that features an enable input and a power-good output. The enable input and power-good output allow users to configure power management solutions that can meet the sequencing requirements of FPGAs, DSPs, and other applications with different start-up and power-down requirements. The AP7175 features two supply inputs, for power conversion supply and control. With the separation of the control and the power input very low dropout voltages can be reached and power dissipation is reduced. A precision reference and feedback control deliver 1.5% accuracy over load, line, and operating temperature ranges. The AP7175 is available in SO-8EP and MSOP-8EP package with an exposed PAD to reduce the junction to case resistance and extend the temperature range it can be used in. Features  VIN Range: 1.2V to 3.65V VCNTL 3.0V to 5.5V  Adjustable output voltage  Continuous Output Current IOUT = 3A  Fast transient response  Power on reset monitoring on VCNTL and VIN  Internal Softstart  Stable with Low ESR MLCC Capacitors  Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)  Halogen and Antimony Free. “Green” Device (Note 3) Pin Assignments GND FB VOUT EN PG VCNTL VIN SO-8EP (Top View) 8 7 6 5 1 2 3 4VOUT 2 GND FB VOUT EN PG VCNTL VIN MSOP-8EP (Top View) 1 3 4 8 7 6 5VOUT = PAD (connected to VIN) Applications  Notebook  PC  Netbook  Wireless Communication  Server  Motherboard  Dongle  Front Side Bus VTT (1.2V/3.3A) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. Typical Applications Circuit ON OFF PG VCNTL VIN EN VOUT FB GND C1R1 R2 CIN COUT CCNTL R3 *Optional 10µF 1µF 5.1KΩ 10µF 24KΩ 12KΩ AP7175 Figure 1. Typical Application Circuit

Page 3

AP7175 Document number: DS35606 Rev. 4 - 3 2 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Pin Descriptions Pin Name Pin Number Function SO-8EP MSOP-8EP GND 1 1 Ground FB 2 2 Feedback to set the output voltage via an external resistor divider between VOUT and GND. VOUT 3/4 3/4 Power Output Pin. Connect at least 10µF capacitor to this pin to improve transient response and required for stability. When the part is disabled the output is discharged via an internal pull-low MOSFET. VIN 5 5 Power Input Pin for current supply. Connect a decoupling capacitor (≥10µF) as close as possible to the pin for noise filtering. VCNTL 6 6 BIAS supply for the controller, recommended 5V. Connect a decoupling capacitor (≥1µF) as close as possible to the pin for noise filtering. PG 7 7 Power Good output open drain to indicate the status of VOUT via monitoring the FB pin. This pin is pulled low when the voltage is outside the limits, during thermal shutdown and if either VCNTL or VIN go below their thresholds. EN 8 8 Enable pin. Driving this pin low will disable the part. When left floating an internal current source will pull this pin high and enable it. PAD EP EP Exposed pad connect this to VIN for good thermal conductivity. Functional Block Diagram Power On Reset (POR) 5µA 0.8V Ref Control Logic SoftStart VCNTL EN Thermal Shutdown Current Limit and Short Circuit 0.8V Ref Delay POR 90%VRef VIN PG FB VOUT GND Error Amp

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AP7175 Document number: DS35606 Rev. 4 - 3 3 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.) Symbol Parameter Rating Unit VIN VIN Supply Voltage (VIN to GND) -0.3 to +4.0 V VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 to +7.0 V VOUT VOUT to GND Voltage -0.3 to VIN +0.3 V — PG to GND Voltage -0.3 to +7.0 V — EN, FB to GND Voltage -0.3 to VCNTL +0.3 V PD Power Dissipation (SO-8EP) 1.7 W Power Dissipation (MSOP-8EP) 1.5 W TJ Maximum Junction Temperature +150 °C TSTG Storage Temperature -65 to +150 °C TSDR Maximum Lead Soldering Temperature, 10 Seconds +260 °C Note: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above, may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VCNTL VCNTL Supply Voltage 3.0 5.5 V VIN VIN Supply Voltage 1.2 3.65 V VOUT VOUT Output Voltage (when VCNTL-VOUT >1.9V) 0.8 VIN - VDROP V IOUT VOUT Output Current Continuous Current 0 3 A Peak Current 0 4 COUT VOUT Output Capacitance IOUT = 3A at 25% nominal VOUT 8 1100 µF IOUT = 2A at 25% nominal VOUT 8 1700 IOUT = 1A at 25% nominal VOUT 8 2400 ESRCOUT ESR of VOUT Output Capacitor 0 200 mΩ TA Ambient Temperature -40 +85 °C TJ Junction Temperature -40 +125 °C

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AP7175 Document number: DS35606 Rev. 4 - 3 4 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Electrical Characteristics (VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40 to +85°C, @TA = +25°C, unless otherwise specified.) Symbol Parameter Test Conditions AP7175 Unit Min Typ Max SUPPLY CURRENT IVCNTL VCNTL Supply Current EN = VCNTL, IOUT=0A — 1.0 1.5 mA ISD VCNTL Supply Current at Shutdown EN = GND — 15 30 µA — VIN Supply Current at Shutdown EN = GND, VIN=3.65V — — 1 µA POWER-ON-RESET (POR) — Rising VCNTL POR Threshold — 2.5 2.7 2.95 V — VCNTL POR Hysteresis — — 0.4 — V — Rising VIN POR Threshold — 0.8 0.9 1.0 V — VIN POR Hysteresis — — 0.5 — V OUTPUT VOLTAGE VREF Reference Voltage FB = VOUT — 0.8 — V Output Voltage Accuracy VCNTL =3.0 V to 5.5V, IOUT = 0 to 3A, TJ = -40 to +125°C -1.5 — +1.5 % Load Regulation IOUT =0A to 3A — 0.06 0.25 % Line Regulation IOUT =10mA, VCNTL = 3.0 to 5.5V -0.15 — +0.15 %/V VOUT Pull-low Resistance VCNTL = 3.3V, VEN = 0V, VOUT < 0.8V — 10 — Ω FB Input Current VFB = 0.8V -100 — 100 nA DROPOUT VOLTAGE VDROP VIN-to-VOUT Dropout Voltage (Note 5) VCNTL = 5.0V, IOUT = 3A VOUT = 2.5V TJ = +25°C — 0.26 0.31 V TJ = -40 to +125°C — — 0.42 VOUT = 1.8V TJ = +25°C — 0.24 0.29 TJ = -40 to +125°C — — 0.40 VOUT = 1.2V TJ = +25°C — 0.23 0.28 TJ = -40 to +125°C — — 0.38 ILIM Current-Limit Level TJ = +25°C, VOUT = 80% VNOMINAL 4.5 5.7 6.7 A TJ = -40 to +125°C 4.2 — — A PROTECTIONS ISHORT Short Current-Limit Level VFB < 0.2V — 1.1 — A TSD Thermal Shutdown Temperature TJ rising — +170 — °C — Thermal Shutdown Hysteresis — — +50 — °C ENABLE AND SOFT-START — EN Logic High Threshold Voltage VEN rising 0.5 0.8 1.1 V — EN Hysteresis — — 0.1 — V — EN Pull-High Current EN = GND — 5 — µA tSS Soft-Start Interval — 0.3 0.6 1.2 ms — Turn On Delay From being enabled to VOUT rising 10% 200 350 500 µs POWER-GOOD AND DELAY VTHPG Rising PG Threshold Voltage VFB rising 90 92 95 % — PG Threshold Hysteresis — — 8 — % — PG Pull-low Voltage PG sinks 5mA — 0.25 0.4 V — PG Debounce Interval VFB < falling PG voltage threshold — 10 — µs — PG Delay Time From VFB = VTHPG to rising edge of the VPG 1 2 4 ms Note: 5. Dropout voltage is the voltage difference between the inut and the output at which the output voltage drops 2% below its nominal value.

Page 6

AP7175 Document number: DS35606 Rev. 4 - 3 5 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Electrical Characteristics (Cont.) (VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40 to +85°C, @TA = +25°C, unless otherwise specified.) Symbol Parameter Test Conditions AP7175 Unit Min Typ Max THERMAL CHARACTERISTIC θJA Thermal Resistance Junction-to-Ambient SO-8EP (Note 6) — 70 — C/W MSOP-8EP (Note 7) — 80 — C/W θJC Thermal Resistance Junction-to-Case SO-8EP (Note 6) — 30 — C/W MSOP-8EP (Note 7) — 30 — C/W Notes: 6. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer and thermal vias to bottom layer ground plane. 7. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. Typical Characteristics

Page 7

AP7175 Document number: DS35606 Rev. 4 - 3 6 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Typical Characteristics (Cont.)

Page 8

AP7175 Document number: DS35606 Rev. 4 - 3 7 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Power On COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 2ms/Div VIN VCNTL VOUT VPOK Power Off COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 2ms/Div VIN VCNTL VOUT VPOK Load Transient Response IOUT = 10mA to 3A to10mA (rise / fall time =1µs) COUT = 10µF, CIN = 10µF CH1: VOUT, 50mV/Div, AC CH2: IOUT, 1A/Div, DC TIME: 50µs/Div VOUT IOUT Over Current Protection COUT = 10µF, CIN = 10µF, IOUT = 2A to 5.6A CH1: VOUT, 0.5V/Div, DC CH2: IOUT, 2A/Div, DC TIME: 0.2ms/Div VOUT IOUT Operating Waveforms (@ VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V, TA = +25°C, unless otherwise specified.)

Page 9

AP7175 Document number: DS35606 Rev. 4 - 3 8 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Shutdown COUT = 10µF, CIN = 10µF, RL = 0.4Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 4µs/Div VEN VOUT VPOK IOUT Enable COUT = 10µF, CIN = 10µF, RL = 0.4Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 1ms/Div VEN VOUT VPOK IOUT Operating Waveforms (Cont.) (@ VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V, TA = +25°C, unless otherwise specified.)

Page 10

AP7175 Document number: DS35606 Rev. 4 - 3 9 of 14 www.diodes.com January 2017 © Diodes Incorporated AP7175 NOT RECOMMENDED FOR NEW DESIGN - NO ALTERNATE PART Application Information Power Good and Delay AP7175 monitors the feedback voltage VFB on the FB pin. An internal delay timer is started after the PG voltage threshold (VTHPG) on the FB pin is reached. At the end of the delay time an internal NMOS of the PG is turned off to indicate that the power at the output is good (PG). This monitoring function is continued during operation and if VFB falls 8% (typ) below VTHPG, the NMOS of the PG is turned on after a delay time of typical 10µs to avoid oscillating of the PG signal. Power On Reset AP7175 monitors both supply voltages, VCNTL and VIN to ensure operation as intended. A Soft-Start process is initiated after both voltages exceed their POR threshold during power on. During operation the POR component continues to monitor the supply voltage and pulls the PG low to indicate an out of regulation supply. This function will engage without regard to the status of the output. Soft-Start AP7175 incorporates an internal Soft-Start function. The output voltage rise is controlled to limit the current surge during start-up. The typical Soft-Start time is 0.6ms. Current-Limit Protection AP7175 monitors the current flow through the NMOS and limits the maximum current to avoid damage to the load and AP7175 during overload conditions. Short Circuit Current-Limit Protection AP7175 incorporates a current limit function to reduce the maximum current to 1.1A (typ) when the voltage at FB falls below 0.2V (typ) during an overload or short circuit situation. During start-up period, this function is disabled to ensure successful heavy load start-up. Enable Control If the enable pin (EN) is left open, an internal current source of ~5µA pulls the pin up and enables the AP7175. This will reduce the bill of material saving an external pull up resistor. Driving the enable pin low disables the device. Driving the pin high subsequently initiates a new Soft-Start cycle. Output Voltage Regulation Output Voltage is set by resistor divider from VOUT via FB pin to GND. Internally VFB is compared to a 0.8V temperature compensated reference voltage and the NMOS pass element regulates the output voltage while delivering current from VIN to VOUT. Setting the Output Voltage A resistor divider connected to FB pin programs the output voltage. V 2R 1R 1*VV REFOUT        R1 is connected from VOUT to FB with Kelvin sensing connection. R2 is connected from FB to GND. To improve load transient response and stability, a bypass capacitor can be connected in parallel with R1. (optional in typical application circuit) Power Sequencing AP7175 requires no specific sequencing between VIN and VCNTL. However, care should be taken to avoid forcing VOUT for prolonged time without the presence of VIN. Conduction through internal parasitic diode (from VOUT to VIN) could damage AP7175. Thermal Shutdown The PCB layout and power requirements for AP7175 under normal operation condition should allow enough cooling to restrict the junction temperature to +125°C. The packages for AP7175 have an exposed PAD to support this. These packages provide better connection to the PCB and thermal performance. Refer to the layout considerations. If AP7175 junction temperature reaches +170°C a thermal protection block disables the NMOS pass element and lets the part cool down. After its junction temperature drops by 50°C (typ), a new Soft-Start cycle will be initiated. A new thermal protection will start, if the load or ambient conditions continue to raise the junction temperature to +170°C. This cycle will repeat until normal operation temperature is maintained again.

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January 13, 2020

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November 24, 2019

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November 23, 2019

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June 4, 2019

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May 19, 2019

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February 28, 2019

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February 26, 2019

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February 21, 2019

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February 18, 2019

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