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AT24C04AN-10SI

AT24C04AN-10SI

AT24C04AN-10SI

For Reference Only

Part Number AT24C04AN-10SI
Manufacturer Microchip Technology
Description IC EEPROM 4KBIT 400KHZ 8SOIC
Datasheet AT24C04AN-10SI Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 252 piece(s)
Unit Price Request a Quote
Lead Time To be Confirmed
Estimated Delivery Time Jul 10 - Jul 15 (Choose Expedited Shipping)
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Part Number # AT24C04AN-10SI (Memory) is manufactured by Microchip Technology and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AT24C04AN-10SI Specifications

ManufacturerMicrochip Technology
CategoryIntegrated Circuits (ICs) - Memory
Datasheet AT24C04AN-10SIDatasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
Memory TypeNon-Volatile
Memory FormatEEPROM
TechnologyEEPROM
Memory Size4Kb (512 x 8)
Memory InterfaceI2C
Clock Frequency400kHz
Write Cycle Time - Word, Page5ms
Access Time900ns
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

AT24C04AN-10SI Datasheet

Page 1

Page 2

1 Features • Write Protect Pin for Hardware Data Protection – Utilizes Different Array Protection Compared to the AT24C02/04/08 • Low Voltage and Standard Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 2.5 (VCC = 2.5V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) • Internally Organized 256 x 8 (2K), 512 x 8 (4K) or 1024 x 8 (8K) • 2-Wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Supperssion • Bidirectional Data Transfer Protocol • 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility • 8-Byte Page (2K), 16-Byte Page (4K, 8K) Write Modes • Partial Page Writes Are Allowed • Self-Timed Write Cycle (10 ms max) • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3000V • Automotive Grade and Extended Temperature Devices Available • 8-Pin and 14-Pin JEDEC SOIC, 8-Pin PDIP, and 8-Pin TSSOP Packages Description The AT24C02A/04A/08A provides 2048/4096/8192 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 256/512/1024 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C02A/04A/08A is available in space saving 8-pin PDIP, 8-pin and 14-pin JEDEC SOIC, and 8-pin TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions. 2-Wire Serial EEPROM 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) AT24C02A AT24C04A AT24C08A Rev. 0976B–07/98 Pin Configurations Pin Name Function A0 - A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect 14-Pin SOIC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC A0 A1 NC A2 GND NC NC VCC WP NC SCL SDA NC 8-Pin PDIP 1 2 3 4 8 7 6 5 A0 A1 A2 GND VCC WP SCL SDA 8-Pin SOIC 1 2 3 4 8 7 6 5 A0 A1 A2 GND VCC WP SCL SDA AT24C02A/04A/ 08A 8-Pin TSSOP 1 2 3 4 8 7 6 5 A0 A1 A2 GND VCC WP SCL SDA

Page 3

AT24C02A/04A/08A2 Block Diagram Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The AT24C04A uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no con- nect. The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects. WRITE PROTECT (WP): The AT24C02A/04A/08A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage........................................... 6.25V DC Output Current........................................................ 5.0 mA

Page 4

AT24C02A/04A/08A 3 pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. Memory Organization AT24C02A, 2K SERIAL EEPROM: Internally organized with 256 pages of 1-byte each, the 2K requires an 8 bit data word address for random word addressing. AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 256 pages of 2-bytes each. Random word addressing requires a 9 bit data word address. AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 4 blocks of 256 pages of 4-bytes each. Random word addressing requires a 10 bit data word address. Note: 1. This parameter is characterized and is not 100% tested. Note: 1. VIL min and VIH max are reference only and are not tested. WP Pin Status Part of the Array Protected 24C02A 24C04A 24C08A At VCC Upper Half (1K) Array Upper Half (2K) Array Full (8K) Array At GND Normal Read/Write Operations Pin Capacitance Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V. Symbol Test Condition Max Units Conditions CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA VIL Input Low Level (1) -0.6 VCC x 0.3 V VIH Input High Level (1) VCC x 0.7 VCC + 0.5 V VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

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AT24C02A/04A/08A4 Note: 1. This parameter is characterized and is not 100% tested. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is nor- mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing dia- gram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are seri- ally transmitted to and from the EEPROM in 8 bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C02A/04A/08A features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by follow- ing these steps:(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high. AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter 2.7-, 2.5-, 1.8-volt 5.0-volt UnitsMin Max Min Max fSCL Clock Frequency, SCL 100 400 kHz tLOW Clock Pulse Width Low 4.7 1.2 µs tHIGH Clock Pulse Width High 4.0 0.6 µs tI Noise Suppression Time (1) 100 50 ns tAA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs tBUF Time the bus must be free before a new transmission can start(1) 4.7 1.2 µs tHD.STA Start Hold Time 4.0 0.6 µs tSU.STA Start Set-up Time 4.7 0.6 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Set-up Time 200 100 ns tR Inputs Rise Time (1) 1.0 0.3 µs tF Inputs Fall Time (1) 300 300 ns tSU.STO Stop Set-up Time 4.7 0.6 µs tDH Data Out Hold Time 100 50 ns tWR Write Cycle Time 10 10 ms Endurance(1) 5.0V, 25°C, Page Mode 1M 1M Write Cycles

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AT24C02A/04A/08A 5 Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O) Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle. SCL SDA 8th BIT WORD n ACK STOP CONDITION START CONDITION tWR (1)

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AT24C02A/04A/08A6 Data Validity Start and Stop Definition Output Acknowledge

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AT24C02A/04A/08A 7 Device Addressing The 2K, 4K and 8K EEPROM devices all require an 8 bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their correspond- ing hard-wired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The eighth bit of the device address is the read/write opera- tion select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. Write Operations BYTE WRITE: A write operation requires an 8 bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8 bit data word. Following receipt of the 8 bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2). PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K and 8K devices are capable of 16- byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcon- troller can transmit up to seven (2K) or fifteen (4K, 8K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3). The data word address lower three (2K) or four (4K, 8K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incre- mented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwrit- ten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are dis- abled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write opera- tions with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed dur- ing the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds

Page 9

AT24C02A/04A/08A8 with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con- tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6). Figure 1. Device Address Figure 2. Byte Write Figure 3. Page write MSD 2K LSB 1 A2 A0A1 R/W 4K 1 A2 P0A1 R/W 0 0 0 0 0 0 1 1 18K 1 A2 P0P1 R/W S T A R T M S B M S B L S B S T O P W R I T E SDA LINE DEVICE ADDRESS WORD ADDRESS DATA L S B A C K A C K A C K R / W S T A R T M S B S T O P W R I T E SDA LINE DEVICE ADDRESS WORD ADDRESS (n) DATA (n) DATA (n + 1) DATA (n + x) L S B A C K A C K A C K A C K A C K R / W

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AT24C02A/04A/08A 9 Figure 4. Current Address Read Figure 5. Random Read Figure 6. Sequential Read S T A R T R E A D M S B S T O P SDA LINE DEVICE ADDRESS DATAL S B A C K N O A C K R / W S T A R T S T A R T M S B S T O P W R I T E R E A D SDA LINE DEVICE ADDRESS DUMMY WRITE WORD ADDRESS n DEVICE ADDRESS DATA nL S B A C K A C K A C K N O A C K R / W M S B L S B M S B L S B

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June 30, 2020

I always have good experiences in dealing with Heisener Electronics. They have the components I need in stock, their search function is great, and shipping is fast and always as promised.

Virg***** Moody

June 28, 2020

The are the right size and type and do what they are designed to do.

Ami*****hite

June 26, 2020

I took time to note down but perfect after several months of use

Keny*****auhan

June 18, 2020

It gives you a good quality product, with a great variety.. I will for sure order this set again when i start to run low

Sere*****riggs

June 16, 2020

These were delivered very quickly and are fantastic selection of products.

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June 9, 2020

They worked as I expected. I'll definitely purchase again. Thank you!

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June 3, 2020

I wish I had come across Heisener first, no one could help me for 2 days. You are now saved into the TOP of my favorites web list. Thank you very much.

Lean*****hroff

June 3, 2020

Worked perfectly for my application. Worked like a charm!

Cyr*****Case

June 2, 2020

So far so good. I need to see how they hold up.

Kyle*****Dudley

May 27, 2020

Work Great. Would recommend. Only used 2. So I have 248 extras. Best deal by far that's why I got these.

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