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AT25BCM512B-MAH-T

hot AT25BCM512B-MAH-T

AT25BCM512B-MAH-T

For Reference Only

Part Number AT25BCM512B-MAH-T
Manufacturer Adesto Technologies
Description IC FLASH 512KBIT 70MHZ 8UDFN
Datasheet AT25BCM512B-MAH-T Datasheet
Package 8-UFDFN Exposed Pad
In Stock 18388 piece(s)
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AT25BCM512B-MAH-T Specifications

ManufacturerAdesto Technologies
CategoryIntegrated Circuits (ICs) - Memory
Datasheet AT25BCM512B-MAH-T Datasheet
Package8-UFDFN Exposed Pad
Series-
Memory TypeNon-Volatile
Memory FormatFLASH
TechnologyFLASH
Memory Size512Kb (64K x 8)
Clock Frequency70MHz
Write Cycle Time - Word, Page15µs, 5ms
Memory InterfaceSPI
Voltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C (TC)
Mounting TypeSurface Mount
Package / Case8-UFDFN Exposed Pad
Supplier Device Package8-UDFN (2x3)

AT25BCM512B-MAH-T Datasheet

Page 1

Page 2

512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory AT25BCM512B Preliminary 3704BX–DFLASH–11/2012Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 70 MHz Maximum Operating Frequency – Clock-to-Output (tV) of 6 ns Maximum • Flexible, Optimized Erase Architecture for Code + Data Storage Applications – Uniform 4-Kbyte Block Erase – Uniform 32-Kbyte Block Erase – Full Chip Erase • Hardware Controlled Locking of Protected Sectors via WP Pin • 128-Byte Programmable OTP Security Register • Flexible Programming – Byte/Page Program (1 to 256 Bytes) • Fast Program and Erase Times – 2.5 ms Typical Page Program (256 Bytes) Time – 100 ms Typical 4-Kbyte Block Erase Time – 500 ms Typical 32-Kbyte Block Erase Time • Automatic Checking and Reporting of Erase/Program Failures • JEDEC Standard Manufacturer and Device ID Read Methodology • Low Power Dissipation – 6 mA Active Read Current (Typical at 20 MHz) – 5 µA Deep Power-Down Current (Typical) • Endurance: 100,000 Program/Erase Cycles • Data Retention: 20 Years • Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-pad Ultra Thin DFN (2 x 3 x 0.6 mm) 1. Description The AT25BCM512B is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25BCM512B, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The erase block sizes of the AT25BCM512B have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The device also contains a specialized OTP (One-Time Programmable) Security Reg- ister that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. Specifically designed for use in 3-volt systems, the AT25BCM512B supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No sepa- rate voltage is required for programming and erasing.

Page 3

2. Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Symbol Name and Function Asserted State Type CS CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Low Input SCK SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. - Input SI SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). - Input SO SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted). - Output WP WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 11 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. Low Input HOLD HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 24 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. Low Input VCC DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. - Power GND GROUND: The ground reference for the power supply. GND should be connected to the system ground. - Power2 3704BX–DFLASH–11/2012 AT25BCM512B [Preliminary]

Page 4

AT25BCM512B [Preliminary]3. Block Diagram Figure 3-1. Block Diagram Figure 2-1. 8-UDFN (Top View) CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI FLASH MEMORY ARRAY Y-GATING CS SCK SO SI Y-DECODER A D D RE SS L AT C H X-DECODER I/O BUFFERS AND LATCHES CONTROL AND PROTECTION LOGIC SRAM DATA BUFFER WP INTERFACE CONTROL AND LOGIC HOLD3 3704BX–DFLASH–11/2012

Page 5

4. Memory Array To provide the greatest flexibility, the memory array of the AT25BCM512B can be erased in three levels of granularity including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the breakdown of each erase level. Figure 4-1. Memory Architecture Diagram4 3704BX–DFLASH–11/2012 AT25BCM512B [Preliminary]

Page 6

AT25BCM512B [Preliminary]5. Device Operation The AT25BCM512B is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25BCM512B via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25BCM512B supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. Figure 5-1. SPI Mode 0 and 3 6. Commands and Addressing A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and data bytes are trans- ferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25BCM512B will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no oper- ation will be performed and the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since the upper address limit of the AT25BCM512B memory array is 00FFFFh, address bits A23-A16 are always ignored by the device. SCK CS SI SO MSB LSB MSB LSB5 3704BX–DFLASH–11/2012

Page 7

Table 6-1. Command Listing Command Opcode Clock Frequency Address Bytes Dummy Bytes Data Bytes Read Commands Read Array 0Bh 0000 1011 Up to 70 MHz 3 1 1+ 03h 0000 0011 Up to 33 MHz 3 0 1+ Program and Erase Commands Block Erase (4 Kbytes) 20h 0010 0000 Up to 70 MHz 3 0 0 Block Erase (32 Kbytes) 52h 0101 0010 Up to 70 MHz 3 0 0 D8h 1101 1000 Up to 70 MHz 3 0 0 Chip Erase 60h 0110 0000 Up to 70 MHz 0 0 0 C7h 1100 0111 Up to 70 MHz 0 0 0 Chip Erase (Legacy Command) 62h 0110 0010 Up to 70 MHz 0 0 0 Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 Up to 70 MHz 3 0 1+ Protection Commands Write Enable 06h 0000 0110 Up to 70 MHz 0 0 0 Write Disable 04h 0000 0100 Up to 70 MHz 0 0 0 Security Commands Program OTP Security Register 9Bh 1001 1011 Up to 70 MHz 3 0 1+ Read OTP Security Register 77h 0111 0111 Up to 70 MHz 3 2 1+ Status Register Commands Read Status Register 05h 0000 0101 Up to 70 MHz 0 0 1+ Write Status Register 01h 0000 0001 Up to 70 MHz 0 0 1 Miscellaneous Commands Read Manufacturer and Device ID 9Fh 1001 1111 Up to 70 MHz 0 0 1 to 4 Read ID (Legacy Command) 15h 0001 0101 Up to 70 MHz 0 0 2 Deep Power-Down B9h 1011 1001 Up to 70 MHz 0 0 0 Resume from Deep Power-Down ABh 1010 1011 Up to 70 MHz 0 0 06 3704BX–DFLASH–11/2012 AT25BCM512B [Preliminary]

Page 8

AT25BCM512B [Preliminary]7. Read Commands 7.1 Read Array The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been speci- fied. The device incorporates an internal address counter that automatically increments on every clock cycle. Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency read operations up to the maximum specified by fRDLF. To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. Following the three address bytes, an additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation. After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (00FFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped- ance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array - 0Bh Opcode Figure 7-2. Read Array - 03h Opcode SCK CS SI SO MSB MSB 2 310 0 0 0 0 1 0 1 1 6 754 10 1198 12 39 42 43414037 3833 36353431 3229 30 44 47 484645 OPCODE A A A A A A AA A MSB X X X X X X X X MSB MSB D D D D D D D DDD ADDRESS BITS A23-A0 DON'T CARE DATA BYTE 1 HIGH-IMPEDANCE SCK CS SI SO MSB MSB 2 310 0 0 0 0 0 0 1 1 6 754 10 1198 12 37 3833 36353431 3229 30 39 40 OPCODE A A A A A A AA A MSB MSB D D D D D D D DDD ADDRESS BITS A23-A0 DATA BYTE 1 HIGH-IMPEDANCE7 3704BX–DFLASH–11/2012

Page 9

8. Program and Erase Commands 8.1 Byte/Page Program The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must have been previously issued to the device (see “Write Enable” on page 11) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state. To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro- gram it into the appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of tPP or tBP if only programming a single byte. The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be pro- grammed into the memory array. In addition, if the memory is in the protected state (see “Block Protection” on page 12), then the Byte/Page Program command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Sta- tus Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deas- serted on uneven byte boundaries, or because the memory location to be programmed is protected. While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.8 3704BX–DFLASH–11/2012 AT25BCM512B [Preliminary]

Page 10

AT25BCM512B [Preliminary]Figure 8-1. Byte Program Figure 8-2. Page Program 8.2 Block Erase A block of 4 or 32 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, and an opcode of 52h or D8h is used for a 32-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4- or 32-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas- serted, the device will erase the appropriate block. The erasing of the block is internally self- timed and should take place in a time of tBLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. SCK CS SI SO MSB MSB 2 310 0 0 0 0 0 0 1 0 6 754 10 1198 12 3937 3833 36353431 3229 30 OPCODE HIGH-IMPEDANCE A A A A A A AA A MSB D D D D D D D D ADDRESS BITS A23-A0 DATA IN SCK CS SI SO MSB MSB 2 310 0 0 0 0 0 0 1 0 6 754 98 3937 3833 36353431 3229 30 OPCODE HIGH-IMPEDANCE A A A A AA MSB D D D D D D D D ADDRESS BITS A23-A0 DATA IN BYTE 1 MSB D D D D D D D D DATA IN BYTE n9 3704BX–DFLASH–11/2012

AT25BCM512B-MAH-T Reviews

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Noem*****rton

January 11, 2020

Great product at a good price. No complaints.

Kyrie*****nagar

October 30, 2019

Best way to locate what I need, on a fast and efficient shipping! Keep up the good work!

Trent*****ughlin

August 19, 2019

Good and works well. What else is there to say about it.

Mar***** Deo

May 28, 2019

Wow super fast delivery, product as described good company!

Ryan*****amillo

May 17, 2019

This was a perfect replacement for the original mode. 5 minutes and it was up and running like new.

Eile*****ailey

April 28, 2019

Every time I order, I get it correctly filled and faster than most of website. For a friendly use operate system, you guys are the best!

Meli*****Abbott

April 19, 2019

They work great exactly what I needed.

Lara*****dhawa

March 25, 2019

You guys and girls are fantastic! The selection is fantastic and service is great.

Kael*****rtega

March 8, 2019

Items arrived well pakaged, reasonable postage and as described. Top seller

Octa*****Kant

March 8, 2019

Most of the reviews for this product were positive so I took a chance.

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