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AT29C512-15PC

hot AT29C512-15PC

AT29C512-15PC

For Reference Only

Part Number AT29C512-15PC
Manufacturer Microchip Technology
Description IC FLASH 512KBIT 150NS 32DIP
Datasheet AT29C512-15PC Datasheet
Package 32-DIP (0.600", 15.24mm)
In Stock 10880 piece(s)
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Lead Time Can Ship Immediately
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AT29C512-15PC

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AT29C512-15PC Specifications

ManufacturerMicrochip Technology
CategoryIntegrated Circuits (ICs) - Memory
Datasheet AT29C512-15PC Datasheet
Package32-DIP (0.600", 15.24mm)
Series-
Memory TypeNon-Volatile
Memory FormatFLASH
TechnologyFLASH
Memory Size512Kb (64K x 8)
Write Cycle Time - Word, Page10ms
Access Time150ns
Memory InterfaceParallel
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C (TC)
Mounting TypeThrough Hole
Package / Case32-DIP (0.600", 15.24mm)
Supplier Device Package32-DIP

AT29C512-15PC Datasheet

Page 1

Page 2

512K (64K x 8) 5-volt Only Flash Memory AT29C512Features • Fast Read Access Time – 70 ns • 5-volt Only Reprogramming • Sector Program Operation – Single Cycle Reprogram (Erase and Program) – 512 Sectors (128 Bytes/Sector) – Internal Address and Data Latches for 128 Bytes • Internal Program Control and Timer • Hardware and Software Data Protection • Fast Sector Program Cycle Time – 10 ms • DATA Polling for End of Program Detection • Low Power Dissipation – 50 mA Active Current – 100 µA CMOS Standby Current • Typical Endurance > 10,000 Cycles • Single 5V ± 10% Supply • CMOS and TTL Compatible Inputs and Outputs • Commercial and Industrial Temperature Ranges Description The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man- ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW over the commercial tem- perature range. When the device is deselected, the CMOS standby current is less than 100 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.Pin Configurations Pin Name Function A0 - A15 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No ConnectRev. 0456F–FLASH–12/02TSOP Top View Type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3DIP Top View PLCC Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A14 A13 A8 A9 A11 OE A10 CE I/O7 4 3 2 1 3 2 3 1 3 0 1 4 1 5 1 6 1 7 1 8 1 9 2 0 I/ O 1 I/ O 2 G N D I/ O 3 I/ O 4 I/ O 5 I/ O 6 A 1 2 A 1 5 N C N C V C C W E N C 1

Page 3

To allow for simple in-system reprogrammability, the AT29C512 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are loaded into the device and then simultaneously programmed. During a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can be g in . Block Diagram Device Operation READ: The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. BYTE LOAD: Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal program- ming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high-to-low tran- sition on WE (or CE) within 150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A7 to A15 specify the sector address. The sector address must be valid during each high-to-low transition of WE (or CE). A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation.2 AT29C512 0456F–FLASH–12/02

Page 4

AT29C512SOFTWARE DATA PROTECTION: A software controlled data protection feature is avail- able on the AT29C512. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program com- mands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the sector pro- gram timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data pro- tection feature; however, the software feature will guard against inadvertent program cycles during power transitions. Once set, software data protection will remain active unless the disable command sequence is issued. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the dura- tion of tWC, a read operation will effectively be a polling operation. After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro- grams to the AT29C512 in the following ways: (a) VCC sense – if VCC is below 3.8V (typical), the program function is inhibited; (b) VCC power on delay – once VCC has reached the VCC sense level, the device will automatically time out 5 ms (typical) before programming; (c) Pro- gram inhibit – holding any one of OE low, CE high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a pro- gram cycle. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identi- fication mode to identify the part (i.e., using the device code), and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.3 0456F–FLASH–12/02

Page 5

DATA POLLING: The AT29C512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the com- plement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT29C512 provides another method for deter- mining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin- ing the toggle bit may begin at any time during a program cycle. OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte soft- ware code. Please see Software Chip Erase application note for details. Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V4 AT29C512 0456F–FLASH–12/02

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AT29C512Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 4. Manufacturer Code: 1F, Device Code: 5D. 5. See details under Software Product Identification Entry/Exit. DC and AC Operating Range AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15 Operating Temperature (Case) Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C VCC Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10% Note: Not recommended for New Designs. Operating Modes Mode CE OE WE Ai I/O Read VIL VIL VIH Ai DOUT Program(2) VIL VIH VIL Ai DIN 5V Chip Erase VIL VIH VIL Ai Standby/Write Inhibit VIH X (1) X X High Z Program Inhibit X X VIH Program Inhibit X VIL X Output Disable X VIH X High Z Product Identification Hardware VIL VIL VIH A1 - A15 = VIL, A9 = VH, (3) A0 = VIL Manufacturer Code (4) A1-A15 = VIL, A9 = VH, (3) A0 = VIH Device Code (4) Software(5) A0 = VIL Manufacturer Code (4) A0 = VIH Device Code (4) DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current VIN = 0V to VCC 10 µA ILO Output Leakage Current VI/O = 0V to VCC 10 µA ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA Ind. 300 µA ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3 mA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage IOL = 2.1 mA 0.45 V VOH1 Output High Voltage IOH = -400 µA 2.4 V VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V5 0456F–FLASH–12/02

Page 7

AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. AC Read Characteristics Symbol Parameter AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15 UnitsMin Max Min Max Min Max Min Max tACC Address to Output Delay 70 90 120 150 ns tCE (1) CE to Output Delay 70 90 120 150 ns tOE (2) OE to Output Delay 0 35 0 40 0 50 0 70 ns tDF (3)(4) CE or OE to Output Float 0 10 0 25 0 30 0 40 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 0 0 0 ns Note: Not recommended for New Designs.6 AT29C512 0456F–FLASH–12/02

Page 8

AT29C512Input Test Waveforms and Measurement Level Output Test Load Note: 1. This parameter is characterized and is not 100% tested. tR, tF < 5 ns OUTPUT PIN 5.0V 30pF 1.8K 1.3K OUTPUT PIN 5.0V 100pF 1.8K 1.3K 70 ns 90/120/150 ns Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V7 0456F–FLASH–12/02

Page 9

AC Byte Load Waveforms WE Controlled CE Controlled AC Byte Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 90 ns tDS Data Set-up Time 35 ns tDH, tOEH Data, OE Hold Time 0 ns tWPH Write Pulse Width High 100 ns tDHtDS tAS tAH tWP CE ADDRESS DATA IN OE tOES tOEH WE tCS tCH tWPH tDHtDS tAS tAH tWP WE ADDRESS DATA IN OE tOES tOEH CE tCS tCH tWPH8 AT29C512 0456F–FLASH–12/02

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AT29C512Program Cycle Waveforms(1)(2)(3) Notes: 1. A7 through A15 must specify the sector address during each high-to-low transition of WE (or CE). 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the sector being programmed will be indeterminate. Program Cycle Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 35 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 90 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 100 ns9 0456F–FLASH–12/02

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