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AT89C51-24JI

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AT89C51-24JI

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Part Number AT89C51-24JI
Manufacturer Microchip Technology
Description IC MCU 8BIT 4KB FLASH 44PLCC
Datasheet AT89C51-24JI Datasheet
Package 44-LCC (J-Lead)
In Stock 11,714 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 1 - Jun 6 (Choose Expedited Shipping)
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Part Number # AT89C51-24JI (Embedded - Microcontrollers) is manufactured by Microchip Technology and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AT89C51-24JI Specifications

ManufacturerMicrochip Technology
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet AT89C51-24JIDatasheet
Package44-LCC (J-Lead)
Series89C
Core Processor8051
Core Size8-Bit
Speed24MHz
ConnectivityUART/USART
Peripherals-
Number of I/O32
Program Memory Size4KB (4K x 8)
Program Memory TypeFLASH
EEPROM Size-
RAM Size128 x 8
Voltage - Supply (Vcc/Vdd)4 V ~ 6 V
Data Converters-
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C
Mounting Type-
Package / Case44-LCC (J-Lead)
Supplier Device Package44-PLCC (16.59x16.59)

AT89C51-24JI Datasheet

Page 1

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8-bit Microcontroller with 4K Bytes Flash AT89C51 Not Recommended Features • Compatible with MCS-51™ Products • 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles • Fully Static Operation: 0 Hz to 24 MHz • Three-level Program Memory Lock • 128 x 8-bit Internal RAM • 32 Programmable I/O Lines • Two 16-bit Timer/Counters • Six Interrupt Sources • Programmable Serial Channel • Low-power Idle and Power-down Modes Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conven- tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.1 PQFP/TQFP 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 PO.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 (W R )P 3 .6 (R D ) P 3 .7 X T A L 2 X T A L 1 G N D G N D (A 8 ) P 2 .0 (A 9 ) P 2 .1 (A 1 0 ) P 2 .2 (A 1 1 ) P 2 .3 (A 1 2 ) P 2 .4 P 1 .4 P 1 .3 P 1 .2 P 1 .1 ( T 2 E X ) P 1 .0 ( T 2 ) N C V C C P 0 .0 ( A D 0 ) P 0 .1 ( A D 1 ) P 0 .2 ( A D 2 ) P 0 .3 ( A D 3 ) PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) Rev. 0265G–02/00 for New Designs. Use AT89S51. Pin Configurations PLCC 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 PO.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) 6 5 4 3 2 1 4 4 4 3 4 2 4 1 4 0 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 (W R )P 3 .6 (R D ) P 3 .7 X T A L 2 X T A L 1 G N D N C (A 8 ) P 2 .0 (A 9 ) P 2 .1 (A 1 0 ) P 2 .2 (A 1 1 ) P 2 .3 (A 1 2 ) P 2 .4 P 1 .4 P 1 .3 P 1 .2 P 1 .1 P 1 .0 N C V C C P 0 .0 ( A D 0 ) P 0 .1 ( A D 1 ) P 0 .2 ( A D 2 ) P 0 .3 ( A D 3 )

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AT89C512 Block Diagram PORT 2 DRIVERS PORT 2 LATCH P2.0 - P2.7 FLASH PORT 0 LATCHRAM PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTR RAM ADDR. REGISTER INSTRUCTION REGISTER B REGISTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS STACK POINTERACC TMP2 TMP1 ALU PSW TIMING AND CONTROL PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 PORT 1 LATCH PORT 1 DRIVERS P1.0 - P1.7 OSC GND VCC PSEN ALE/PROG EA / VPP RST PORT 0 DRIVERS P0.0 - P0.7

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AT89C51The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock cir- cuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 may also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash program- ming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data mem- ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash pro- gramming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external tim- ing or clocking purposes. Note, however, that one ALE Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)3

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pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur- ing a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external pro- gram memory. When the AT89C51 is executing code from external pro- gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable volt- age (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi- mum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on- chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe- cial functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execu- tion, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Figure 1. Oscillator Connections Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators C2 XTAL2 GND XTAL1 C1 Status of External Pins During Idle and Power-down Modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data DataAT89C514

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AT89C51Figure 2. External Clock Drive Configuration Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Regis- ters retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is nec- essary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Lock Bit Protection Modes Program Lock Bits Protection TypeLB1 LB2 LB3 1 U U U No program lock features 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled 3 P P U Same as mode 2, also verify is disabled 4 P P P Same as mode 3, also external execution is disabled5

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Programming the Flash The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage program- ming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third- party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table. The AT89C51 code memory array is programmed byte-by- byte in either programming mode. To program any non- blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps. 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage program- ming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indi- cate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com- plement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combi- nation of control signals. The write operation cycle is self- timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. VPP = 12V VPP = 5V Top-side Mark AT89C51 xxxx yyww AT89C51 xxxx-5 yyww Signature (030H) = 1EH (031H) = 51H (032H) =F FH (030H) = 1EH (031H) = 51H (032H) = 05HAT89C516

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AT89C51Note: 1. Chip Erase requires a 10 ms PROG pulse. Figure 3. Programming the Flash Figure 4. Verifying the Flash Flash Programming Modes Mode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7 Write Code Data H L H/12V L H H H Read Code Data H L H H L L H H Write Lock Bit - 1 H L H/12V H H H H Bit - 2 H L H/12V H H L L Bit - 3 H L H/12V H L H L Chip Erase H L H/12V H L L L Read Signature Byte H L H H L L L L (1) P1 P2.6 P3.6 P2.0 - P2.3 A0 - A7 ADDR. OOOOH/OFFFH T SEE FLASH PROGRAMMING MODES ABLE 3-24 MHz A8 - A11 P0 +5V P2.7 PGM DATA PROG V /VIH PP VIH ALE P3.7 XTAL2 EA RST PSEN XTAL1 GND VCC AT89C51 P1 P2.6 P3.6 P2.0 - P2.3 A0 - A7 ADDR. OOOOH/0FFFH 3-24 MHz A8 - A11 P0 +5V P2.7 PGM DATA (USE 10K PULLUPS) VIH VIH ALE P3.7 XTAL2 EA RST PSEN XTAL1 GND VCC AT89C51 T SEE FLASH PROGRAMMING MODES ABLE7

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Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V) Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V) tGLGH tGHSL tAVGL tSHGL tDVGL tGHAX tAVQV tGHDX tEHSH tELQV tWC BUSY READY tGHBL tEHQZ P1.0 - P1.7 P2.0 - P2.3 ALE/PROG PORT 0 LOGIC 1 LOGIC 0EA/VPP VPP P2.7 (ENABLE) P3.4 (RDY/BSY) PROGRAMMING ADDRESS VERIFICATION ADDRESS DATA IN DATA OUT tGLGH tAVGL tSHGL tDVGL tGHAX tAVQV tGHDX tEHSH tELQV tWC BUSY READY tGHBL tEHQZ P1.0 - P1.7 P2.0 - P2.3 ALE/PROG PORT 0 LOGIC 1 LOGIC 0EA/VPP P2.7 (ENABLE) P3.4 (RDY/BSY) PROGRAMMING ADDRESS VERIFICATION ADDRESS DATA IN DATA OUTAT89C518

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AT89C51Note: 1. Only used in 12-volt programming mode. Flash Programming and Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ± 10% Symbol Parameter Min Max Units VPP (1) Programming Enable Voltage 11.5 12.5 V IPP (1) Programming Enable Current 1.0 mA 1/tCLCL Oscillator Frequency 3 24 MHz tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold after PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL tSHGL VPP Setup to PROG Low 10 µs tGHSL (1) VPP Hold after PROG 10 µs tGLGH PROG Width 1 110 µs tAVQV Address to Data Valid 48tCLCL tELQV ENABLE Low to Data Valid 48tCLCL tEHQZ Data Float after ENABLE 0 48tCLCL tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 2.0 ms9

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