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Part Number AT90PWM3B-16SU
Manufacturer Microchip Technology
Description IC MCU 8BIT 8KB FLASH 32SOIC
Datasheet AT90PWM3B-16SU Datasheet
Package 32-SOIC (0.295", 7.50mm Width)
In Stock 319 piece(s)
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AT90PWM3B-16SU Specifications

ManufacturerMicrochip Technology
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet AT90PWM3B-16SUDatasheet
Package32-SOIC (0.295", 7.50mm Width)
SeriesAVR? 90PWM Lighting
Core ProcessorAVR
Core Size8-Bit
ConnectivitySPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number of I/O27
Program Memory Size8KB (8K x 8)
Program Memory TypeFLASH
EEPROM Size512 x 8
RAM Size512 x 8
Voltage - Supply (Vcc/Vdd)2.7 V ~ 5.5 V
Data ConvertersA/D 11x10b; D/A 1x10b
Oscillator TypeInternal
Operating Temperature-40°C ~ 105°C (TA)
Mounting Type-
Package / Case32-SOIC (0.295", 7.50mm Width)
Supplier Device Package32-SOIC

AT90PWM3B-16SU Datasheet

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4317KS–AVR–03/2013 8-bit Atmel Microcontroller with 8K Bytes In-System Programmable Flash AT90PWM2 AT90PWM3 AT90PWM2B AT90PWM3B SummaryFeatures • High Performance, Low Power Atmel® AVR® 8-bit Microcontroller • Advanced RISC Architecture – 129 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle Multiplier • Data and Non-Volatile Program Memory – 8K Bytes Flash of In-System Programmable Program Memory • Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – 512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 512 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • On Chip Debug Interface (debugWIRE) • Peripheral Features – Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement • Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time • Variable PWM duty Cycle and Frequency • Synchronous Update of all PWM Registers • Auto Stop Function for Event Driven PFC Implementation • Less than 25 Hz Step Width at 150 kHz Output Frequency • PSC2 with four Output Pins and Output Matrix – One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture Mode – One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode – Programmable Serial USART • Standard UART mode • 16/17 bit Biphase Mode for DALI Communications – Master/Slave SPI Serial Interface – 10-bit ADC • Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs • Programmable Gain (5x, 10x, 20x, 40x on Differential Channels) • Internal Reference Voltage – 10-bit DAC – Two or three Analog Comparator with Resistor-Array to Adjust Comparison Voltage – 4 External Interrupts – Programmable Watchdog Timer with Separate On-Chip Oscillator • Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes)

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AT90PWM2/3/2B/3B– In-System Programmable via SPI Port – Internal Calibrated RC Oscillator (8 MHz) – On-chip PLL for fast PWM (32 MHz, 64 MHz) and CPU (16 MHz) • Operating Voltage: 2.7V - 5.5V • Extended Operating Temperature: – -40C to +105C 1. History This datasheet deals with product characteristics of AT90PW2 and AT90WM3. It will be updated as soon as characterization will be done. 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized. Product Package 12 bit PWM with deadtime ADC Input ADC Diff Analog Compar Application AT90PWM2 AT90PWM2B SO24 2 x 2 8 1 2 One fluorescent ballast AT90PWM3 AT90PWM3B SO32, QFN32 3 x 2 11 2 3 HID ballast, fluorescent ballast, Motor control Product Revision AT90PWM2 AT90PWM3 First revision of parts, only for running production. AT90PWM2B AT90PWM3B Second revision of parts, for all new developments. The major changes are : • complement the PSCOUT01, PSCOUT11, PSCOUT21 polarity in centered mode - See “PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode” on page 140. • Add the PSC software triggering capture - See “PSC 0 Input Capture Register – PICR0H and PICR0L” on page 171. • Add bits to read the PSC output activity - See “PSC0 Interrupt Flag Register – PIFR0” on page 173. • Add some clock configurations - See “Device Clocking Options Select AT90PWM2B/3B” on page 31. • Change Amplifier Synchonization - See “Amplifier” on page 252. and See “” on page 254. • Correction of the Errata - See “Errata” on page 351.2 4317KS–AVR–03/2013

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AT90PWM2/3/2B/3B3. Pin Configurations Figure 3-1. SOIC 24-pin Package Figure 3-2. SOIC 32-pin Package AT90PWM2/2B SOIC24 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 (PSCOUT00/XCK/SS_A) PD0 (RESET/OCD) PE0 (PSCIN0/CLKO) PD1 (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 VCC GND (MISO/PSCOUT20) PB0 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 (ADC1/RXD/DALI/ICP1A/SCK_A) PD4 PB7(ADC4/PSCOUT01/SCK) PB6 (ADC7/ICP1B) PB5 (ADC6/INT2) PB4 (AMP0+) PB3 (AMP0-) AREF AGND AVCC PB2 (ADC5/INT1) PD7 (ACMP0) PD6 (ADC3/ACMPM/INT0) PD5 (ADC2/ACMP2) AT90PWM3/3B SOIC 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (PSCOUT00/XCK/SS_A) PD0 (INT3/PSCOUT10) PC0 (RESET/OCD) PE0 (PSCIN0/CLKO) PD1 (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 (PSCIN1/OC1B) PC1 VCC GND (T0/PSCOUT22) PC2 (T1/PSCOUT23) PC3 (MISO/PSCOUT20) PB0 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 (ADC1/RXD/DALI/ICP1A/SCK_A) PD4 PB7(ADC4/PSCOUT01/SCK) PB6 (ADC7/PSCOUT11/ICP1B) PB5 (ADC6/INT2) PC7 (D2A) PB4 (AMP0+) PB3 (AMP0-) PC6 (ADC10/ACMP1) AREF AGND AVCC PC5 (ADC9/AMP1+) PC4 (ADC8/AMP1-) PB2 (ADC5/INT1) PD7 (ACMP0) PD6 (ADC3/ACMPM/INT0) PD5 (ADC2/ACMP2)3 4317KS–AVR–03/2013

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AT90PWM2/3/2B/3BFigure 3-3. QFN32 (7*7 mm) Package. Note: The Center GND PADDLE has to be connected to GND. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 (PSCIN1/OC1B) PC1 VCC GND (T0/PSCOUT22) PC2 (T1/PSCOUT23) PC3 (MISO/PSCOUT20) PB0 PB4 (AMP0+) PB3 (AMP0-) PC6 (ADC10/ACMP1) AREF AGND AVCC PC5 (ADC9/AMP1+) PC4 (ADC8/AMP1-) 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 (M O S I/ P S C O U T 2 1 ) P B 1 (O C 0 B /X T A L 1 ) P E 1 (A D C 0 /X T A L 2 ) P E 2 (A D C 1 /R X D /D A L I/ IC P 1 _ A /S C K _ A ) P D 4 (A D C 2 /A C M P 2 ) P D 5 ( A D C 3 /A C M P M /I N T 0 ) P D 6 ( A C M P 0 ) P D 7 (A D C 5 /I N T 1 ) P B 2 P D 1 (P S C IN 0 /C L K O ) P E 0 ( R E S E T /O C D ) P C 0 (I N T 3 /P S C O U T 1 0 ) P D 0 ( P S C O U T 0 0 /X C K /S S _ A ) P B 7 ( A D C 4 /P S C O U T 0 1 /S C K ) P B 6 ( A D C 7 /P S C O U T 1 1 /I C P 1 B ) P B 5 ( A D C 6 /I N T 2 ) P C 7 ( D 2 A ) AT90PWM3/3B QFN 324 4317KS–AVR–03/2013

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AT90PWM2/3/2B/3B3.1 Pin Descriptions Table 3-1. Pin out description S024 Pin Number SO32 Pin Number QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function 7 9 5 GND Power Ground: 0V reference 18 24 20 AGND Power Analog Ground: 0V reference for analog part 6 8 4 VCC power Power Supply: 17 23 19 AVCC Power Analog Power Supply: This is the power supply voltage for analog part For a normal use this pin must be connected. 19 25 21 AREF Power Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog 8 12 8 PBO I/O MISO (SPI Master In Slave Out) PSCOUT20 output 9 13 9 PB1 I/O MOSI (SPI Master Out Slave In) PSCOUT21 output 16 20 16 PB2 I/O ADC5 (Analog Input Channel5 ) INT1 20 27 23 PB3 I/O AMP0- (Analog Differential Amplifier 0 Input Channel ) 21 28 24 PB4 I/O AMP0+ (Analog Differential Amplifier 0 Input Channel ) 22 30 26 PB5 I/O ADC6 (Analog Input Channel 6) INT 2 23 31 27 PB6 I/O ADC7 (Analog Input Channel 7) ICP1B (Timer 1 input capture alternate input) PSCOUT11 output (see note 1) 24 32 28 PB7 I/O PSCOUT01 output ADC4 (Analog Input Channel 4) SCK (SPI Clock)5 4317KS–AVR–03/2013

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AT90PWM2/3/2B/3BNA 2 30 PC0 I/O PSCOUT10 output (see note 1) INT3 7 3 PC1 I/O PSCIN1 (PSC 1 Digital Input) OC1B (Timer 1 Output Compare B) 10 6 PC2 I/O T0 (Timer 0 clock input) PSCOUT22 output 11 7 PC3 I/O T1 (Timer 1 clock input) PSCOUT23 output 21 17 PC4 I/O ADC8 (Analog Input Channel 8) AMP1- (Analog Differential Amplifier 1 Input Channel ) 22 18 PC5 I/O ADC9 (Analog Input Channel 9) AMP1+ (Analog Differential Amplifier 1 Input Channel ) 26 22 PC6 I/O ADC10 (Analog Input Channel 10) ACMP1 (Analog Comparator 1 Positive Input ) 29 25 PC7 I/O D2A : DAC output 1 1 29 PD0 I/O PSCOUT00 output XCK (UART Transfer Clock) SS_A (Alternate SPI Slave Select) 3 4 32 PD1 I/O PSCIN0 (PSC 0 Digital Input ) CLKO (System Clock Output) 4 5 1 PD2 I/O PSCIN2 (PSC 2 Digital Input) OC1A (Timer 1 Output Compare A) MISO_A (Programming & alternate SPI Master In Slave Out) 5 6 2 PD3 I/O TXD (Dali/UART Tx data) OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In) 12 16 12 PD4 I/O ADC1 (Analog Input Channel 1) RXD (Dali/UART Rx data) ICP1A (Timer 1 input capture) SCK_A (Programming & alternate SPI Clock) 13 17 13 PD5 I/O ADC2 (Analog Input Channel 2) ACMP2 (Analog Comparator 2 Positive Input ) 14 18 14 PD6 I/O ADC3 (Analog Input Channel 3 ) ACMPM reference for analog comparators INT0 15 19 15 PD7 I/O ACMP0 (Analog Comparator 0 Positive Input ) 2 3 31 PE0 I/O or I RESET (Reset Input) OCD (On Chip Debug I/O) 10 14 10 PE1 I/O XTAL1: XTAL Input OC0B (Timer 0 Output Compare B) Table 3-1. Pin out description (Continued) S024 Pin Number SO32 Pin Number QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function6 4317KS–AVR–03/2013

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AT90PWM2/3/2B/3B1. PSCOUT10 & PSCOUT11 are not present on 24 pins package 4. Overview The AT90PWM2/2B/3/3B is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM2/2B/3/3B achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 11 15 11 PE2 I/O XTAL2: XTAL OuTput ADC0 (Analog Input Channel 0) Table 3-1. Pin out description (Continued) S024 Pin Number SO32 Pin Number QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function7 4317KS–AVR–03/2013

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AT90PWM2/3/2B/3B4.1 Block Diagram Figure 4-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The AT90PWM2/2B/3/3B provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, three Power Stage Controllers, two flexible Timer/Counters with compare modes and PWM, one USART with DALI mode, an 11- channel 10-bit ADC with two differential input stage with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. 8Kx8 Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM 512 bytes Data Bus 8-bit Data SRAM 512 bytes D ir e c t A d d re s s in g In d ir e c t A d d re s s in g Interrupt Unit SPI Unit Watchdog Timer 3 Analog Comparators DAC ADC PSC 2/1/0 Timer 1 Timer 0 DALI USART8 4317KS–AVR–03/2013

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AT90PWM2/3/2B/3BThe Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switch- ing noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90PWM2/3 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90PWM2/3 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 4.2 Pin Descriptions 4.2.1 VCC Digital supply voltage. 4.2.2 GND Ground. 4.2.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed on page 69. 4.2.4 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C is not available on 24 pins package. Port C also serves the functions of special features of the AT90PWM2/2B/3/3B as listed on page 72.9 4317KS–AVR–03/2013

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November 18, 2020

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