with 1K Byte
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 89 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 12 MIPS Throughput at 12 MHz
• Data and Non-volatile Program Memory
– 1K Byte of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Selectable On-chip RC Oscillator for Zero External Components
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.0 mA
– Idle Mode: 0.4 mA
– Power-down Mode: <1 µA
• I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP, SOIC and SSOP
• Operating Voltages
– 2.7 - 6.0V (AT90S1200-4)
– 4.0 - 6.0V (AT90S1200-12)
• Speed Grades
– 0 - 4 MHz, (AT90S1200-4)
– 0 - 12 MHz, (AT90S1200-12)
Description The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S1200
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with the 32 general purpose working reg-
isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
Block Diagram Figure 1. The AT90S1200 Block Diagram
The architecture supports high-level languages efficiently as well as extremely dense
assembler code programs. The AT90S1200 provides the following features: 1K byte of
In-System Programmable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32
general purpose working registers, internal and external interrupts, programmable
watchdog timer with internal oscillator, an SPI serial port for program downloading and
two software selectable power-saving modes. The Idle Mode stops the CPU while allow-2 AT90S1200
AT90S1200ing the Registers, Timer/Counter, Watchdog and Interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscilla-
tor, disabling all other chip functions until the next External Interrupt or hardware Reset.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip In-System Programmable Flash allows the program memory to be repro-
grammed in-system through an SPI serial interface or by a conventional nonvolatile
memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-
grammable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful
microcontroller that provides a highly flexible and cost-effective solution to many embed-
ded control applications.
The AT90S1200 AVR is supported with a full suite of program and system development
tools including: macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
VCC Supply voltage pin.
GND Ground pin.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the
negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out-
put buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7
are used as inputs and are externally pulled low, they will source current if the internal
pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S1200 as listed
on page 30.
Port D (PD6..PD0) Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The
Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port D pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S1200 as listed
on page 34.
RESET Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the
clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.3
Figure 2. Oscillator Connections
Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be
connected as indicated in the figure.
Figure 3. External Clock Drive Configuration
On-chip RC Oscillator An On-chip RC Oscillator running at a fixed frequency of 1 MHz can be selected as the
MCU clock source. If enabled, the AT90S1200 can operate with no external compo-
nents. A control bit (RCEN) in the Flash Memory selects the On-chip RC Oscillator as
the clock source when programmed (“0”). The AT90S1200 is normally shipped with this
bit unprogrammed (“1”). Parts with this bit programmed can be ordered as
AT90S1200A. The RCEN-bit can be changed by parallel programming only. When
using the On-chip RC Oscillator for Serial Program downloading, the RCEN bit must be
programmed in Parallel Programming mode first.
MAX 1 HC BUFFER
The fast-access register file concept contains 32 x 8-bit general purpose working regis-
ters with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed, and the result is stored back in the register
file – in one clock cycle.
Figure 4. The AT90S1200 AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Har-
vard architecture concept – with separate memories and buses for program and data
memories. The program memory is accessed with a 2-stage pipeline. While one instruc-
tion is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Programmable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.5
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou-
tines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions such as
Control Registers, Timer/Counters, A/D Converters and other I/O functions. The mem-
ory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
rate interrupt vector in the in terrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt
vector position. The lower the interrupt vector address, the higher the priority.
Figure 5 shows the structure of the 32 general purpose registers in the CPU.
Figure 5. AVR CPU General Purpose Working Registers
All the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI
instruction for load immediate constant data. These instructions apply to the second half
of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND, OR
and all other operations between two registers or on a single register apply to the entire
Register 30 also serves as an 8-bit pointer for indirect address of the register file.
ALU – Arithmetic Logic
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, ALU operations between regis-
ters in the register file are executed. The ALU operations are divided into three main
categories – arithmetic, logic and bit-functions.
The AT90S1200 contains 1K bytes On-chip In-System Programmable Flash memory for
program storage. Since all instructions are single 16-bit words, the Flash is organized as
512 x 16. The Flash memory has an endurance of at least 1000 write/erase cycles.
The AT90S1200 Program Counter is 9 bits wide, thus addressing the 512 words Flash
See page 37 for a detailed description on Flash data downloading.
AT90S1200Program and Data
The AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressing
modes. This section describes the different addressing modes supported in the
AT90S1200. In the figures, OP means the operation code part of the instruction word.
To simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single
Figure 6. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Indirect Figure 7. Indirect Register Addressing
The register accessed is the one pointed to by the Z-register (R30).
Register Direct, Two Registers
Rd and Rr
Figure 8. Direct Register Addressing, Two Registers7
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
I/O Direct Figure 9. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or
source register address.
Relative Program Addressing,
RJMP and RCALL
Figure 10. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to
Subroutine and Interrupt
The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts. The
hardware stack is 9 bits wide and stores the Program Counter (PC) return address while
subroutines and interrupts are executed.
RCALL instructions and interrupts push the PC return address onto stack level 0, and
the data in the other stack levels 1 - 2 are pushed one level deeper in the stack. When a
RET or RETI instruction is executed the returning PC is fetched from stack level 0, and
the data in the other stack levels 1 - 2 are popped one level in the stack.
If more than three subsequent subroutine calls or interrupts are executed, the first val-
ues written to the stack are overwritten.8 AT90S1200
AT90S1200EEPROM Data Memory The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 25 specifying the EEPROM address register, the
EEPROM data register, and the EEPROM control register. For the SPI data download-
ing, see page 44 for a detailed description.
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 11 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipe-
lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 11. The Parallel Instruction Fetches and Instruction Executions
Figure 12 shows the internal timing concept for the register file. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 12. Single-cycle ALU Operation
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T49