Structure : Silicon Monolithic Integrated Circuit
Product Name : Power Driver For Compact Disc Players
Device Name : BA5826FP
Features : • 4-ch BTL driver
• Use of an HSOP28 power package can achieve downsizing of the set.
• Gain can be controlled by attaching an external resistance.
• A built-in thermal shutdown circuit installed.
• A built-in 3.3V regulator installed. (External PNP Tr must be installed.)
• A built-in general operational amplifier installed.
• A built-in 2.7V reset circuit installed.
• Using an external capacitor, the reset delay time can be changed.
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)]
Parameter Symbol Limits Unit
Power Supply Voltage VCC 13.5 V
Power Dissipation Pd 1.7 *1 W
Topr -35 to 85 °C
Tstg -55 to 150 °C
*1 When mounted on the glass/epoxy board with the size: 70 mm×70 mm, the thickness: 1.6 mm, and
the rate of copper foil occupancy area: 3% or less.
Over Ta=25°C, derating at the rate of 13.6mW/°C.
Parameter Symbol Limits Unit
Power Supply Voltage VCC 4.5 to 9 V
This product has not been checked for the strategic materials (or service) defined in the Foreign
Exchange and Foreign Trade Control Low of Japan so that a verification work is required before
Not designed for radiation resistance.
ELECTRIC CHARACTERISTICS (Ta=25°C, Vcc=8V, VBIAS=1.65V, RL=8Ω, unless otherwise noted.)
Parameter Symbol MIN. TYP. MAX Unit Condition
Circuit Current at no signal ICC 6.0 10.0 14.0 MA No load applied
Output Offset Voltage VOO1 -50 - 50 MV
Maximum Output Amplitude VOM1 4.35 5.0 - V VBIAS=4V
Closed Circuit Voltage Gain GVC1 6.0 8.0 10.0 DB
Output Offset Voltage VOO2 -50 - 50 mV
Maximum Output Amplitude VOM2 4.3 4.9 - V VBIAS=4V
Closed Circuit Voltage Gain GVC2 7.0 8.0 9.0 dB
Mute OFF Voltage VMTOFF 2.0 - - V
Mute ON Voltage VMTON - - 0.5 V
Bias Drop Mute Threshold
VBTHR - 0.7 1.2 V
<3.3V Regulator >
Output Voltage Vreg 3.13 3.3 3.47 V IL=100mA
Output Load Regulation ∆VRL -20 0 10 mV IL=100 to 200mA
Power Supply Voltage
Regulation ∆VVCC -10 0 35 mV (Vcc=6 to 9V) IL=100mA
Offset Voltage VOFOP -6 - 6 mV
Input Bias Current IBIAS - - 300 nA
High-level Output Voltage VOHOP 7.5 - - V VBIAS=4V
Low-level Output Voltage VOLOP - - 0.3 V VBIAS=4V
Output Driving Current
ISOU 300 500 - µA VBIAS=4V
Output Driving Current Sink ISIN 1 - - mA VBIAS=4V
Reset ON Threshold Voltage VTHR 2.56 2.7 2.84 V When Vreg drops
Reset ON Output Voltage VRON - - 0.5 V
Connected to 3.3V with the
resistance of 10kΩ applied.
IREST 16.6 23.7 30.8 µA
Reset τ Threshold Voltage H VRESTH 7.7 - - V VREST=1.5V
Reset τ Threshold Voltage L VRESTL - - 0.4 V VREST=1V
OUTLINE DIMENSIONS, SYMBOLS
(MAX 18.85 include BURR)
APPLICATION CIRCUIT DIAGRAM
T. S. D.: Thermal shutdown
Resistance unit: [Ω]
PIN NUMBERS, PIN NAMES
No. Pin Name Description No. Pin Name Description
1 VO1(-) Driver CH1 negative output 15 OPIN
Operational amplifier inverted
2 VO1(+) Driver CH1 positive output 16 RESETτ Reset τ terminal
3 IN1 CH1 input terminal 17 VO3(-) Driver CH3 negative output
4 RESET Reset output 18 VO3(+) Driver CH3 positive output
Regulator external Tr base connection
19 IN3 CH3 input terminal
6 REGOUT Regulator output 20 IN3’
CH3 input terminal for gain
7 MUTE Driver mute control terminal 21 VCC Power supply input
8 GND PREGND, REGGND 22 VCC Power supply input
9 IN2’ CH2 input terminal for gain control 23 BIAS Bias input
10 IN2 CH2 input terminal 24 IN4’
CH4 input terminal for gain
11 VO2(+) Driver CH2 positive output 25 IN4 CH4 input terminal
12 VO2(-) Driver CH2 negative output 26 VO4(+) Driver CH4 positive output
13 GND CH2,3 POWGND 27 VO4(-) Driver CH4 negative output
14 OPOUT Operational amplifier output 28 GND CH1,4 POWGND
Note: The positive or negative polarity of driver outputs is determined by the input polarity.
When the signal H is applied to the input pin, the negative output pin outputs L and the positive
output pin outputs H.
SERVO PRE AMP
CAUTIONS ON USE
(1) Relationship between the mute function and the reset output
Bias voltage drop ‘H’→‘L’
Thermal shutdown ‘H’→‘L’
Mute (pin 7)
ON in all cases
[Regulator Voltage Drop]
When the regulator voltage drops to 2.7V (typ.) or less, the reset output will become ‘L’ while the mute
function will turn ON and, when the voltage recovers to 2.9V (typ.) or above, the reset output will
become ‘H’ while the mute function will turn OFF.
When the bias terminal (pin 23) voltage has dropped to 0.7V (typ.) or less, the mute function will turn
ON while the reset output will become ‘L’. Under conditions of normal use, it should be set to 1.2V or
When the chip temperature has reached to 175°C (typ.) or above, the mute function will turn ON while
the reset output will become ‘L’. Ten the chip temperature has dropped to 150°C (typ.) or less, the
mute function will turn OFF while the reset output will become ‘H’.
When the mute terminal (pin 7) voltage has set to open or dropped to 0.5V (typ.) or less, the mute
function will turn ON while the reset output will not change.
(2) About reset τ terminal
Inserting a capacitor between the reset τ terminal (pin 16) and GND can set the delay time for the
The delay time t [sec] can be expressed by the following equation, where C[F] is a capacitance of
the capacitor to be connected;
When V=1.14[V], I=23.7[µA ] (typ.) and the capacitor with the capacitance of 4.7 µF is connected,
the delay time will become approximately 220msec.
(3) Thermal shutdown (TSD), mute ON, bias terminal voltage drop, or regulator voltage drop will activate
the mute function, where only the driver part can be muted. While muting, the voltage at the output
terminal will equal to the internal bias voltage (approximately (VCC-VF) / 2).
(4) The capacitor installed between the regulator output (pin 6) and GND also serves as an anti-oscillation
capacitor and therefore, it is required to have high performance in the temperature characteristics.
(5) While the regulator is not in use, the regulator output terminal (pin 6) must be shorted to VCC and the
regulator external Tr base connection terminal (pin 5) must be open.
(6) The radiating FIN must be connected to the external GND.
(7) Short-circuits between output pin-VCC, output pin-GND, or output terminals (load short) must be
avoided. Make sure that the ICs are installed on the board in proper directions.
Mounting the ICs in improper directions may damage them or produce smoke.
(8) About absolute maximum ratings
Exceeding the absolute maximum ratings, such as the applied voltage or the operating temperature
range, may cause permanent device damage. As these cases cannot be limited to the broken short
mode or the open mode, if a special mode where the absolute maximum ratings may be exceeded is
assumed, it is recommended to take mechanical safety measures such as attaching fuses.
(9) About power supply lines
As a measure against the back current regenerated by a counter electromotive force of the motor, a
capacitor to be used as a regenerated-current path can be installed between the power supply and
GND and its capacitance value should be determined after careful check that any problems, for
example, a leak capacitance of the electrolytic capacitor at low temperature, are not found in various
(10) About GND potential
The electric potential of the GND terminal must be kept lowest in the circuitry at any operation states.
(11) About thermal design
With consideration of the power dissipation (Pd) under conditions of actual use, a thermal design
provided with an enough margin should be done.
(12) About operations in a strong electric field
When used in a strong electric field, note that a malfunction may occur.
When using this IC, the output Tr. must be set not to exceed the values specified in the absolute
maximum ratings and ASO.
(14) Thermal shutdown circuit
This IC incorporates a thermal shutdown circuit (TSD circuit). When the chip temperature reaches the
value shown below, the coil output to the motor will be set to open.
The thermal shutdown circuit is designed only to shut off the IC from a thermal runaway and not
intended to protect or guarantee the entire IC functions.
Therefore, users cannot assume that the TSD circuit once activated can be used continuously in the
TSD ON Temperature
(15) About earth wiring patterns
When a small signal GND and a large current GND are provided, it is recommended that the large
current GND pattern and the small signal GND pattern should be separated and grounded at a single
point of the reference point of the set in order to prevent the voltage of the small signal GND from being
affected by a voltage change caused by the resistance of the pattern wiring and the large current.
Make sure that the GND wiring patterns of the external components will not change, too.
(16) This IC is a monolithic IC which has a P+ isolations and P substrate to isolate elements each other.
This P layer and an N layer in each element form a PN junction to construct various parasitic elements.
Due to the IC structure, the parasitic elements are inevitably created by the potential relationship.
Activation of the parasitic elements can cause interference between circuits and may result in a
malfunction or, consequently, a fatal damage. Therefore, make sure that the IC must not be used
under conditions that may activate the parasitic elements, for example, applying the lower voltage than
the ground level (GND, P substrate) to the input terminals.
Note that, while not applying the power supply voltage to the IC, any voltage must not be applied to the
input terminals. In addition, do not applying the voltage to input terminals without applying the power
supply voltage to the IC. Also while applying the power supply voltage, each input terminal must be
the power supply voltage or less; or within the guaranteed values in the electric characteristics.