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C8051F301

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C8051F301

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Part Number C8051F301
Manufacturer Silicon Labs
Description IC MCU 8BIT 8KB FLASH 11QFN
Datasheet C8051F301 Datasheet
Package 10-VFDFN Exposed Pad
In Stock 8,132 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 21 - Sep 26 (Choose Expedited Shipping)
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Part Number # C8051F301 (Embedded - Microcontrollers) is manufactured by Silicon Labs and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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C8051F301 Specifications

ManufacturerSilicon Labs
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet C8051F301Datasheet
Package10-VFDFN Exposed Pad
SeriesC8051F30x
Core Processor8051
Core Size8-Bit
Speed25MHz
ConnectivitySMBus (2-Wire/I2C), UART/USART
PeripheralsPOR, PWM, WDT
Number of I/O8
Program Memory Size8KB (8K x 8)
Program Memory TypeFLASH
EEPROM Size-
RAM Size256 x 8
Voltage - Supply (Vcc/Vdd)2.7 V ~ 3.6 V
Data Converters-
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C (TA)
Mounting Type-
Package / Case10-VFDFN Exposed Pad
Supplier Device Package11-QFN (3x3)

C8051F301 Datasheet

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Mixed Signal ISP Flash MCU Family C8051F300/1/2/3/4/5 ReAnalog Peripherals - 8-Bit ADC ('F300/2 only) • Up to 500 ksps • Up to 8 external inputs • Programmable amplifier gains of 4, 2, 1, & 0.5 • VREF from external pin or VDD • Built-in temperature sensor • External conversion start input - Comparator • Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current (<0.5 µA) On-chip Debug - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) - Provides breakpoints, single stepping, inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - Complete development kit Supply Voltage 2.7 to 3.6 V - Typical operating current: 6.6 mA @ 25 MHz; 14 µA @ 32 kHz - Typical stop mode current: 0.1 µA - Temperature range: –40 to +85 °C High Speed 8051 µc Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 256 bytes internal data RAM - Up to 8 kB (‘F300/1/2/3), 4 kB (‘F304), or 2 kB (‘F305) Flash; 512 bytes are reserved in the 8 kB devices Digital Peripherals - 8 Port I/O; All 5 V tolerant with high sink current - Hardware enhanced UART and SMBus™ serial ports - Three general-purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with three capture/compare modules - Real time clock mode using PCA or timer and external clock source Clock Sources - Internal oscillator: 24.5 MHz with ±2% accuracy supports UART operation - External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) - Can switch between clock sources on-the-fly; Useful in power saving modes 11-Pin QFN or 14-Pin SOIC Package - QFN Size = 3x3 mmv. 2.9 7/08 Copyright © 2008 by Silicon Laboratories C8051F300/1/2/3/4/5 ANALOG PERIPHERALS PGA 8/4/2 kBytes ISP Flash 256 B SRAM POR DEBUG CIRCUITRY 12 INTERRUPTS 8051 CPU (25MIPS) DIGITAL I/O PROGRAMMABLE PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE A M U X I/O P or t C R O S S B A R UART SMBus PCA Timer 0 Timer 1 Timer 2 VOLTAGE COMPARATOR + - WDT 8-bit 500 ksps ADC TEMP SENSOR C8051F300/2 only

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C8051F300/1/2/3/4/5NOTES:2 Rev. 2.9

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C8051F300/1/2/3/4/5Table of Contents 1. System Overview.................................................................................................... 13 1.1. CIP-51™ Microcontroller Core.......................................................................... 16 1.1.1. Fully 8051 Compatible.............................................................................. 16 1.1.2. Improved Throughput ............................................................................... 16 1.1.3. Additional Features .................................................................................. 17 1.2. On-Chip Memory............................................................................................... 18 1.3. On-Chip Debug Circuitry................................................................................... 19 1.4. Programmable Digital I/O and Crossbar ........................................................... 19 1.5. Serial Ports ....................................................................................................... 20 1.6. Programmable Counter Array ........................................................................... 21 1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) ..................................... 22 1.8. Comparator ....................................................................................................... 23 2. Absolute Maximum Ratings .................................................................................. 24 3. Global Electrical Characteristics .......................................................................... 25 4. Pinout and Package Definitions............................................................................ 27 5. ADC0 (8-Bit ADC, C8051F300/2)............................................................................ 35 5.1. Analog Multiplexer and PGA............................................................................. 36 5.2. Temperature Sensor ......................................................................................... 36 5.3. Modes of Operation .......................................................................................... 39 5.3.1. Starting a Conversion............................................................................... 39 5.3.2. Tracking Modes........................................................................................ 40 5.3.3. Settling Time Requirements ..................................................................... 41 5.4. Programmable Window Detector ...................................................................... 45 5.4.1. Window Detector In Single-Ended Mode ................................................. 45 5.4.2. Window Detector In Differential Mode...................................................... 46 6. Voltage Reference (C8051F300/2) ......................................................................... 49 7. Comparator0 ........................................................................................................... 51 8. CIP-51 Microcontroller ........................................................................................... 57 8.1. Instruction Set ................................................................................................... 58 8.1.1. Instruction and CPU Timing ..................................................................... 58 8.1.2. MOVX Instruction and Program Memory ................................................. 59 8.2. Memory Organization........................................................................................ 63 8.2.1. Program Memory...................................................................................... 63 8.2.2. Data Memory............................................................................................ 64 8.2.3. General Purpose Registers ...................................................................... 64 8.2.4. Bit Addressable Locations........................................................................ 65 8.2.5. Stack ....................................................................................................... 65 8.2.6. Special Function Registers....................................................................... 65 8.2.7. Register Descriptions ............................................................................... 68 8.3. Interrupt Handler ............................................................................................... 72 8.3.1. MCU Interrupt Sources and Vectors ........................................................ 72 8.3.2. External Interrupts .................................................................................... 73 8.3.3. Interrupt Priorities ..................................................................................... 73Rev. 2.9 3

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C8051F300/1/2/3/4/58.3.4. Interrupt Latency ...................................................................................... 73 8.3.5. Interrupt Register Descriptions................................................................. 75 8.4. Power Management Modes .............................................................................. 80 8.4.1. Idle Mode.................................................................................................. 80 8.4.2. Stop Mode................................................................................................ 81 9. Reset Sources......................................................................................................... 83 9.1. Power-On Reset ............................................................................................... 84 9.2. Power-Fail Reset/VDD Monitor......................................................................... 84 9.3. External Reset .................................................................................................. 85 9.4. Missing Clock Detector Reset........................................................................... 85 9.5. Comparator0 Reset........................................................................................... 85 9.6. PCA Watchdog Timer Reset............................................................................. 85 9.7. Flash Error Reset.............................................................................................. 86 9.8. Software Reset ................................................................................................. 86 10.Flash Memory ......................................................................................................... 89 10.1.Programming The Flash Memory ..................................................................... 89 10.1.1.Flash Lock and Key Functions................................................................. 89 10.1.2.Flash Erase Procedure ............................................................................ 89 10.1.3.Flash Write Procedure ............................................................................. 90 10.2.Non-Volatile Data Storage................................................................................ 90 10.3.Security Options ............................................................................................... 90 10.4.Flash Write and Erase Guidelines .................................................................... 94 10.4.1.VDD Maintenance and the VDD monitor ................................................... 94 10.4.2.PSWE Maintenance................................................................................. 94 10.4.3.System Clock ........................................................................................... 95 11.Oscillators............................................................................................................... 97 11.1.Programmable Internal Oscillator ..................................................................... 97 11.2.External Oscillator Drive Circuit........................................................................ 99 11.3.System Clock Selection.................................................................................... 99 11.4.External Crystal Example ............................................................................... 101 11.5.External RC Example ..................................................................................... 102 11.6.External Capacitor Example ........................................................................... 102 12.Port Input/Output.................................................................................................. 103 12.1.Priority Crossbar Decoder .............................................................................. 104 12.2.Port I/O Initialization ....................................................................................... 106 12.3.General Purpose Port I/O............................................................................... 108 13.SMBus ................................................................................................................... 111 13.1.Supporting Documents ................................................................................... 112 13.2.SMBus Configuration...................................................................................... 112 13.3.SMBus Operation ........................................................................................... 112 13.3.1.Arbitration............................................................................................... 113 13.3.2.Clock Low Extension.............................................................................. 114 13.3.3.SCL Low Timeout................................................................................... 114 13.3.4.SCL High (SMBus Free) Timeout .......................................................... 1144 Rev. 2.9

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C8051F300/1/2/3/4/513.4.Using the SMBus............................................................................................ 115 13.4.1.SMBus Configuration Register............................................................... 116 13.4.2.SMB0CN Control Register ..................................................................... 119 13.4.3.Data Register ......................................................................................... 122 13.5.SMBus Transfer Modes.................................................................................. 123 13.5.1.Master Transmitter Mode....................................................................... 123 13.5.2.Master Receiver Mode........................................................................... 124 13.5.3.Slave Receiver Mode............................................................................. 125 13.5.4.Slave Transmitter Mode......................................................................... 126 13.6.SMBus Status Decoding................................................................................. 127 14.UART0.................................................................................................................... 131 14.1.Enhanced Baud Rate Generation................................................................... 132 14.2.Operational Modes ......................................................................................... 133 14.2.1.8-Bit UART............................................................................................. 133 14.2.2.9-Bit UART............................................................................................. 134 14.3.Multiprocessor Communications .................................................................... 135 15.Timers.................................................................................................................... 143 15.1.Timer 0 and Timer 1 ....................................................................................... 143 15.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 143 15.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 145 15.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 145 15.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 146 15.2.Timer 2 .......................................................................................................... 151 15.2.1.16-bit Timer with Auto-Reload................................................................ 151 15.2.2.8-bit Timers with Auto-Reload................................................................ 152 16.Programmable Counter Array ............................................................................. 155 16.1.PCA Counter/Timer ........................................................................................ 156 16.2.Capture/Compare Modules ............................................................................ 157 16.2.1.Edge-triggered Capture Mode................................................................ 158 16.2.2.Software Timer (Compare) Mode........................................................... 159 16.2.3.High Speed Output Mode....................................................................... 160 16.2.4.Frequency Output Mode ........................................................................ 161 16.2.5.8-Bit Pulse Width Modulator Mode......................................................... 162 16.2.6.16-Bit Pulse Width Modulator Mode....................................................... 163 16.3.Watchdog Timer Mode ................................................................................... 164 16.3.1.Watchdog Timer Operation .................................................................... 164 16.3.2.Watchdog Timer Usage ......................................................................... 165 16.4.Register Descriptions for PCA........................................................................ 167 17.C2 Interface........................................................................................................... 173 17.1.C2 Interface Registers.................................................................................... 173 17.2.C2 Pin Sharing ............................................................................................... 175 Document Change List............................................................................................. 176 Contact Information.................................................................................................. 178Rev. 2.9 5

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C8051F300/1/2/3/4/5NOTES:6 Rev. 2.9

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C8051F300/1/2/3/4/5List of Figures 1. System Overview Figure 1.1. C8051F300/2 Block Diagram................................................................. 15 Figure 1.2. C8051F301/3/4/5 Block Diagram........................................................... 15 Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 16 Figure 1.4. On-Chip Clock and Reset ...................................................................... 17 Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown) ................................. 18 Figure 1.6. Development/In-System Debug Diagram............................................... 19 Figure 1.7. Digital Crossbar Diagram....................................................................... 20 Figure 1.8. PCA Block Diagram ............................................................................... 21 Figure 1.9. PCA Block Diagram ............................................................................... 21 Figure 1.10. 8-Bit ADC Block Diagram..................................................................... 22 Figure 1.11. Comparator Block Diagram.................................................................. 23 2. Absolute Maximum Ratings 3. Global Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. QFN-11 Pinout Diagram (Top View) ...................................................... 28 Figure 4.2. QFN-11 Package Drawing ..................................................................... 29 Figure 4.3. Typical QFN-11 Solder Paste Mask....................................................... 30 Figure 4.4. Typical QFN-11 Landing Diagram.......................................................... 31 Figure 4.5. SOIC-14 Pinout Diagram (Top View) ..................................................... 32 Figure 4.6. SOIC-14 Package Drawing .................................................................... 33 Figure 4.7. SOIC-14 PCB Land Pattern ................................................................... 34 5. ADC0 (8-Bit ADC, C8051F300/2) Figure 5.1. ADC0 Functional Block Diagram............................................................ 35 Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 37 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 38 Figure 5.4. 8-Bit ADC Track and Conversion Example Timing ................................ 40 Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 41 Figure 5.6. ADC Window Compare Examples, Single-Ended Mode........................ 45 Figure 5.7. ADC Window Compare Examples, Differential Mode ............................ 46 6. Voltage Reference (C8051F300/2) Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 49 7. Comparator0 Figure 7.1. Comparator0 Functional Block Diagram ................................................ 51 Figure 7.2. Comparator Hysteresis Plot ................................................................... 52 8. CIP-51 Microcontroller Figure 8.1. CIP-51 Block Diagram............................................................................ 57 Figure 8.2. Program Memory Maps.......................................................................... 63 Figure 8.3. Data Memory Map.................................................................................. 64 9. Reset Sources Figure 9.1. Reset Sources........................................................................................ 83 Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 84Rev. 2.9 7

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C8051F300/1/2/3/4/510.Flash Memory Figure 10.1. Flash Program Memory Map................................................................ 91 11.Oscillators Figure 11.1. Oscillator Diagram................................................................................ 97 Figure 11.2. 32.768 kHz External Crystal Example................................................ 101 12.Port Input/Output Figure 12.1. Port I/O Functional Block Diagram..................................................... 103 Figure 12.2. Port I/O Cell Block Diagram ............................................................... 103 Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 104 Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 105 13.SMBus Figure 13.1. SMBus Block Diagram ....................................................................... 111 Figure 13.2. Typical SMBus Configuration ............................................................. 112 Figure 13.3. SMBus Transaction ............................................................................ 113 Figure 13.4. Typical SMBus SCL Generation......................................................... 117 Figure 13.5. Typical Master Transmitter Sequence................................................ 123 Figure 13.6. Typical Master Receiver Sequence.................................................... 124 Figure 13.7. Typical Slave Receiver Sequence...................................................... 125 Figure 13.8. Typical Slave Transmitter Sequence.................................................. 126 14.UART0 Figure 14.1. UART0 Block Diagram ....................................................................... 131 Figure 14.2. UART0 Baud Rate Logic .................................................................... 132 Figure 14.3. UART Interconnect Diagram .............................................................. 133 Figure 14.4. 8-Bit UART Timing Diagram............................................................... 133 Figure 14.5. 9-Bit UART Timing Diagram............................................................... 134 Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 135 15.Timers Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 144 Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 145 Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 146 Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 151 Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 152 16.Programmable Counter Array Figure 16.1. PCA Block Diagram............................................................................ 155 Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 156 Figure 16.3. PCA Interrupt Block Diagram ............................................................. 157 Figure 16.4. PCA Capture Mode Diagram.............................................................. 158 Figure 16.5. PCA Software Timer Mode Diagram.................................................. 159 Figure 16.6. PCA High Speed Output Mode Diagram............................................ 160 Figure 16.7. PCA Frequency Output Mode ............................................................ 161 Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 162 Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 163 Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 164 17.C2 Interface Figure 17.1. Typical C2 Pin Sharing....................................................................... 1758 Rev. 2.9

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C8051F300/1/2/3/4/5List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 14 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings .................................................................... 24 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics ............................................................. 25 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 ........................................... 27 Table 4.2. QFN-11 Package Dimensions ................................................................ 29 Table 4.3. QFN-11 Landing Diagram Dimensions ................................................... 31 Table 4.4. SOIC-14 Package Dimensions ............................................................... 33 Table 4.5. SOIC-14 PCB Land Pattern Dimensions ................................................ 34 5. ADC0 (8-Bit ADC, C8051F300/2) Table 5.1. ADC0 Electrical Characteristics .............................................................. 47 6. Voltage Reference (C8051F300/2) Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 50 7. Comparator0 Table 7.1. Comparator0 Electrical Characteristics .................................................. 55 8. CIP-51 Microcontroller Table 8.1. CIP-51 Instruction Set Summary ............................................................ 59 Table 8.2. Special Function Register (SFR) Memory Map ...................................... 66 Table 8.3. Special Function Registers ..................................................................... 66 Table 8.4. Interrupt Summary .................................................................................. 74 9. Reset Sources Table 9.1. User Code Space Address Limits ........................................................... 86 Table 9.2. Reset Electrical Characteristics .............................................................. 86 10.Flash Memory Table 10.1. Flash Electrical Characteristics ............................................................ 90 Table 10.2. Security Byte Decoding ........................................................................ 91 11.Oscillators Table 11.1. Internal Oscillator Electrical Characteristics ......................................... 99 12.Port Input/Output Table 12.1. Port I/O DC Electrical Characteristics ................................................. 110 13.SMBus Table 13.1. SMBus Clock Source Selection .......................................................... 116 Table 13.2. Minimum SDA Setup and Hold Times ................................................ 117 Table 13.3. Sources for Hardware Changes to SMB0CN ..................................... 121 Table 13.4. SMBus Status Decoding ..................................................................... 127 14.UART0 Table 14.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator .............................................. 138 Table 14.2. Timer Settings for Standard Baud Rates Using an External 25 MHz Oscillator .................................................. 138Rev. 2.9 9

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Guil*****o Lala

August 22, 2020

Those components that were in stock shipped fast and arrived promptly.

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August 14, 2020

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August 13, 2020

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August 10, 2020

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August 5, 2020

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July 29, 2020

I wanted something that would handle voltage spikes. Worked perfectly. I plan to use four more.

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July 27, 2020

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East*****anghvi

July 22, 2020

All current moves in switching devices with the proper selection of amp rating capability. I chose these to do a job that had to handle only 1/3 of it's rated capacity. So they were the perfect choice. To date they work as expected; perfectly.

Dunc*****oyer

July 17, 2020

Great price and condition, Very speedy delivery, Very pleased thank you

Yeh***** Lamb

July 4, 2020

What can I say, great value for the money. I only needed 2 but now I have some spares for future projects. They got the job done, nothing more I can say.

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