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C8051F380-GQ

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C8051F380-GQ

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Part Number C8051F380-GQ
Manufacturer Silicon Labs
Description IC MCU 8BIT 64KB FLASH 48TQFP
Datasheet C8051F380-GQ Datasheet
Package 48-TQFP
In Stock 379 piece(s)
Unit Price $ 2.5500 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 8 - Jun 13 (Choose Expedited Shipping)
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Part Number # C8051F380-GQ (Embedded - Microcontrollers) is manufactured by Silicon Labs and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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C8051F380-GQ Specifications

ManufacturerSilicon Labs
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet C8051F380-GQDatasheet
Package48-TQFP
SeriesC8051F38x
Core Processor8051
Core Size8-Bit
Speed48 MIPS
ConnectivityEBI/EMI, I2C, SPI, UART/USART, USB
PeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number of I/O40
Program Memory Size64KB (64K x 8)
Program Memory TypeFLASH
EEPROM Size-
RAM Size4.25K x 8
Voltage - Supply (Vcc/Vdd)2.7 V ~ 5.25 V
Data ConvertersA/D 32x10b
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C (TA)
Mounting Type-
Package / Case48-TQFP
Supplier Device Package48-QFP (7x7)

C8051F380-GQ Datasheet

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Page 2

Full Speed USB Flash MCU Family C8051F380/1/2/3/4/5/6/7/C Rev. 1.4 10/13 Copyright © 2013 by Silicon Laboratories C8051F380/1/2/3/4/5/6/7/C Analog Peripherals - 10-Bit ADC (C8051F380/1/2/3/C only) • Up to 500 ksps • Built-in analog multiplexer with single-ended and differential mode • VREF from external pin, internal reference, or VDD • Built-in temperature sensor • External conversion start input option - Two comparators - Internal voltage reference (C8051F380/1/2/3/C only) - Brown-out detector and POR Circuitry USB Function Controller - USB specification 2.0 compliant - Full speed (12 Mbps) or low speed (1.5 Mbps) operation - Integrated clock recovery; no external crystal required for full speed or low speed - Supports eight flexible endpoints - 1 kB USB buffer memory - Integrated transceiver; no external resistors required On-Chip Debug - On-chip debug circuitry facilitates full speed, non-intru- sive in-system debug (No emulator required) - Provides breakpoints, single stepping, inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets Voltage Supply Input: 2.7 to 5.25 V - Voltages from 2.7 to 5.25 V supported using On-Chip Voltage Regulators High Speed 8051 μC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 48 MIPS operation - Expanded interrupt handler Memory - 4352 or 2304 Bytes RAM - 64, 32, or 16 kB Flash; In-system programmable in 512-byte sectors Digital Peripherals - 40/25 Port I/O; All 5 V tolerant with high sink current - Hardware enhanced SPI™, two I2C/SMBus™, and two enhanced UART serial ports - Six general purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with five cap- ture/compare modules - External Memory Interface (EMIF) Clock Sources - Internal Oscillator: ±0.25% accuracy with clock recovery enabled. Supports all USB and UART modes - External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin modes) - Low Frequency (80 kHz) Internal Oscillator - Can switch between clock sources on-the-fly Packages - 48-pin TQFP (C8051F380/2/4/6) - 32-pin LQFP (C8051F381/3/5/7/C) - 5x5 mm 32-pin QFN (C8051F381/3/5/7/C) Temperature Range: –40 to +85 °C

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C8051F380/1/2/3/4/5/6/7/C 2 Rev. 1.4

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C8051F380/1/2/3/4/5/6/7/C Rev. 1.4 3 Table of Contents 1. System Overview ..................................................................................................... 16 2. C8051F34x Compatibility ........................................................................................ 20 2.1. Hardware Incompatibilities ................................................................................ 21 3. Pinout and Package Definitions ............................................................................. 22 4. Typical Connection Diagrams ................................................................................ 34 4.1. Power ............................................................................................................ 34 4.2. USB ............................................................................................................ 36 4.3. Voltage Reference (VREF)................................................................................ 36 5. Electrical Characteristics ........................................................................................ 37 5.1. Absolute Maximum Specifications..................................................................... 37 5.2. Electrical Characteristics ................................................................................... 38 6. 10-Bit ADC (ADC0, C8051F380/1/2/3/C only) ......................................................... 46 6.1. Output Code Formatting .................................................................................... 47 6.3. Modes of Operation ........................................................................................... 50 6.3.1. Starting a Conversion................................................................................ 50 6.3.2. Tracking Modes......................................................................................... 51 6.3.3. Settling Time Requirements...................................................................... 52 6.4. Programmable Window Detector....................................................................... 56 6.4.1. Window Detector Example........................................................................ 58 6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C only) ........................................ 59 7. Voltage Reference Options..................................................................................... 62 8. Comparator0 and Comparator1.............................................................................. 64 8.1. Comparator Multiplexers ................................................................................... 71 9. Voltage Regulators (REG0 and REG1)................................................................... 74 9.1. Voltage Regulator (REG0)................................................................................. 74 9.1.1. Regulator Mode Selection......................................................................... 74 9.1.2. VBUS Detection ........................................................................................ 74 9.2. Voltage Regulator (REG1)................................................................................. 74 10. Power Management Modes................................................................................... 76 10.1. Idle Mode......................................................................................................... 76 10.2. Stop Mode ....................................................................................................... 77 10.3. Suspend Mode ................................................................................................ 77 11. CIP-51 Microcontroller........................................................................................... 79 11.1. Instruction Set.................................................................................................. 80 11.1.1. Instruction and CPU Timing .................................................................... 80 11.2. CIP-51 Register Descriptions .......................................................................... 85 12. Prefetch Engine...................................................................................................... 88 13. Memory Organization ............................................................................................ 89 13.1. Program Memory............................................................................................. 91 13.2. Data Memory ................................................................................................... 91 13.3. General Purpose Registers ............................................................................. 92 13.4. Bit Addressable Locations ............................................................................... 92 13.5. Stack ............................................................................................................ 92

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C8051F380/1/2/3/4/5/6/7/C 4 Rev. 1.4 14. External Data Memory Interface and On-Chip XRAM......................................... 93 14.1. Accessing XRAM............................................................................................. 93 14.1.1. 16-Bit MOVX Example ............................................................................ 93 14.1.2. 8-Bit MOVX Example .............................................................................. 93 14.2. Accessing USB FIFO Space ........................................................................... 94 14.3. Configuring the External Memory Interface ..................................................... 95 14.4. Port Configuration............................................................................................ 95 14.5. Multiplexed and Non-multiplexed Selection..................................................... 98 14.5.1. Multiplexed Configuration........................................................................ 98 14.5.2. Non-multiplexed Configuration................................................................ 98 14.6. Memory Mode Selection................................................................................ 100 14.6.1. Internal XRAM Only .............................................................................. 100 14.6.2. Split Mode without Bank Select............................................................. 100 14.6.3. Split Mode with Bank Select.................................................................. 101 14.6.4. External Only......................................................................................... 101 14.7. Timing .......................................................................................................... 102 14.7.1. Non-multiplexed Mode .......................................................................... 104 14.7.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 104 14.7.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 105 14.7.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 106 14.7.2. Multiplexed Mode.................................................................................. 107 14.7.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 107 14.7.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 108 14.7.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 109 15. Special Function Registers................................................................................. 111 15.1. 13.1. SFR Paging .......................................................................................... 111 16. Interrupts .............................................................................................................. 118 16.1. MCU Interrupt Sources and Vectors.............................................................. 119 16.1.1. Interrupt Priorities.................................................................................. 119 16.1.2. Interrupt Latency ................................................................................... 119 16.2. Interrupt Register Descriptions ...................................................................... 119 16.3. INT0 and INT1 External Interrupt Sources .................................................... 127 17. Reset Sources...................................................................................................... 129 17.1. Power-On Reset ............................................................................................ 130 17.2. Power-Fail Reset / VDD Monitor ................................................................... 131 17.3. External Reset ............................................................................................... 132 17.4. Missing Clock Detector Reset ....................................................................... 132 17.5. Comparator0 Reset ....................................................................................... 132 17.6. PCA Watchdog Timer Reset ......................................................................... 133 17.7. Flash Error Reset .......................................................................................... 133 17.8. Software Reset .............................................................................................. 133 17.9. USB Reset..................................................................................................... 133 18. Flash Memory....................................................................................................... 135 18.1. Programming The Flash Memory .................................................................. 135 18.1.1. Flash Lock and Key Functions .............................................................. 135

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C8051F380/1/2/3/4/5/6/7/C Rev. 1.4 5 18.1.2. Flash Erase Procedure ......................................................................... 135 18.1.3. Flash Write Procedure .......................................................................... 136 18.2. Non-Volatile Data Storage............................................................................. 137 18.3. Security Options ............................................................................................ 137 19. Oscillators and Clock Selection ......................................................................... 142 19.1. System Clock Selection................................................................................. 143 19.2. USB Clock Selection ..................................................................................... 143 19.3. Programmable Internal High-Frequency (H-F) Oscillator .............................. 145 19.3.1. Internal Oscillator Suspend Mode......................................................... 145 19.4. Clock Multiplier .............................................................................................. 147 19.5. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 148 19.5.1. Calibrating the Internal L-F Oscillator.................................................... 148 19.6. External Oscillator Drive Circuit..................................................................... 149 19.6.1. External Crystal Mode........................................................................... 149 19.6.2. External RC Example............................................................................ 151 19.6.3. External Capacitor Example.................................................................. 151 20. Port Input/Output ................................................................................................. 153 20.1. Priority Crossbar Decoder ............................................................................. 154 20.2. Port I/O Initialization ...................................................................................... 158 20.3. General Purpose Port I/O.............................................................................. 161 21. Universal Serial Bus Controller (USB0) ............................................................. 172 21.1. Endpoint Addressing ..................................................................................... 172 21.2. USB Transceiver ........................................................................................... 173 21.3. USB Register Access .................................................................................... 175 21.4. USB Clock Configuration............................................................................... 179 21.5. FIFO Management ........................................................................................ 181 21.5.1. FIFO Split Mode.................................................................................... 181 21.5.2. FIFO Double Buffering .......................................................................... 182 21.5.1. FIFO Access ......................................................................................... 182 21.6. Function Addressing...................................................................................... 183 21.7. Function Configuration and Control............................................................... 183 21.8. Interrupts ....................................................................................................... 186 21.9. The Serial Interface Engine ........................................................................... 193 21.10. Endpoint0 .................................................................................................... 193 21.10.1. Endpoint0 SETUP Transactions ......................................................... 193 21.10.2. Endpoint0 IN Transactions.................................................................. 193 21.10.3. Endpoint0 OUT Transactions.............................................................. 194 21.11. Configuring Endpoints1-3 ............................................................................ 196 21.12. Controlling Endpoints1-3 IN......................................................................... 197 21.12.1. Endpoints1-3 IN Interrupt or Bulk Mode.............................................. 197 21.12.2. Endpoints1-3 IN Isochronous Mode.................................................... 198 21.13. Controlling Endpoints1-3 OUT..................................................................... 201 21.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode.......................................... 201 21.13.2. Endpoints1-3 OUT Isochronous Mode................................................ 201 22. SMBus0 and SMBus1 (I2C Compatible)............................................................. 205

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C8051F380/1/2/3/4/5/6/7/C 6 Rev. 1.4 22.1. Supporting Documents .................................................................................. 206 22.2. SMBus Configuration..................................................................................... 206 22.3. SMBus Operation .......................................................................................... 206 22.3.1. Transmitter Vs. Receiver....................................................................... 207 22.3.2. Arbitration.............................................................................................. 207 22.3.3. Clock Low Extension............................................................................. 207 22.3.4. SCL Low Timeout.................................................................................. 207 22.3.5. SCL High (SMBus Free) Timeout ......................................................... 208 22.4. Using the SMBus........................................................................................... 208 22.4.1. SMBus Configuration Register.............................................................. 208 22.4.2. SMBus Timing Control Register............................................................ 210 22.4.3. SMBnCN Control Register .................................................................... 214 22.4.3.1. Software ACK Generation ............................................................ 214 22.4.3.2. Hardware ACK Generation ........................................................... 214 22.4.4. Hardware Slave Address Recognition .................................................. 217 22.4.5. Data Register ........................................................................................ 221 22.5. SMBus Transfer Modes................................................................................. 223 22.5.1. Write Sequence (Master) ...................................................................... 223 22.5.2. Read Sequence (Master) ...................................................................... 224 22.5.3. Write Sequence (Slave) ........................................................................ 225 22.5.4. Read Sequence (Slave) ........................................................................ 226 22.6. SMBus Status Decoding................................................................................ 226 23. UART0................................................................................................................... 232 23.1. Enhanced Baud Rate Generation.................................................................. 233 23.2. Operational Modes ........................................................................................ 234 23.2.1. 8-Bit UART............................................................................................ 234 23.2.2. 9-Bit UART............................................................................................ 235 23.3. Multiprocessor Communications ................................................................... 236 24. UART1................................................................................................................... 240 24.1. Baud Rate Generator .................................................................................... 241 24.2. Data Format................................................................................................... 242 24.3. Configuration and Operation ......................................................................... 243 24.3.1. Data Transmission ................................................................................ 243 24.3.2. Data Reception ..................................................................................... 243 24.3.3. Multiprocessor Communications ........................................................... 244 25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 250 25.1. Signal Descriptions........................................................................................ 251 25.1.1. Master Out, Slave In (MOSI)................................................................. 251 25.1.2. Master In, Slave Out (MISO)................................................................. 251 25.1.3. Serial Clock (SCK) ................................................................................ 251 25.1.4. Slave Select (NSS) ............................................................................... 251 25.2. SPI0 Master Mode Operation ........................................................................ 251 25.3. SPI0 Slave Mode Operation .......................................................................... 253 25.4. SPI0 Interrupt Sources .................................................................................. 254 25.5. Serial Clock Phase and Polarity .................................................................... 254

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C8051F380/1/2/3/4/5/6/7/C Rev. 1.4 7 25.6. SPI Special Function Registers ..................................................................... 256 26. Timers ................................................................................................................... 263 26.1. Timer 0 and Timer 1 ...................................................................................... 266 26.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 266 26.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 267 26.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 267 26.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 268 26.2. Timer 2 .......................................................................................................... 274 26.2.1. 16-bit Timer with Auto-Reload............................................................... 274 26.2.2. 8-bit Timers with Auto-Reload............................................................... 275 26.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ..... 275 26.3. Timer 3 .......................................................................................................... 281 26.3.1. 16-bit Timer with Auto-Reload............................................................... 281 26.3.2. 8-bit Timers with Auto-Reload............................................................... 282 26.3.3. Timer 3 Capture Modes: USB Start-of-Frame or LFO Falling Edge ..... 282 26.4. Timer 4 .......................................................................................................... 288 26.4.1. 16-bit Timer with Auto-Reload............................................................... 288 26.4.2. 8-bit Timers with Auto-Reload............................................................... 289 26.5. Timer 5 .......................................................................................................... 293 26.5.1. 16-bit Timer with Auto-Reload............................................................... 293 26.5.2. 8-bit Timers with Auto-Reload............................................................... 294 27. Programmable Counter Array............................................................................. 298 27.1. PCA Counter/Timer ....................................................................................... 299 27.2. PCA0 Interrupt Sources................................................................................. 300 27.3. Capture/Compare Modules ........................................................................... 301 27.3.1. Edge-triggered Capture Mode............................................................... 302 27.3.2. Software Timer (Compare) Mode.......................................................... 303 27.3.3. High-Speed Output Mode ..................................................................... 304 27.3.4. Frequency Output Mode ....................................................................... 305 27.3.5. 8-bit Pulse Width Modulator Mode....................................................... 306 27.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 307 27.4. Watchdog Timer Mode .................................................................................. 308 27.4.1. Watchdog Timer Operation ................................................................... 308 27.4.2. Watchdog Timer Usage ........................................................................ 309 27.5. Register Descriptions for PCA0..................................................................... 311 28. C2 Interface .......................................................................................................... 316 28.1. C2 Interface Registers................................................................................... 316 28.2. C2 Pin Sharing .............................................................................................. 319 Document Change List.............................................................................................. 320 Contact Information................................................................................................... 321

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C8051F380/1/2/3/4/5/6/7/C Rev. 1.4 8 List of Figures Figure 1.1. C8051F380/2/4/6 Block Diagram .......................................................... 18 Figure 1.2. C8051F381/3/5/7/C Block Diagram ....................................................... 19 Figure 3.1. TQFP-48 Pinout Diagram (Top View) ................................................... 25 Figure 3.2. TQFP-48 Package Diagram .................................................................. 26 Figure 3.3. TQFP-48 Recommended PCB Land Pattern ........................................ 27 Figure 3.4. LQFP-32 Pinout Diagram (Top View) .................................................... 28 Figure 3.5. LQFP-32 Package Diagram .................................................................. 29 Figure 3.6. LQFP-32 Recommended PCB Land Pattern ........................................ 30 Figure 3.7. QFN-32 Pinout Diagram (Top View) ..................................................... 31 Figure 3.8. QFN-32 Package Drawing .................................................................... 32 Figure 3.9. QFN-32 Recommended PCB Land Pattern .......................................... 33 Figure 4.1. Connection Diagram with Voltage Regulator Used and No USB .......... 34 Figure 4.2. Connection Diagram with Voltage Regulator Not Used and No USB ... 34 Figure 4.3. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered) ................................................................................................... 35 Figure 4.4. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered) ................................................................................................... 35 Figure 4.5. Connection Diagram for USB Pins ........................................................ 36 Figure 4.6. Connection Diagram for Internal Voltage Reference ............................. 36 Figure 6.1. ADC0 Functional Block Diagram ........................................................... 46 Figure 6.2. Typical Temperature Sensor Transfer Function .................................... 48 Figure 6.3. Temperature Sensor Error with 1-Point Calibration .............................. 49 Figure 6.4. 10-Bit ADC Track and Conversion Example Timing ............................. 51 Figure 6.5. ADC0 Equivalent Input Circuits ............................................................. 52 Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 58 Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 58 Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 62 Figure 8.1. Comparator0 Functional Block Diagram ............................................... 64 Figure 8.2. Comparator1 Functional Block Diagram ............................................... 65 Figure 8.3. Comparator Hysteresis Plot .................................................................. 66 Figure 8.4. Comparator Input Multiplexer Block Diagram ........................................ 71 Figure 11.1. CIP-51 Block Diagram ......................................................................... 79 Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F380/1/4/5) ............. 89 Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F382/3/6/7) ............. 90 Figure 13.3. On-Chip Memory Map for 16 kB Devices (C8051F38C) ..................... 91 Figure 14.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ ... 94 Figure 14.2. Multiplexed Configuration Example ..................................................... 98 Figure 14.3. Non-multiplexed Configuration Example ............................................. 99 Figure 14.4. EMIF Operating Modes ..................................................................... 100 Figure 14.5. Non-Multiplexed 16-bit MOVX Timing ............................................... 104 Figure 14.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 105 Figure 14.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 106 Figure 14.8. Multiplexed 16-bit MOVX Timing ....................................................... 107

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C8051F380/1/2/3/4/5/6/7/C 9 Rev. 1.4 Figure 14.9. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 108 Figure 14.10. Multiplexed 8-bit MOVX with Bank Select Timing ........................... 109 Figure 17.1. Reset Sources ................................................................................... 129 Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 130 Figure 18.1. Flash Program Memory Map and Security Byte ................................ 137 Figure 19.1. Oscillator Options .............................................................................. 142 Figure 19.2. External Crystal Example .................................................................. 150 Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 153 Figure 20.2. Port I/O Cell Block Diagram .............................................................. 154 Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 155 Figure 20.4. Crossbar Priority Decoder in Example Configuration (No Pins Skipped) ............................................................................................ 156 Figure 20.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped) ............................................................................................................. 157 Figure 21.1. USB0 Block Diagram ......................................................................... 172 Figure 21.2. USB0 Register Access Scheme ........................................................ 175 Figure 21.3. USB FIFO Allocation ......................................................................... 181 Figure 22.1. SMBus Block Diagram ...................................................................... 205 Figure 22.2. Typical SMBus Configuration ............................................................ 206 Figure 22.3. SMBus Transaction ........................................................................... 207 Figure 22.4. Typical SMBus SCL Generation ........................................................ 209 Figure 22.5. Typical Master Write Sequence ........................................................ 223 Figure 22.6. Typical Master Read Sequence ........................................................ 224 Figure 22.7. Typical Slave Write Sequence .......................................................... 225 Figure 22.8. Typical Slave Read Sequence .......................................................... 226 Figure 23.1. UART0 Block Diagram ...................................................................... 232 Figure 23.2. UART0 Baud Rate Logic ................................................................... 233 Figure 23.3. UART Interconnect Diagram ............................................................. 234 Figure 23.4. 8-Bit UART Timing Diagram .............................................................. 234 Figure 23.5. 9-Bit UART Timing Diagram .............................................................. 235 Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 236 Figure 24.1. UART1 Block Diagram ...................................................................... 240 Figure 24.2. UART1 Timing Without Parity or Extra Bit ......................................... 242 Figure 24.3. UART1 Timing With Parity ................................................................ 242 Figure 24.4. UART1 Timing With Extra Bit ............................................................ 242 Figure 24.5. Typical UART Interconnect Diagram ................................................. 243 Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 244 Figure 25.1. SPI Block Diagram ............................................................................ 250 Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 252 Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ............................................................................................................. 252 Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ............................................................................................................. 253 Figure 25.5. Master Mode Data/Clock Timing ....................................................... 255 Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 255

C8051F380-GQ Reviews

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Jayl*****Ghose

May 27, 2020

Great service as always from this supplier. Already bought many times

Bar*****a Sha

May 22, 2020

On time and as described, fast delivery. Would definitely buy again. Thx.

Pris*****a Bean

May 22, 2020

Well packed, good item, capacitors both within 2.5% tolerance!

Lond*****esai

May 21, 2020

I always enjoy shopping with Heisener, never makes a mistake, most reliable, and no long waiting for deliveries.

Elia*****utta

May 14, 2020

These are great for projects with the kids or doing any type of DIY projects. The case is nice to keep everything separated. Very nice.

Elis*****eill

May 10, 2020

Comparison with other company, Heisener is my first choice for supplier.

Maggi*****onald

May 6, 2020

C8051F380-GQ arrived in great condition, very happy, Would buy again. A++ . thank you!!

Maxw*****Barber

April 28, 2020

Arrived safely. All OK. Thanks

Glor*****radley

April 26, 2020

Diodes okay. Shipped quick and received with well - packed

Ellio*****ngleton

April 12, 2020

Does what it says. As with this this type of device it is important to have it mounted so that heat can dissipate. The higher the amperage the hotter the device.

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