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CA3140E

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CA3140E

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Part Number CA3140E
Manufacturer Renesas Electronics America
Description IC OPAMP GP 4.5MHZ 8DIP
Datasheet CA3140E Datasheet
Package 8-DIP (0.300", 7.62mm)
In Stock 388 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 12 - Jul 17 (Choose Expedited Shipping)
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Part Number # CA3140E (Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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CA3140E Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps
Datasheet CA3140EDatasheet
Package8-DIP (0.300", 7.62mm)
Series-
Amplifier TypeGeneral Purpose
Number of Circuits1
Output Type-
Slew Rate9 V/µs
Gain Bandwidth Product4.5MHz
-3db Bandwidth-
Current - Input Bias10pA
Voltage - Input Offset5mV
Current - Supply4mA
Current - Output / Channel40mA
Voltage - Supply, Single/Dual (±)4 V ~ 36 V, ±2 V ~ 18 V
Operating Temperature-55°C ~ 125°C
Mounting TypeThrough Hole
Package / Case8-DIP (0.300", 7.62mm)
Supplier Device Package8-PDIP

CA3140E Datasheet

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FN957 Rev.10.00 Jul 11, 2005 CA3140, CA3140A 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output DATASHEETThe CA3140A and CA3140 are integrated circuit operational amplifiers that combine the advantages of high voltage PMOS transistors with high voltage bipolar transistors on a single monolithic chip. The CA3140A and CA3140 BiMOS operational amplifiers feature gate protected MOSFET (PMOS) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. The CA3140A and CA3140 operate at supply voltage from 4V to 36V (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute for single supply applications. The output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground. The CA3140A and CA3140 are intended for operation at supply voltages up to 36V (18V). Features • MOSFET Input Stage - Very High Input Impedance (ZIN) -1.5T (Typ) - Very Low Input Current (Il) -10pA (Typ) at 15V - Wide Common Mode Input Voltage Range (VlCR) - Can be Swung 0.5V Below Negative Supply Voltage Rail - Output Swing Complements Input Common Mode Range • Directly Replaces Industry Type 741 in Most Applications • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Ground-Referenced Single Supply Amplifiers in Automobile and Portable Instrumentation • Sample and Hold Amplifiers • Long Duration Timers/Multivibrators (seconds-Minutes-Hours) • Photocurrent Instrumentation • Peak Detectors • Active Filters • Comparators • Interface in 5V TTL Systems and Other Low Supply Voltage Systems • All Standard Operational Amplifier Applications • Function Generators • Tone Controls • Power Supplies • Portable Instruments • Intrusion Alarm Systems Pinout CA3140 (PDIP, SOIC) TOP VIEW INV. INPUT NON-INV. V- 1 2 3 4 8 7 6 5 STROBE V+ OUTPUT OFFSET NULL OFFSET NULL INPUT - + FN957 Rev.10.00 Page 1 of 24 Jul 11, 2005

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CA3140, CA3140AOrdering Information PART NUMBER (BRAND) TEMP. RANGE (°C) PACKAGE PKG. DWG. # CA3140AE -55 to 125 8 Ld PDIP E8.3 CA3140AEZ* (See Note) -55 to 125 8 Ld PDIP (Pb-free) E8.3 CA3140AM (3140A) -55 to 125 8 Ld SOIC M8.15 CA3140AM96 (3140A) -55 to 125 8 Ld SOIC Tape and Reel CA3140AMZ (3140A) (See Note) -55 to 125 8 Ld SOIC (Pb-free) M8.15 CA3140AMZ96 (3140A) (See Note) -55 to 125 8 Ld SOIC Tape and Reel (Pb-free) CA3140E -55 to 125 8 Ld PDIP E8.3 CA3140EZ* (See Note) -55 to 125 8 Ld PDIP (Pb-free) E8.3 CA3140M (3140) -55 to 125 8 Ld SOIC M8.15 CA3140M96 (3140) -55 to 125 8 Ld SOIC Tape and Reel CA3140MZ (3140) (See Note) -55 to 125 8 Ld SOIC (Pb-free) M8.15 CA3140MZ96 (3140) (See Note) -55 to 125 8 Ld SOIC Tape and Reel (Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020.FN957 Rev.10.00 Page 2 of 24 Jul 11, 2005

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CA3140, CA3140AAbsolute Maximum Ratings Thermal Information DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V++8V) To (V- -0.5V) Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . Indefinite Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package* . . . . . . . . . . . . . . . . . . 115 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder process- ing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details 2. Short circuit may be applied to ground or to either supply. Electrical Specifications VSUPPLY = 15V, TA = 25oC PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITSCA3140 CA3140A Input Offset Voltage Adjustment Resistor Typical Value of Resistor Between Terminals 4 and 5 or 4 and 1 to Adjust Max VIO 4.7 18 k Input Resistance RI 1.5 1.5 T Input Capacitance CI 4 4 pF Output Resistance RO 60 60  Equivalent Wideband Input Noise Voltage (See Figure 27) eN BW = 140kHz, RS = 1M 48 48 V Equivalent Input Noise Voltage (See Figure 35) eN RS = 100 f = 1kHz 40 40 nV/Hz f = 10kHz 12 12 nV/Hz Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA IOM- Sink 18 18 mA Gain-Bandwidth Product, (See Figures 6, 30) fT 4.5 4.5 MHz Slew Rate, (See Figure 31) SR 9 9 V/s Sink Current From Terminal 8 To Terminal 4 to Swing Output Low 220 220 A Transient Response (See Figure 28) tr RL = 2k CL = 100pF Rise Time 0.08 0.08 s OS Overshoot 10 10 % Settling Time at 10VP-P, (See Figure 5) tS RL = 2k CL = 100pF Voltage Follower To 1mV 4.5 4.5 s To 10mV 1.4 1.4 s Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL CA3140 CA3140A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage |VIO| - 5 15 - 2 5 mV Input Offset Current |IIO| - 0.5 30 - 0.5 20 pA Input Current II - 10 50 - 10 40 pAFN957 Rev.10.00 Page 3 of 24 Jul 11, 2005

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CA3140, CA3140ALarge Signal Voltage Gain (Note 3) (See Figures 6, 29) AOL 20 100 - 20 100 - kV/V 86 100 - 86 100 - dB Common Mode Rejection Ratio (See Figure 34) CMRR - 32 320 - 32 320 V/V 70 90 - 70 90 - dB Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V Power-Supply Rejection Ratio, VIO/VS (See Figure 36) PSRR - 100 150 - 100 150 V/V 76 80 - 76 80 - dB Max Output Voltage (Note 4) (See Figures 2, 8) VOM+ +12 13 - +12 13 - V VOM- -14 -14.4 - -14 -14.4 - V Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA Device Dissipation PD - 120 180 - 120 180 mW Input Offset Voltage Temperature Drift VIO/T - 8 - - 6 - V/oC NOTES: 3. At VO = 26VP-P, +12V, -14V and RL = 2k. 4. At RL = 2k. Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued) PARAMETER SYMBOL CA3140 CA3140A UNITSMIN TYP MAX MIN TYP MAX Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC PARAMETER SYMBOL TYPICAL VALUES UNITSCA3140 CA3140A Input Offset Voltage |VIO| 5 2 mV Input Offset Current |IIO| 0.1 0.1 pA Input Current II 2 2 pA Input Resistance RI 1 1 T Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V 100 100 dB Common Mode Rejection Ratio CMRR 32 32 V/V 90 90 dB Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V 2.6 2.6 V Power Supply Rejection Ratio PSRR VIO/VS 100 100 V/V 80 80 dB Maximum Output Voltage (See Figures 2, 8) VOM+ 3 3 V VOM- 0.13 0.13 V Maximum Output Current: Source IOM+ 10 10 mA Sink IOM- 1 1 mA Slew Rate (See Figure 31) SR 7 7 V/s Gain-Bandwidth Product (See Figure 30) fT 3.7 3.7 MHz Supply Current (See Figure 32) I+ 1.6 1.6 mA Device Dissipation PD 8 8 mWFN957 Rev.10.00 Page 4 of 24 Jul 11, 2005

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CA3140, CA3140ABlock Diagram Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 A Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC (Continued) PARAMETER SYMBOL TYPICAL VALUES UNITSCA3140 CA3140A A 10 A 10,000 C1 12pF 5 A 1 1 8 4 6 7 2 3 OFFSET STROBE NULL OUTPUTINPUT + - 200A 200A1.6mA 2A 2mA 2mA 4mA V+ V- BIAS CIRCUIT CURRENT SOURCES AND REGULATORFN957 Rev.10.00 Page 5 of 24 Jul 11, 2005

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CA3140, CA3140ASchematic Diagram Application Information Circuit Description As shown in the block diagram, the input terminals may be operated down to 0.5V below the negative supply rail. Two class A amplifier stages provide the voltage gain, and a unique class AB amplifier stage provides the current gain necessary to drive low-impedance loads. A biasing circuit provides control of cascoded constant current flow circuits in the first and second stages. The CA3140 includes an on chip phase compensating capacitor that is sufficient for the unity gain voltage follower configuration. Input Stage The schematic diagram consists of a differential input stage using PMOS field-effect transistors (Q9, Q10) working into a mirror pair of bipolar transistors (Q11, Q12) functioning as load resistors together with resistors R2 through R5. The mirror pair transistors also function as a differential-to-single-ended converter to provide base current drive to the second stage bipolar transistor (Q13). Offset nulling, when desired, can be effected with a 10k potentiometer connected across Terminals 1 and 5 and with its slider arm connected to Terminal 4. Cascode-connected bipolar transistors Q2, Q5 are the constant current source for the input stage. The base biasing circuit for the constant current source is described subsequently. The small diodes D3, D4, D5 provide gate oxide protection against high voltage transients, e.g., static electricity. Second Stage Most of the voltage gain in the CA3140 is provided by the second amplifier stage, consisting of bipolar transistor Q13 and its cascode connected load resistance provided by bipolar transistors Q3, Q4. On-chip phase compensation, sufficient for a majority of the applications is provided by C1. Additional Miller-Effect compensation (roll off) can be accomplished, when desired, by simply connecting a small capacitor between Terminals 1 and 8. Terminal 8 is also used to strobe the output R5 500 R4 500 Q11 Q12 R2 500 R3 500 Q10Q9 D5 D4D3 5 1 8 STROBEOFFSET NULL 3 2 NON-INVERTING INPUT INVERTING INPUT + - C1 12pF Q13 Q15 Q16 Q21 Q20 D8 Q19 Q18 Q17 R11 20 R9 50 R8 1K R12 12K R14 20K R13 5K D7 R10 1K OUTPUT D6 4 V- V+ 6 7 DYNAMIC CURRENT SINKOUTPUT STAGESECOND STAGEINPUT STAGEBIAS CIRCUIT D2 Q8 Q4 Q3 Q5 Q2 Q6 Q7 D1 Q1 R1 8K Q14 R7 30 R6 50 NOTE: All resistance values are in ohms.FN957 Rev.10.00 Page 6 of 24 Jul 11, 2005

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CA3140, CA3140Astage into quiescence. When terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output Terminal 6 swings low, i.e., approximately to Terminal 4 potential. Output Stage The CA3140 Series circuits employ a broad band output stage that can sink loads to the negative supply to complement the capability of the PMOS input stage when operating near the negative rail. Quiescent current in the emitter-follower cascade circuit (Q17, Q18) is established by transistors (Q14, Q15) whose base currents are “mirrored” to current flowing through diode D2 in the bias circuit section. When the CA3140 is operating such that output Terminal 6 is sourcing current, transistor Q18 functions as an emitter-follower to source current from the V+ bus (Terminal 7), via D7, R9, and R11. Under these conditions, the collector potential of Q13 is sufficiently high to permit the necessary flow of base current to emitter follower Q17 which, in turn, drives Q18. When the CA3140 is operating such that output Terminal 6 is sinking current to the V- bus, transistor Q16 is the current sinking element. Transistor Q16 is mirror connected to D6, R7, with current fed by way of Q21, R12, and Q20. Transistor Q20, in turn, is biased by current flow through R13, zener D8, and R14. The dynamic current sink is controlled by voltage level sensing. For purposes of explanation, it is assumed that output Terminal 6 is quiescently established at the potential midpoint between the V+ and V- supply rails. When output current sinking mode operation is required, the collector potential of transistor Q13 is driven below its quiescent level, thereby causing Q17, Q18 to decrease the output voltage at Terminal 6. Thus, the gate terminal of PMOS transistor Q21 is displaced toward the V- bus, thereby reducing the channel resistance of Q21. As a consequence, there is an incremental increase in current flow through Q20, R12, Q21, D6, R7, and the base of Q16. As a result, Q16 sinks current from Terminal 6 in direct response to the incremental change in output voltage caused by Q18. This sink current flows regardless of load; any excess current is internally supplied by the emitter-follower Q18. Short circuit protection of the output circuit is provided by Q19, which is driven into conduction by the high voltage drop developed across R11 under output short circuit conditions. Under these conditions, the collector of Q19 diverts current from Q4 so as to reduce the base current drive from Q17, thereby limiting current flow in Q18 to the short circuited load terminal. Bias Circuit Quiescent current in all stages (except the dynamic current sink) of the CA3140 is dependent upon bias current flow in R1. The function of the bias circuit is to establish and maintain constant current flow through D1, Q6, Q8 and D2. D1 is a diode connected transistor mirror connected in parallel with the base emitter junctions of Q1, Q2, and Q3. D1 may be considered as a current sampling diode that senses the emitter current of Q6 and automatically adjusts the base current of Q6 (via Q1) to maintain a constant current through Q6, Q8, D2. The base currents in Q2, Q3 are also determined by constant current flow D1. Furthermore, current in diode connected transistor Q2 establishes the currents in transistors Q14 and Q15. Typical Applications Wide dynamic range of input and output characteristics with the most desirable high input impedance characteristics is achieved in the CA3140 by the use of an unique design based upon the PMOS Bipolar process. Input common mode voltage range and output swing capabilities are complementary, allowing operation with the single supply down to 4V. The wide dynamic range of these parameters also means that this device is suitable for many single supply applications, such as, for example, where one input is driven below the potential of Terminal 4 and the phase sense of the output signal must be maintained – a most important consideration in comparator applications.FN957 Rev.10.00 Page 7 of 24 Jul 11, 2005

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CA3140, CA3140AOutput Circuit Considerations Excellent interfacing with TTL circuitry is easily achieved with a single 6.2V zener diode connected to Terminal 8 as shown in Figure 1. This connection assures that the maximum output signal swing will not go more positive than the zener voltage minus two base-to-emitter voltage drops within the CA3140. These voltages are independent of the operating supply voltage. Figure 2 shows output current sinking capabilities of the CA3140 at various supply voltages. Output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for level shifting circuitry usually associated with the 741 series of operational amplifiers. Figure 4 shows some typical configurations. Note that a series resistor, RL, is used in both cases to limit the drive available to the driven device. Moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit. Offset Voltage Nulling The input offset voltage can be nulled by connecting a 10k potentiometer between Terminals 1 and 5 and returning its wiper arm to terminal 4, see Figure 3A. This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors (R) that may be placed at either end of the potentiometer, see Figure 3B, to optimize its utilization range are given in the Electrical Specifications table. An alternate system is shown in Figure 3C. This circuit uses only one additional resistor of approximately the value shown in the table. For potentiometers, in which the resistance does not drop to 0 at either end of rotation, a value of resistance 10% lower than the values shown in the table should be used. Low Voltage Operation Operation at total supply voltages as low as 4V is possible with the CA3140. A current regulator based upon the PMOS threshold voltage maintains reasonable constant operating current and hence consistent performance down to these lower voltages. The low voltage limitation occurs when the upper extreme of the input common mode voltage range extends down to the voltage at Terminal 4. This limit is reached at a total supply voltage just below 4V. The output voltage range also begins to extend down to the negative supply rail, but is slightly higher than that of the input. Figure 8 shows these characteristics and shows that with 2V dual supplies, the lower extreme of the input common mode voltage range is below ground potential. 3 2 4 CA3140 8 6 7 V+ 5V TO 36V 6.2V 5V LOGIC SUPPLY 5V TYPICAL TTL GATE FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT SWING TO TTL LEVELS 1 0.01 0.1 LOAD (SINKING) CURRENT (mA) 1.0 10 10 100 1000 O U T P U T S TA G E T R A N S IS T O R ( Q 15 , Q 1 6) S A T U R A T IO N V O LT A G E ( m V ) SUPPLY VOLTAGE (V-) = 0V TA = 25oC SUPPLY VOLTAGE (V+) = +5V +15V +30V FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15 AND Q16) vs LOAD CURRENT FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS 3 2 4 CA3140 7 6 V+ 5 1 V- 10k 3 2 4 CA3140 7 6 V+ 5 1 V- 10k R R 3 2 4 CA3140 7 6 V+ 5 1 V- 10k R FN957 Rev.10.00 Page 8 of 24 Jul 11, 2005

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CA3140, CA3140ABandwidth and Slew Rate For those cases where bandwidth reduction is desired, for example, broadband noise reduction, an external capacitor connected between Terminals 1 and 8 can reduce the open loop -3dB bandwidth. The slew rate will, however, also be proportionally reduced by using this additional capacitor. Thus, a 20% reduction in bandwidth by this technique will also reduce the slew rate by about 20%. Figure 5 shows the typical settling time required to reach 1mV or 10mV of the final value for various levels of large signal inputs for the voltage follower and inverting unity gain amplifiers. The exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of the CA3140; as shown in Figure 6. Input Circuit Considerations As mentioned previously, the amplifier inputs can be driven below the Terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry. Moreover, some current limiting resistance should be provided between the inverting input and the output when the CA3140 is FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES 3 2 4 CA3140 7 6 LOAD RL RS MT2 MT1 30V NO LOAD 120VAC 3 2 4 CA3140 7 6 V+ +HV LOAD RL FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS FIGURE 5. SETTLING TIME vs INPUT VOLTAGE SETTLING TIME (s) 0.1 IN P U T V O LT A G E ( V ) 1.0 10 SUPPLY VOLTAGE: VS = 15V TA = 25oC 1mV 10mV 10mV 1mV 1mV1mV 10mV FOLLOWER INVERTING LOAD RESISTANCE (RL) = 2k LOAD CAPACITANCE (CL) = 100pF 10 8 6 4 2 0 -2 -4 -6 -8 -10 10mV 3 2 CA3140 6 SIMULATED LOAD 4 -15V 0.1F 5.11k 0.1F 7 +15V 5k 2k100pF 5k INVERTING SETTLING POINT 200 4.99k D1 1N914 D2 1N914 2 CA3140 6 SIMULATED LOAD 4 -15V 0.1F 0.1F 7 +15V 2k100pF 0.05F 2k 3 10k FOLLOWERFN957 Rev.10.00 Page 9 of 24 Jul 11, 2005

CA3140E Reviews

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Aliz*****rnal

June 28, 2020

Very quick dispatch, arrived the next day. Item as described. Thanks!

Adel*****stillo

June 21, 2020

I am always amazed at the cost of automotive or marine costs when a rectifier is needed while these will do the exact same thing if you are a bit technically minded to wire them up.

Laur*****kins

June 20, 2020

It gives you a good quality product, with a great variety.. I will for sure order this set again when i start to run low

Trey*****lard

June 16, 2020

Good service, and great value for money I am pleased with the item of CA3140E.

Arth*****trong

June 13, 2020

Item is as described and very good postage time. Thank you.

Natha*****Kapur

June 6, 2020

Well packed in anti-static bags. Repaired my amp perfectly - thank you!

Steph*****Johns

May 27, 2020

A well designed product that fit my custom PCB's perfectly. Easy to use. Sturdy construction. Highly recommend to all PCB builders.

Layt*****wens

May 26, 2020

The specs range is wide for a selection and the customer service is great.

Kyn*****uck

May 24, 2020

Great seller, item shipped quickly and in great packaging. I will come next time .

Reag*****osales

May 17, 2020

Does what it says. As with this this type of device it is important to have it mounted so that heat can dissipate. The higher the amperage the hotter the device.

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