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CD4021BCMX

hot CD4021BCMX

CD4021BCMX

For Reference Only

Part Number CD4021BCMX
Manufacturer Fairchild/ON Semiconductor
Description IC SHIFT REGISTER 8STAGE 16SOIC
Datasheet CD4021BCMX Datasheet
Package 16-SOIC (0.154", 3.90mm Width)
In Stock 9718 piece(s)
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CD4021BCMX

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CD4021BCMX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Shift Registers
Datasheet CD4021BCMX Datasheet
Package16-SOIC (0.154", 3.90mm Width)
Series4000B
Logic TypeShift Register
Output TypePush-Pull
Number of Elements1
Number of Bits per Element8
FunctionParallel or Serial to Serial
Voltage - Supply3 V ~ 18 V
Operating Temperature-55°C ~ 125°C
Mounting TypeSurface Mount
Package / Case16-SOIC (0.154", 3.90mm Width)
Supplier Device Package16-SOIC

CD4021BCMX Datasheet

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© 2002 Fairchild Semiconductor Corporation DS005954 www.fairchildsemi.com October 1987 Revised March 2002 C D 4 0 2 1 B C 8 -S ta g e S ta tic S h ift R e g is te r CD4021BC 8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individ- ual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive. When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/ serial control is in the logical “1” state, data is jammed into each stage of the register asynchronously with the clock. All inputs are protected against static discharge with diodes to VDD and VSS. Features ■Wide supply voltage range: 3.0V to 15V ■High noise immunity: 0.45 VDD (typ.) ■Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■5V–10V–15V parametric ratings ■Symmetrical output characteristics ■Maximum input leakage 1 µ A at 15V over full tempera- ture range Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View Truth Table X = Don't care case Note 1: Level change Note 2: No change Order Number Order Code Package Description CD4021BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4021BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CL (Note 1) Serial Input Parallel/ Serial Control PI 1 PI n Q1 (Internal) Qn (Note 2) X X 1 0 0 0 0 X X 1 0 1 0 1 X X 1 1 0 1 0 X X 1 1 1 1 1  0 0 X X 0 Qn− 1  1 0 X X 1 Qn− 1  X 0 X X Q1 Qn

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www.fairchildsemi.com 2 C D 4 0 2 1 B C Logic Diagram

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3 www.fairchildsemi.com C D 4 0 2 1 B C Absolute Maximum Ratings(Note 3) (Note 4) Recommended Operating Conditions (Note 4) Note 3: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 4: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 4) Note 5: IOH and IOL are tested one output at a time. Supply Voltage (VDD) − 0.5V to + 18V Input Voltage (VIN) − 0.5V to VDD + 0.5V Storage Temperature Range (TS) − 65° C to + 150° C Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260° C Supply Voltage (VDD) 3V to 15V Input Voltage (VIN) 0 to VDD Operating Temperature Range (TA) CD4021BCN − 55° C to + 125° C Symbol Parameter Conditions − 55° C + 25° C + 125° C Units Min Max Min Typ Max Min Max IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 5 0.1 5 150 µ ACurrent VDD = 10V, VIN = VDD or VSS 10 0.2 10 300 VDD = 15V, VIN = VDD or VSS 20 0.3 20 600 VOL LOW Level VDD = 5V 0.05 0 0.05 0.05 VOutput Voltage VDD = 10V |IO| < 1 µ A 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 VOH HIGH Level VDD = 5V 4.95 4.95 5 4.95 VOutput Voltage VDD = 10V |IO|< 1 µ A 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2 1.5 1.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 6 4.0 4.0 VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3 3.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 6 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 9 11.0 IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 5) VDD = 10V, VO = 0.5V 1.6 1.3 2.2 0.90 VDD = 15V, VO = 1.5V 4.2 3.4 8 2.4 IOH HIGH Level Output VDD = 5V, VO = 4.6V − 0.64 − 0.51 − 0.88 − 0.36 mACurrent (Note 5) VDD = 10V, VO = 9.5V − 1.6 − 1.3 − 2.2 − 0.90 VDD = 15V, VO = 13.5V − 4.2 − 3.4 − 8 − 2.4 IIN Input Current VDD = 15V, VIN = 0V − 0.1 − 10 − 5 − 0.1 − 1.0 µ A VDD = 15V, VIN = 15V 0.1 10 − 5 0.1 1.0

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www.fairchildsemi.com 4 C D 4 0 2 1 B C AC Electrical Characteristics (Note 6) TA = 25° C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ Note 6: AC Parameters are guaranteed by DC correlated testing. Note 7: If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti- mated capacitive load. Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note AN-90. Symbol Parameter Conditions Min Typ Max Units tPLH, tPHL Propagation Delay Time VDD = 5V 240 350 nsVDD = 10V 100 175 VDD = 15V 70 140 tTHL, tTLH Transition Time VDD = 5V 100 200 nsVDD = 10V 50 100 VDD = 15V 40 80 fCL Maximum Clock VDD = 5V 2.5 3.5 MHzInput Frequency VDD = 10V 5 10 VDD = 15V 8 16 tW Minimum Clock VDD = 5V 100 200 nsPulse Width VDD = 10V 50 100 VDD = 15V 40 80 trCL, tfCL Clock Rise and VDD = 5V 15 µ sFall Time (Note 6) VDD = 10V 15 VDD = 15V 15 ts Minimum Set-Up Time Serial Input VDD = 5V 60 120 nstH ≥ 200 ns VDD = 10V 40 80 (Ref. to CL) VDD = 15V 30 60 Parallel Inputs VDD = 5V 25 50 nstH ≥ 200 ns VDD = 10V 15 30 (Ref. to P/S) VDD = 15V 10 20 tH Minimum Hold Time VDD = 5V 0 nsSerial In, Parallel In, ts ≥ 400 ns VDD = 10V 10 Parallel/Serial Control VDD = 15V 15 tWH Minimum P/S VDD = 5V 150 250 nsPulse Width VDD = 10V 75 125 VDD = 15V 50 100 tREM Minimum P/S Removal VDD = 5V 100 200 nsTime (Ref. to CL) VDD = 10V 50 100 VDD = 15V 40 80 CI Average Input Capacitance Any Input 5 7.5 pF CPD Power Dissipation 100 pF Capacitance (Note 8)

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5 www.fairchildsemi.com C D 4 0 2 1 B C Typical Performance Characteristics

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www.fairchildsemi.com 6 C D 4 0 2 1 B C Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A

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