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CP82C54Z

CP82C54Z

CP82C54Z

For Reference Only

Part Number CP82C54Z
Manufacturer Renesas Electronics America
Description IC OSC PROG TIMER 8MHZ 24DIP
Datasheet CP82C54Z Datasheet
Package 24-DIP (0.600", 15.24mm)
In Stock 1,974 piece(s)
Unit Price $ 10.7800 *
Lead Time To be Confirmed
Estimated Delivery Time Jun 6 - Jun 11 (Choose Expedited Shipping)
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Part Number # CP82C54Z (Clock/Timing - Programmable Timers and Oscillators) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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CP82C54Z Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Clock/Timing - Programmable Timers and Oscillators
Datasheet CP82C54ZDatasheet
Package24-DIP (0.600", 15.24mm)
Series-
TypeProgrammable Timer
Count-
Frequency8MHz
Voltage - Supply4.5 V ~ 5.5 V
Current - Supply10mA
Operating Temperature0°C ~ 70°C
Package / Case24-DIP (0.600", 15.24mm)
Supplier Device Package24-PDIP
Mounting TypeThrough Hole

CP82C54Z Datasheet

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FN2970 Rev 6.00 Sep 15, 2015 82C54 CMOS Programmable Interval Timer DATASHEETThe Intersil 82C54 is a high performance CMOS Programmable Interval Timer manufactured using an advanced 2 micron CMOS process. The 82C54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8MHz (82C54) or 10MHz (82C54-10) or 12MHz (82C54-12). The high speed and industry standard configuration of the 82C54 make it compatible with the Intersil 80C86, 80C88, and 80C286 CMOS microprocessors along with many other industry standard processors. Six programmable timer modes allow the 82C54 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. Static CMOS circuit design insures low power operation. The Intersil advanced CMOS process results in a significant reduction in power with performance equal to or greater than existing equivalent products. Features • 8MHz to 12MHz Clock Input Frequency • Compatible with NMOS 8254 - Enhanced Version of NMOS 8253 • Three Independent 16-Bit Counters • Six Programmable Counter Modes • Status Read Back Command • Binary or BCD Counting • Fully TTL Compatible • Single 5V Power Supply • Low Power - ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz • Operating Temperature Ranges - CX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C - IX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C - MD82C54 . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C • Pb-Free Plus Anneal Available (RoHS Compliant) Pinouts 82C54 (PDIP, CERDIP) TOP VIEW 82C54 (PLCC/CLCC) TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 D7 D6 D5 D4 D3 D2 D1 D0 CLK 0 OUT 0 GATE 0 GND VCC RD CS A1 A0 OUT 2 CLK 1 GATE 1 OUT 1 WR CLK 2 GATE 2 G N D N C O U T 1 G A T E 1 C L K 1 O U T 0 G A T E 0 D 7 N C V C C W R R D D 5 D 6 CS A1 A0 CLK2 NC GATE 2 OUT 2 1234 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 262728 D3 D2 D1 D0 D4 NC CLK 0FN2970 Rev 6.00 Page 1 of 23 Sep 15, 2015

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82C54Ordering Information PART NUMBERS TEMP RANGE (°C) PACKAGE PKG. DWG. #8MHz 10MHz 12MHz CP82C54 CP82C54-10 (No longer available, recommended replacement: CP82C54-10Z) CP82C54-12 (No longer available, recommended replacement: CP82C54-12Z) 0 to +70 24 Lead PDIP E24.6 CP82C54Z (See Note) CP82C54-10Z (See Note) CP82C54-12Z (See Note) 0 to +70 24 Lead PDIP** (Pb-free) E24.6 CS82C54* CS82C54-10* CS82C54-12 (No longer available, recommended replacement: CS82C54-12Z) 0 to +70 28 Lead PLCC N28.45 CS82C54Z* (See Note) CS82C54-10Z* (See Note) CS82C54-12Z* (See Note) 0 to +70 28 Lead PLCC (Pb-free) N28.45 ID82C54 - - -40 to +85 24 Lead CERDIP F24.6 IP82C54 IP82C54-10 - -40 to +85 24 Lead PDIP E24.6 IP82C54Z (See Note) IP82C54-10Z (See Note) - -40 to +85 24 Lead PDIP** (Pb-free) E24.6 IS82C54* IS82C54-10* - -40 to +85 28 Lead PLCC N28.45 IS82C54Z (See Note) IS82C54-10Z (See Note) - -40 to +85 28 Lead PLCC (Pb-free) N28.45 MD82C54/B - - -55 to +125 24 Lead CERDIP F24.6 SMD # 8406501JA - - -55 to +125 24 Lead CERDIP F24.6 SMD# 84065013A - 84065023A -55 to +125 28 Lead CLCC J28.A Contact factory for availability. *Add “96” suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.FN2970 Rev 6.00 Page 2 of 23 Sep 15, 2015

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82C54Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Operating Conditions Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range CX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C IX82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C MD82C54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Thermal Resistance (Typical) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 55 12 CLCC Package . . . . . . . . . . . . . . . . . . 65 14 PDIP Package* . . . . . . . . . . . . . . . . . . 55 N/A PLCC Package. . . . . . . . . . . . . . . . . . . 60 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C Maximum Junction Temperature Ceramic Package . . . . . . . +175°C Maximum Junction Temperature Plastic Package . . . . . . . . . +150°C Maximum Lead Temperature Package (Soldering 10s). . . . . +300°C (PLCC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2250 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications VCC = +5.0V ± 10%, Includes all Temperature Ranges SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V CX82C54, IX82C54 2.2 - V MD82C54 VIL Logical Zero Input Voltage - 0.8 V - VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA VCC -0.4 - V IOH = -100A VOL Output LOW Voltage - 0.4 V IOL = +2.5mA II Input Leakage Current -1 +1 A VIN = GND or VCC DIP Pins 9,11,14-16,18-23 IO Output Leakage Current -10 +10 A VOUT = GND or VCC DIP Pins 1-8 ICCSB Standby Power Supply Current - 10 A VCC = 5.5V, VIN = GND or VCC, Outputs Open, Counters Programmed ICCOP Operating Power Supply Current - 10 mA VCC = 5.5V, CLK0 = CLK1 = CLK2 = 8MHz, VIN = GND or VCC, Outputs Open Capacitance TA = +25oC; All Measurements Referenced to Device GND, Note 1 SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 20 pF FREQ = 1MHz COUT Output Capacitance 20 pF FREQ = 1MHz CI/O I/O Capacitance 20 pF FREQ = 1MHz NOTE: 1. Not tested, but characterized at initial design and at major process/design changes.FN2970 Rev 6.00 Page 3 of 23 Sep 15, 2015

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82C54AC Electrical SpecificationsVCC = +5.0V ± 10%, Includes all Temperature Ranges SYMBOL PARAMETER 82C54 82C54-10 82C54-12 UNITS TEST CONDITIONSMIN MAX MIN MAX MIN MAX READ CYCLE (1) TAR Address Stable Before RD 30 - 25 - 25 - ns 1 (2) TSR CS Stable Before RD 0 - 0 - 0 - ns 1 (3) TRA Address Hold Time After RD 0 - 0 - 0 - ns 1 (4) TRR RD Pulse Width 150 - 95 - 95 - ns 1 (5) TRD Data Delay from RD - 120 - 85 - 85 ns 1 (6) TAD Data Delay from Address - 210 - 185 - 185 ns 1 (7) TDF RD to Data Floating 5 85 5 65 5 65 ns 2, Note 1 (8) TRV Command Recovery Time 200 - 165 - 165 - ns WRITE CYCLE (9) TAW Address Stable Before WR 0 - 0 - 0 - ns (10) TSW CS Stable Before WR 0 - 0 - 0 - ns (11) TWA Address Hold Time After WR 0 - 0 - 0 - ns (12) TWW WR Pulse Width 95 - 95 - 95 - ns (13) TDW Data Setup Time Before WR 140 - 95 - 95 - ns (14) TWD Data Hold Time After WR 25 - 0 - 0 - ns (15) TRV Command Recovery Time 200 - 165 - 165 - ns CLOCK AND GATE (16) TCLK Clock Period 125 DC 100 DC 80 DC ns 1 (17) TPWH High Pulse Width 60 - 30 - 30 - ns 1 (18) TPWL Low Pulse Width 60 - 40 - 30 - ns 1 (19) TR Clock Rise Time - 25 - 25 - 25 ns (20) TF Clock Fall Time - 25 - 25 - 25 ns (21) TGW Gate Width High 50 - 50 - 50 - ns 1 (22) TGL Gate Width Low 50 - 50 - 50 - ns 1 (23) TGS Gate Setup Time to CLK 50 - 40 - 40 - ns 1 (24) TGH Gate Hold Time After CLK 50 - 50 - 50 - ns 1 (25) TOD Output Delay from CLK - 150 - 100 - 100 ns 1 (26) TODG Output Delay from Gate - 120 - 100 - 100 ns 1 (27) TWO OUT Delay from Mode Write - 260 - 240 - 240 ns 1 (28) TWC CLK Delay for Loading 0 55 0 55 0 55 ns 1 (29) TWG Gate Delay for Sampling -5 40 -5 40 -5 40 ns 1 (30) TCL CLK Setup for Count Latch -40 40 -40 40 -40 40 ns 1 NOTE: 1. Not tested, but characterized at initial design and at major process/design changes.FN2970 Rev 6.00 Page 4 of 23 Sep 15, 2015

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82C54Functional Diagram CONTROL WORD REGISTER READ/ WRITE LOGIC DATA/ BUS BUFFER COUNTER 2 COUNTER 1 COUNTER 0 IN T E R N A L B U S INTERNAL BUS CONTROL LOGIC CONTROL WORD REGISTER STATUS LATCH STATUS REGISTER CLK n GATE n OUT n OUT 2 GATE 2 CLK 2 OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 CLK 0 WR RD D7 - D0 A0 A1 CS OLM OLL CE CRM CRL COUNTER INTERNAL BLOCK DIAGRAM 8 Pin Description SYMBOL DIP PIN NUMBER TYPE DEFINITION D7 - D0 1 - 8 I/O DATA: Bi-directional three-state data bus lines, connected to system data bus. CLK 0 9 I CLOCK 0: Clock input of Counter 0. OUT 0 10 O OUT 0: Output of Counter 0. GATE 0 11 I GATE 0: Gate input of Counter 0. GND 12 GROUND: Power supply connection. OUT 1 13 O OUT 1: Output of Counter 1. GATE 1 14 I GATE 1: Gate input of Counter 1. CLK 1 15 I CLOCK 1: Clock input of Counter 1. GATE 2 16 I GATE 2: Gate input of Counter 2. OUT 2 17 O OUT 2: Output of Counter 2. CLK 2 18 I CLOCK 2: Clock input of Counter 2. A0, A1 19 - 20 I ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. CS 21 I CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR are ignored otherwise. RD 22 I READ: This input is low during CPU read operations. WR 23 I WRITE: This input is low during CPU write operations. VCC 24 - VCC: The +5V power supply pin. A 0.1F capacitor between pins VCC and GND is recommended for decoupling. A1 A0 SELECTS 0 0 Counter 0 0 1 Counter 1 1 0 Counter 2 1 1 Control Word RegisterFN2970 Rev 6.00 Page 5 of 23 Sep 15, 2015

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82C54Functional Description General The 82C54 is a programmable interval timer/counter designed for use with microcomputer systems. It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software. The 82C54 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 82C54 to match his requirements and programs one of the counters for the desired delay. After the desired delay, the 82C54 will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated. Some of the other computer/timer functions common to microcomputers which can be implemented with the 82C54 are: • Real time clock • Event counter • Digital one-shot • Programmable rate generator • Square wave generator • Binary rate multiplier • Complex waveform generator • Complex motor controller Data Bus Buffer This three-state, bi-directional, 8-bit buffer is used to interface the 82C54 to the system bus (see Figure 1). Read/Write Logic The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 82C54. A1 and A0 select one of the three counters or the Control Word Register to be read from/written into. A “low” on the RD input tells the 82C54 that the CPU is reading one of the counters. A “low” on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 82C54 has been selected by holding CS low. Control Word Register The Control Word Register (Figure 2) is selected by the Read/Write Logic when A1, A0 = 11. If the CPU then does a write operation to the 82C54, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the Counter operation. The Control Word Register can only be written to; status information is available with the Read-Back Command. Counter 0, Counter 1, Counter 2 These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a signal counter is shown in Figure 3. The counters are fully independent. Each Counter may operate in a different Mode. The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents determine how the Counter operates. The status register, shown in the figure, when latched, contains the current contents of the Control Word Register and status of CONTROL WORD REGISTER COUNTER 2 COUNTER 1 COUNTER 0 IN T E R N A L B U S OUT 2 GATE 2 CLK 2 OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 CLK 0 WR RD D7 - D0 A0 A1 CS FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC FUNCTIONS 8 DATA/ BUS BUFFER READ/ WRITE LOGIC READ/ WRITE LOGIC DATA/ BUS BUFFER IN T E R N A L B U S OUT 2 GATE 2 CLK 2 OUT 1 GATE 1 CLK 1 OUT 0 GATE 0 CLK 0 WR RD D7 - D0 A0 A1 CS FIGURE 2. CONTROL WORD REGISTER AND COUNTER FUNCTIONS 8 CONTROL WORD REGISTER COUNTER 2 COUNTER 1 COUNTER 0 FN2970 Rev 6.00 Page 6 of 23 Sep 15, 2015

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82C54the output and null count flag. (See detailed explanation of the Read-Back command.) The actual counter is labeled CE (for Counting Element). It is a 16-bit presettable synchronous down counter. OLM and OLL are two 8-bit latches. OL stands for “Output Latch”; the subscripts M and L for “Most significant byte” and “Least significant byte”, respectively. Both are normally referred to as one unit and called just OL. These latches normally “follow” the CE, but if a suitable Counter Latch Command is sent to the 82C54, the latches “latch” the present count until read by the CPU and then return to “following” the CE. One latch at a time is enabled by the counter’s Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read. Similarly, there are two 8-bit registers called CRM and CRL (for “Count Register”). Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero. Note that the CE cannot be written into; whenever a count is written, it is written into the CR. The Control Logic is also shown in the diagram. CLK n, GATE n, and OUT n are all connected to the outside world through the Control Logic. 82C54 System Interface The 82C54 is treated by the system software as an array of peripheral I/O ports; three are counters and the fourth is a control register for MODE programming. Basically, the select inputs A0, A1 connect to the A0, A1 address bus signals of the CPU. The CS can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder. Operational Description General After power-up, the state of the 82C54 is undefined. The Mode, count value, and output of all Counters are undefined. How each Counter operates is determined when it is programmed. Each Counter must be programmed before it can be used. Unused counters need not be programmed. Programming the 82C54 Counters are programmed by writing a Control Word and then an initial count. All Control Words are written into the Control Word Register, which is selected when A1, A0 = 11. The Control Word specifies which Counter is being programmed. By contrast, initial counts are written into the Counters, not the Control Word Register. The A1, A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used. Write Operations The programming procedure for the 82C54 is very flexible. Only two conventions need to be remembered: 1. For Each Counter, the Control Word must be written before the initial count is written. 2. The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). INTERNAL BUS CONTROL LOGIC CONTROL WORD REGISTER STATUS LATCH STATUS REGISTER CLK n GATE n OUT n OLM OLL CE CRM CRL FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM ADDRESS BUS (16) CONTROL BUS DATA BUS (8) I/OR I/OW WRRDCSA0A1 A1 A0 8 COUNTER 0 OUTGATE CLK COUNTER 1 COUNTER 2 OUTGATE CLK OUTGATE CLK D0 - D7 82C54 FIGURE 4. COUNTER INTERNAL BLOCK DIAGRAMFN2970 Rev 6.00 Page 7 of 23 Sep 15, 2015

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82C54Since the Control Word Register and the three Counters have separate addresses (selected by the A1, A0 inputs), and each Control Word specifies the Counter it applies to (SC0, SC1 bits), no special instruction sequence is required. Any programming sequence that follows the conventions above is acceptable. CONTROL WORD FORMAT A1, A0 = 11; CS = 0; RD = 1; WR = 0 D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 RW1 RW0 M2 M1 M0 BCD SC - SELECT COUNTER SC1 SC0 0 0 Select Counter 0 0 1 Select Counter 1 1 0 Select Counter 2 1 1 Read-Back Command (See Read Operations) RW - READ/WRITE RW1 RW0 0 0 Counter Latch Command (See Read Operations) 0 1 Read/Write least significant byte only. 1 0 Read/Write most significant byte only. 1 1 Read/Write least significant byte first, then most significant byte. M - MODE M2 M1 M0 0 0 0 Mode 0 0 0 1 Mode 1 X 1 0 Mode 2 X 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 BCD - BINARY CODED DECIMAL 0 Binary Counter 16-bit 1 Binary Coded Decimal (BCD) Counter (4 Decades) NOTE: Don’t Care bits (X) should be 0 to insure compatibility with future products. POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 0 1 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0 Control Word - Counter 1 1 1 LSB of Count - Counter 1 0 1 MSB of Count - Counter 1 0 1 Control Word - Counter 2 1 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 2 1 0 POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 0 1 1 Control Word - Counter 1 1 1 Control Word - Counter 2 1 1 LSB of Count - Counter 2 1 0 LSB of Count - Counter 1 0 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0 MSB of Count - Counter 1 0 1 MSB of Count - Counter 2 1 0 POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 2 1 1 Control Word - Counter 1 1 1 Control Word - Counter 0 1 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 2 1 0 LSB of Count - Counter 1 0 1 MSB of Count - Counter 1 0 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 0 0 0FN2970 Rev 6.00 Page 8 of 23 Sep 15, 2015

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82C54A new initial count may be written to a Counter at any time without affecting the Counter’s programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format. If a Counter is programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count. READ OPERATIONS It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 82C54. There are three possible methods for reading the Counters. The first is through the Read-Back command, which is explained later. The second is a simple read operation of the Counter, which is selected with the A1, A0 inputs. The only requirement is that the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in process of changing when it is read, giving an undefined result. COUNTER LATCH COMMAND The other method for reading the Counters involves a special software command called the “Counter Latch Command”. Like a Control Word, this command is written to the Control Word Register, which is selected when A1, A0 = 11. Also, like a Control Word, the SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word. . The selected Counter’s output latch (OL) latches the count when the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed). The count is then unlatched automatically and the OL returns to “following” the counting element (CE). This allows reading the contents of the Counters “on the fly” without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counter’s OL holds its count until read. Counter Latch Commands do not affect the programmed Mode of the Counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued. With either method, the count must be read according to the programmed format; specifically, if the Counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other; read or write or programming operations of other Counters may be inserted between them. Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved; for example, if the Counter is programmed for two byte counts, the following sequence is valid. 1. Read least significant byte. 2. Write new least significant byte. 3. Read most significant byte. 4. Write new most significant byte. If a counter is programmed to read or write two-byte counts, the following precaution applies: A program MUST NOT transfer control between reading the first and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read. READ-BACK COMMAND The read-back command allows the user to check the count value, programmed Mode, and current state of the OUT pin and Null Count flag of the selected counter(s). The command is written into the Control Word Register and has the format shown in Figure 5. The command applies to the POSSIBLE PROGRAMMING SEQUENCE A1 A0 Control Word - Counter 1 1 1 Control Word - Counter 0 1 1 LSB of Count - Counter 1 0 1 Control Word - Counter 2 1 1 LSB of Count - Counter 0 0 0 MSB of Count - Counter 1 0 1 LSB of Count - Counter 2 1 0 MSB of Count - Counter 0 0 0 MSB of Count - Counter 2 1 0 NOTE: In all four examples, all counters are programmed to Read/Write two-byte counts. These are only four of many programming sequences. A1, A0 = 11; CS = 0; RD = 1; WR = 0 D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 0 0 X X X X SC1, SC0 - specify counter to be latched SC1 SC0 COUNTER 0 0 0 0 1 1 1 0 2 1 1 Read-Back Command D5, D4 - 00 designates Counter Latch Command, X - Don’t Care. NOTE: Don’t Care bits (X) should be 0 to insure compatibility with future products.FN2970 Rev 6.00 Page 9 of 23 Sep 15, 2015

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DIN-048RPC-DPS-SH DIN-048RPC-DPS-SH 3M, CONN DIN PLUG 48POS VERT GOLD, -, - View
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CP82C54Z

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

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