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CP82C55A-5Z

hot CP82C55A-5Z

CP82C55A-5Z

For Reference Only

Part Number CP82C55A-5Z
Manufacturer Intersil
Description IC I/O EXPANDER 24B 40DIP
Datasheet CP82C55A-5Z Datasheet
Package 40-DIP (0.600", 15.24mm)
In Stock 5962 piece(s)
Unit Price $ 6.57 *
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CP82C55A-5Z

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CP82C55A-5Z Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - Interface - I/O Expanders
Datasheet CP82C55A-5Z Datasheet
Package40-DIP (0.600", 15.24mm)
Series-
Number of I/O24
InterfaceParallel
Interrupt OutputNo
Output TypeOpen Drain
Current - Output Source/Sink2.5mA
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°C
Mounting TypeThrough Hole
Package / Case40-DIP (0.600", 15.24mm)
Supplier Device Package40-DIP

CP82C55A-5Z Datasheet

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FN2969 Rev 11.00 Dec 8, 2015 82C55A CMOS Programmable Peripheral Interface DATASHEETThe Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The Intersil advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power. Features • Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info) • Pin Compatible with NMOS 8255A • 24 Programmable I/O Pins • Fully TTL Compatible • High Speed, No “Wait State” Operation with 5MHz and 8MHz 80C86 and 80C88 • Direct Bit Set/Reset Capability • Enhanced Control Word Read Capability • L7 Process • 2.5mA Drive Capability on All I/O Ports • Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10A Ordering Information PART NUMBERS TEMP. RANGE (°C) PACKAGE PKG. DWG. #5MHz PART MARKING 8MHz PART MARKING CP82C55A-5 (No longer available, recommended replacement: CP82C55A-5Z) CP82C55A-5 CP82C55A CP82C55A 0 to +70 40 Ld PDIP E40.6 CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) CP82C55AZ 0 to +70 40 Ld PDIP (Pb-free) IP82C55A IP82C55A -40 to +85 40 Ld PDIP IP82C55AZ (Note) IP82C55AZ -40 to +85 40 Ld PDIP (Pb-free) CS82C55A-5* (No longer available, recommended replacement: CS82C55A-5Z) CS82C55A-5 CS82C55A* CS82C55A* 0 to +70 44 Ld PLCC N44.65 CS82C55A-5Z* (Note) CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ 0 to +70 44 Ld PLCC (Pb-free) IS82C55A-5* IS82C55A-5 IS82C55A* IS82C55A* -40 to +85 44 Ld PLCC IS82C55A-5Z* (Note) IS82C55A-5Z IS82C55AZ* (Note) IS82C55AZ -40 to +85 44 Ld PLCC (Pb-free) CQ82C55AZ (Note) CQ82C55AZ 0 to +70 44 Ld MQFP (Pb-free) Q44.10x10 IQ82C55AZ* (Note) IQ82C55AZ -40 to +85 44 Ld MQFP (Pb-free) ID82C55A ID82C55A -40 to +85 40 Ld CERDIP F40.6 MD82C55A/B MD82C55A/B -55 to +125 8406602QA 8406602QA SMD# 8406602XA 8406602XA SMD# 44 Ld CLCC J44.A *Add “96” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb- free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.FN2969 Rev 11.00 Page 1 of 30 Dec 8, 2015

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82C55APinouts 82C55A (PDIP, CERDIP) TOP VIEW 82C55A (CLCC) TOP VIEW 82C55A (PLCC) TOP VIEW 82C55A (MQFP) TOP VIEW PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 406 5 3 2 1 44 43 42 414 9 10 11 8 7 12 13 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 GND NC A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 P C 3 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 V C C N C NC RESET D0 D1 D2 D3 D4 D5 D6 D7 NC C S R D P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 W R CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 P C 3 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 N C NC RESET D0 D1 D2 D3 D4 D5 D6 D7 VCC R D P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 W R N C P C 2 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 2827 123456 262524232221201918 7 8 9 10 11 12 13 14 15 16 17 PC6 PC7 A0 A1 GND CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PC5 PC4 PC0 PC1 PC2 28 27 26 25 24 23 2221201918 PB7 VCC D7 D6 D5 D4 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 N C P A 4 P A 5 P A 6 P A 7 W R RESET D0 D1 D2 D3 R D P A 0 P A 1 P A 2 P A 3 N C P B 3 P B 4 P B 5 P B 6 N C N C P C 3 P B 0 P B 1 P B 2 FN2969 Rev 11.00 Page 2 of 30 Dec 8, 2015

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82C55AFunctional Diagram Pin Description SYMBOL TYPE DESCRIPTION VCC VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for decoupling. GND GROUND D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus Hold” circuitry turned on. CS I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. RD I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WR I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. A0-A1 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PA0-PA7 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port. PB0-PB7 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port. PC0-PC7 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port. GROUP A PORT A (8) GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4) GROUP B PORT B (8) GROUP B CONTROL GROUP A CONTROL DATA BUS BUFFER READ WRITE CONTROL LOGIC RD WR A1 A0 RESET CS D7-D0 POWER SUPPLIES +5V GND BIDIRECTIONAL DATA BUS I/O PA7-PA0 I/O PC7-PC4 I/O PC3-PC0 I/O PB7-PB0 8-BIT INTERNAL DATA BUSFN2969 Rev 11.00 Page 3 of 30 Dec 8, 2015

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82C55AFunctional Description Data Bus Buffer This three-state bidirectional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A “low” on this input pin enables the communication between the 82C55A and the CPU. (RD) Read. A “low” on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the 82C55A. (WR) Write. A “low” on this input pin enables the CPU to write data or control words into the 82C55A. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). (RESET) Reset. A “high” on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. “Bus hold” devices internal to the 82C55A will hold the I/O port inputs to a logic “1” state with a maximum hold current of 400A. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the 82C55A. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) The control word register can be both written and read as shown in the “Basic Operation” table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic “1”, as this implies control word mode information. Ports A, B, and C The 82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the 82C55A. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both “pull-up” and “pull-down” bus-hold devices are present on Port A. See Figure 2A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. See Figure 2B. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into 82C55A BASIC OPERATION A1 A0 RD WR CS INPUT OPERATION (READ) 0 0 0 1 0 Port A Data Bus 0 1 0 1 0 Port B Data Bus 1 0 0 1 0 Port C Data Bus 1 1 0 1 0 Control Word Data Bus OUTPUT OPERATION (WRITE) 0 0 1 0 0 Data Bus Port A 0 1 1 0 0 Data Bus Port B 1 0 1 0 0 Data Bus Port C 1 1 1 0 0 Data Bus Control DISABLE FUNCTION X X X X 1 Data Bus Three-State X X 1 1 0 Data Bus Three-State FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS GROUP A PORT A (8) GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4) GROUP B PORT B (8) GROUP B CONTROL GROUP A CONTROL DATA READ WRITE CONTROL LOGIC RD WR A1 A0 RESET CS D7-D0 POWER SUPPLIES +5V GND BIDIRECTIONAL DATA BUS I/O PA7- I/O PC7- I/O PC3- I/O PB7- BUFFER BUS PB0 PC0 PC4 PA0 8-BIT INTERNAL DATA BUSFN2969 Rev 11.00 Page 4 of 30 Dec 8, 2015

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82C55Atwo 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B. See Figure 2B. Operational Description Mode Selection There are three basic modes of operation than can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bidirectional Bus When the reset input goes “high”, all ports will be set to the input mode with all 24 port lines held at a logic “one” level by internal bus hold devices. After the reset is removed, the 82C55A can remain in the input mode with no additional initialization required. This eliminates the need to pull-up or pull-down resistors in all-CMOS designs. The control word register will contain 9Bh. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine. Any port programmed as an output port is initialized to all zeros when the control word is written. FIGURE 2A. PORT A BUS-HOLD CONFIGURATION FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION FIGURE 2. BUS-HOLD CONFIGURATION MASTER RESET OR MODE CHANGE INTERNAL DATA IN INTERNAL DATA OUT (LATCHED) EXTERNAL PORT A PIN OUTPUT MODE INPUT MODE RESET OR MODE CHANGE INTERNAL DATA IN INTERNAL DATA OUT (LATCHED) EXTERNAL PORT B, C OUTPUT MODE PIN P VCC FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE DATA BUS 8 I/O B PB7-PB0 4 I/O PC3-PC0 4 I/O C PC7-PC4 8 I/O A PA7-PA0 CONTROL BUS ADDRESS BUS RD, WR 82C55A D7-D0 A0-A1 CS MODE 0 8 I/O B PB7-PB0 CONTROL C 8 I/O A PA7-PA0 MODE 1 OR I/O CONTROL OR I/O 8 I/O B PB7-PB0 C BI- A PA7-PA0 MODE 2 CONTROL DIRECTIONAL FIGURE 4. MODE DEFINITION FORMAT D7 D6 D5 D4 D3 D2 D1 D0 PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1 GROUP B PORT C (UPPER) 1 = INPUT 0 = OUTPUT PORT A 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 GROUP A 1X = MODE 2 MODE SET FLAG 1 = ACTIVE CONTROL WORDFN2969 Rev 11.00 Page 5 of 30 Dec 8, 2015

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82C55AThe modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be “tailored” to almost any I/O structure. For instance: Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. The mode definitions and possible mode combinations may seem confusing at first, but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into account things such as efficient PC board layout, control signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Single Bit Set/Reset Feature (Figure 5) Any of the eight bits of Port C can be Set or Reset using a single Output instruction. This feature reduces software requirements in control-based applications. When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were output ports. Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure. INTE Flip-Flop Definition (BIT-SET)-INTE is SET - Interrupt Enable (BIT-RESET)-INTE is Reset - Interrupt Disable NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No handshaking is required, data is simply written to or read from a specific port. Mode 0 Basic Functional Definitions: • Two 8-bit ports and two 4-bit ports • Any Port can be input or output • Outputs are latched • Inputs are not latched • 16 different Input/Output configurations possible FIGURE 5. BIT SET/RESET FORMAT D7 D6 D5 D4 D3 D2 D1 D0 BIT SET/RESET 1 = SET 0 = RESET BIT SELECT 0 BIT SET/RESET FLAG CONTROL WORD DON’T CARE XXX 0 = ACTIVE 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 B0 B1 B2 MODE 0 PORT DEFINITION A B GROUP A # GROUP B D4 D3 D1 D0 PORT A PORT C (Upper) PORT B PORT C (Lower) 0 0 0 0 Output Output 0 Output Output 0 0 0 1 Output Output 1 Output Input 0 0 1 0 Output Output 2 Input Output 0 0 1 1 Output Output 3 Input Input 0 1 0 0 Output Input 4 Output Output 0 1 0 1 Output Input 5 Output Input 0 1 1 0 Output Input 6 Input Output 0 1 1 1 Output Input 7 Input Input 1 0 0 0 Input Output 8 Output Output 1 0 0 1 Input Output 9 Output Input 1 0 1 0 Input Output 10 Input Output 1 0 1 1 Input Output 11 Input Input 1 1 0 0 Input Input 12 Output Output 1 1 0 1 Input Input 13 Output Input 1 1 1 0 Input Input 14 Input Output 1 1 1 1 Input Input 15 Input InputFN2969 Rev 11.00 Page 6 of 30 Dec 8, 2015

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82C55AMode 0 (Basic Input) Mode 0 (Basic Output) Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 CONTROL WORD #1 CONTROL WORD #3 tRA tHR tRR tIR tAR tRD tDF RD INPUT CS, A1, A0 D7-D0 tAW tWA tWB tWW tWD tDW WR D7-D0 CS, A1, A0 OUTPUT 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C FN2969 Rev 11.00 Page 7 of 30 Dec 8, 2015

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82C55ACONTROL WORD #4 CONTROL WORD #8 CONTROL WORD #5 CONTROL WORD #9 CONTROL WORD #6 CONTROL WORD #10 CONTROL WORD #7 CONTROL WORD #11 Mode 0 Configurations (Continued) 1 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 0 D4 1 D3 0 D2 1 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C FN2969 Rev 11.00 Page 8 of 30 Dec 8, 2015

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82C55AOperating Modes Mode 1 - (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “hand shaking” signals. In mode 1, port A and port B use the lines on port C to generate or accept these “hand shaking” signals. Mode 1 Basic Function Definitions: • Two Groups (Group A and Group B) • Each group contains one 8-bit port and one 4-bit control/data port • The 8-bit data port can be either input or output. Both inputs and outputs are latched. • The 4-bit port is used for control and status of the 8-bit port. Input Control Signal Definition (Figures 6 and 7) STB (Strobe Input) A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch: in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. CONTROL WORD #12 CONTROL WORD #14 CONTROL WORD #13 CONTROL WORD #15 Mode 0 Configurations (Continued) 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 1 D0 8 PA7 - PA0 4 PC7 - PC4 4 PC3 - PC0 8 PB7 - PB0 D7 - D0 82C55A A B C FIGURE 6. MODE 1 INPUT 1 D7 0 D6 1 D5 1 D4 1/0 D3 D2 D1 D0 CONTROL WORD MODE 1 (PORT A) PC4 8 IBFAPC5 INTE A PA7-PA0 STBA INTRAPC3 PC6, PC7 I/O 2RD PC6, PC7 1 = INPUT 0 = OUTPUT 1 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL WORD MODE 1 (PORT B) PC2 8 IBFBPC1 INTE B PB7-PB0 STBB INTRBPC0 RD 1 1FN2969 Rev 11.00 Page 9 of 30 Dec 8, 2015

CP82C55A-5Z Reviews

Average User Rating
5 / 5 (101)
★ ★ ★ ★ ★
5 ★
91
4 ★
10
3 ★
0
2 ★
0
1 ★
0

Chr*****Das

January 12, 2020

Not messy and easy to handle. I've used these professionally and for my self, and they never failed me.

Jayl*****aynes

December 18, 2019

These did exactly what I needed them to do. Electricity only flows in one direction. Perfect.

Dahl*****antana

December 14, 2019

These are high quality connectors. They work as you would expect them to. There is not much else you can say about them.

Mar*****Agate

November 27, 2019

The best choice, clear and easy to make an order. Gives me full control.

Josu*****dhwa

October 28, 2019

To be honest, you're beating your competitor on delivery - sometimes I request 2nd day and you still get it here overnight. Thanks!

Sum***** Bala

August 1, 2019

These little guys worked perfect for my wiring project. Reliable, good quality.

Magn*****ilson

July 24, 2019

I wanted something that would handle voltage spikes. Worked perfectly. I plan to use four more.

Treas*****alters

July 8, 2019

This product is very easy to replace and solved my problem.

Dari*****oreno

March 30, 2019

Excellent shopping cart process, various of products for selection and order fulfillment a good service quality. I rely on them heavily.

Javon*****reras

January 29, 2019

Fantastic Quality Control and Great Selection. Heisener Electronics has became to my No.1 Supplier for many years.

CP82C55A-5Z Guarantees

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We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

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