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CS42516-CQZ

hotCS42516-CQZ

CS42516-CQZ

For Reference Only

Part Number CS42516-CQZ
Manufacturer Cirrus Logic Inc.
Description IC CODEC S/PDIF RCVR 64LQFP
Datasheet CS42516-CQZDatasheet
Package 64-LQFP
In Stock 14254 piece(s)
Unit Price $ 8.23 *
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CS42516-CQZ

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CS42516-CQZSpecifications

ManufacturerCirrus Logic Inc.
CategoryIntegrated Circuits (ICs) - Interface - CODECs
Datasheet CS42516-CQZDatasheet
Package64-LQFP
Series-
TypeGeneral Purpose
Data InterfaceSerial
Resolution (Bits)24 b
Number of ADCs / DACs2 / 6
Sigma DeltaYes
Dynamic Range, ADCs / DACs (db) Typ114 / 110
Voltage - Supply, Analog4.75 V ~ 5.25 V
Voltage - Supply, Digital3.13 V ~ 5.25 V
Operating Temperature-10°C ~ 70°C
Mounting TypeSurface Mount
Package / Case64-LQFP
Supplier Device Package64-LQFP (10x10)

CS42516-CQZDatasheet

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CS42516110 dB, 192-kHz 6-Ch CODEC with S/PDIF ReceiverFeatures  Six 24-bit D/A, two 24-bit A/D Converters  110 dB DAC / 114 dB ADC Dynamic Range  -100 dB THD+N  System Sampling Rates up to 192 kHz  S/PDIF Receiver Compatible with EIAJ CP1201 and IEC-60958  Recovered S/PDIF Clock or System Clock Selection  8:2 S/PDIF Input MUX  ADC High-Pass Filter for DC Offset Calibration  Expandable ADC Channels and One-Line Mode Support  Digital Output Volume Control with Soft Ramp  Digital ±15 dB Input Gain Adjust for ADC  Differential Analog Architecture  Supports Logic Levels between 1.8 V and 5 V General Description The CS42516 provides two analog-to-digital and six digital-to-analog delta-sigma converters, as well as an integrated S/PDIF receiver. The CS42516 integrated S/PDIF receiver supports up to eight inputs, clock recovery circuitry and format auto- detection. The internal stereo ADC is capable of inde- pendent channel gain control for single-ended or differential analog inputs. All six channels of DAC pro- vide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute con- trols or ADC overflow indicators. The CS42516 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and digital speakers. The CS42516 is available in a 64-pin LQFP package in Commercial (-10° to +70° C) grades. The CDB42518 Customer Demonstration board is also available for de- vice evaluation. Refer to “Ordering Information” on page 90. RST RXP0 RXP1/GPO1 AD0/CS SCL/CCLK SDA/CDOUT AD1/CDIN VLC AOUTA1+ AOUTA1- AOUTB1+ AOUTA3+ AOUTA3- AOUTA2- AOUTB2- AOUTA2+ AOUTB2+ AOUTB1- AOUTB3+ AOUTB3- AINL+ AINL- AINR+ AINR- FILT+ REFGND VQ Ref ADC#1 ADC#2 Digital Filter Digital Filter Gain & Clip Gain & Clip CX_SCLK CX_LRCK CX_SDIN3 CX_SDIN2 CX_SDIN1 DGND VDLPFLTTXP INT Rx Clock/Data Recovery S/PDIF Decoder Control Port DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 D ig ita l F ilt er V ol um e C on tr ol DGND RXP2/GPO2 RXP3/GPO3 RXP4/GPO4 RXP5/GPO5 RXP6/GPO6 RXP7/GPO7 VD MUTEC GPO A n al og F ilt er VARX AGND AGND VA CODEC Serial Port CX_SDOUT ADCIN1 ADCIN2 VLS SAI_LRCK SAI_SCLK SAI_SDOUT OMCK RMCK Serial Audio Interface Port ADC Serial Data Internal MCLK Mult/Div DEM C&U Bit Data Buffer Format Detector MUTECopyright  Cirrus Logic, Inc. 2014 (All Rights Reserved) http://www.cirrus.com MAR '14 DS583F2

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CS42516TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 SPECIFIED OPERATING CONDITIONS ............................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6 ANALOG INPUT CHARACTERISTICS .................................................................................................. 7 A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8 ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9 D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10 SWITCHING CHARACTERISTICS ...................................................................................................... 11 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT ........................................... 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT .......................................... 13 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15 2. PIN DESCRIPTIONS ............................................................................................................................ 16 3. TYPICAL CONNECTION DIAGRAM ............................................................................................. 19 4. APPLICATIONS ................................................................................................................................... 20 4.1 Overview ......................................................................................................................................... 20 4.2 Analog Inputs .................................................................................................................................. 20 4.2.1 Line-Level Inputs ................................................................................................................... 20 4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21 4.3 Analog Outputs ............................................................................................................................... 21 4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21 4.3.2 Interpolation Filter .................................................................................................................. 21 4.3.3 Digital Volume and Mute Control ........................................................................................... 22 4.3.4 ATAPI Specification ............................................................................................................... 22 4.4 S/PDIF Receiver ............................................................................................................................. 23 4.4.1 8:2 S/PDIF Input Multiplexer ................................................................................................. 23 4.4.2 Error Reporting and Hold Function ........................................................................................ 23 4.4.3 Channel Status Data Handling .............................................................................................. 23 4.4.4 User Data Handling ............................................................................................................... 23 4.4.5 Non-Audio Auto-Detection ..................................................................................................... 23 4.5 Clock Generation ............................................................................................................................ 24 4.5.1 PLL and Jitter Attenuation ..................................................................................................... 24 4.5.2 OMCK System Clock Mode ................................................................................................... 25 4.5.3 Master Mode ......................................................................................................................... 25 4.5.4 Slave Mode ........................................................................................................................... 25 4.6 Digital Interfaces ............................................................................................................................. 26 4.6.1 Serial Audio Interface Signals ............................................................................................... 26 4.6.2 Serial Audio Interface Formats .............................................................................................. 28 4.6.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 31 4.6.4 One-Line Mode (OLM) Configurations .................................................................................. 32 4.6.4.1 OLM Config #1 ........................................................................................................... 32 4.6.4.2 OLM Config #2 ........................................................................................................... 33 4.6.4.3 OLM Config #3 ........................................................................................................... 34 4.6.4.4 OLM Config #4 ........................................................................................................... 35 4.6.4.5 OLM Config #5 ........................................................................................................... 36 4.7 Control Port Description and Timing ............................................................................................... 37 4.7.1 SPI Mode ............................................................................................................................... 37 4.7.2 I²C Mode ................................................................................................................................ 38 4.8 Interrupts ........................................................................................................................................ 39 4.9 Reset and Power-Up ...................................................................................................................... 39 4.10 Power Supply, Grounding, and PCB Layout ................................................................................ 39 5. REGISTER QUICK REFERENCE ........................................................................................................ 412 DS583F2

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CS425166. REGISTER DESCRIPTION .................................................................................................................. 45 6.1 Memory Address Pointer (MAP) ..................................................................................................... 45 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 45 6.3 Power Control (address 02h) .......................................................................................................... 46 6.4 Functional Mode (address 03h) ...................................................................................................... 47 6.5 Interface Formats (address 04h) .................................................................................................... 49 6.6 Misc Control (address 05h) ............................................................................................................ 50 6.7 Clock Control (address 06h) ........................................................................................................... 52 6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 53 6.9 RVCR Status (address 08h) (Read Only) ....................................................................................... 54 6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only) ........................................ 55 6.11 Volume Transition Control (address 0Dh) .................................................................................... 56 6.12 Channel Mute (address 0Eh) ........................................................................................................ 58 6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ...................................................... 58 6.14 Channel Invert (address 17h) ....................................................................................................... 58 6.15 Mixing Control Pair 1 (Channels A1 & B1) (address 18h) Mixing Control Pair 2 (Channels A2 & B2) (address 19h) Mixing Control Pair 3 (Channels A3 & B3) (address 1Ah) ............................................................ 58 6.16 ADC Left Channel Gain (address 1Ch) ........................................................................................ 61 6.17 ADC Right Channel Gain (address 1Dh) ...................................................................................... 61 6.18 Receiver Mode Control (address 1Eh) ......................................................................................... 61 6.19 Receiver Mode Control 2 (address 1Fh) ...................................................................................... 63 6.20 Interrupt Status (address 20h) (Read Only) ................................................................................. 63 6.21 Interrupt Mask (address 21h) ....................................................................................................... 64 6.22 Interrupt Mode MSB (address 22h) Interrupt Mode LSB (address 23h) ............................................................................................... 65 6.23 Channel Status Data Buffer Control (address 24h) ...................................................................... 65 6.24 Receiver Channel Status (address 25h) (Read Only) .................................................................. 66 6.25 Receiver Errors (address 26h) (Read Only) ................................................................................. 67 6.26 Receiver Errors Mask (address 27h) ............................................................................................ 68 6.27 Mutec Pin Control (address 28h) .................................................................................................. 69 6.28 RXP/General-Purpose Pin Control (addresses 29h to 2Fh) ......................................................... 69 6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only) ....................................... 71 6.30 C-Bit or U-Bit Data Buffer (addresses 3Ah to 51h) (Read Only) .................................................. 71 7. PARAMETER DEFINITIONS ................................................................................................................ 72 8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 73 8.1 ADC Input Filter .............................................................................................................................. 73 8.2 DAC Output Filter ........................................................................................................................... 73 9. APPENDIX B: S/PDIF RECEIVER ....................................................................................................... 74 9.1 Error Reporting and Hold Function ................................................................................................. 74 9.2 Channel Status Data Handling ....................................................................................................... 74 9.2.1 Channel Status Data E Buffer Access ................................................................................... 75 9.2.1.1 One-Byte Mode .......................................................................................................... 75 9.2.1.2 Two-Byte Mode .......................................................................................................... 75 9.2.2 Serial Copy Management System (SCMS) ........................................................................... 76 9.3 User (U) Data E Buffer Access ....................................................................................................... 76 9.3.1 Non-Audio Auto-Detection ..................................................................................................... 76 9.3.1.1 Format Detection ....................................................................................................... 76 10. APPENDIX C: PLL FILTER ................................................................................................................ 77 10.1 External Filter Components .......................................................................................................... 77 10.1.1 General ................................................................................................................................ 77 10.1.2 Jitter Attenuation ................................................................................................................. 79 10.1.3 Capacitor Selection ............................................................................................................. 80 10.1.4 Circuit Board Layout ............................................................................................................ 81DS583F2 3

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CS4251611. APPENDIX D: EXTERNAL AES3-S/PDIF-IEC60958 RECEIVER COMPONENTS .......................... 82 11.1 AES3 Receiver External Components .......................................................................................... 82 12. APPENDIX E: ADC FILTER PLOTS .................................................................................................. 83 13. APPENDIX F: DAC FILTER PLOTS .................................................................................................. 85 14. PACKAGE DIMENSIONS ............................................................................................................... 89 THERMAL CHARACTERISTICS .......................................................................................................... 89 15. ORDERING INFORMATION .............................................................................................................. 90 16. REFERENCES .................................................................................................................................... 90 17. REVISION HISTORY ......................................................................................................................... 91 LIST OF FIGURES Figure 1. Serial Audio Port Master Mode Timing ...................................................................................... 11 Figure 2. Serial Audio Port Slave Mode Timing ........................................................................................ 11 Figure 3. Control Port Timing - I²C Format ................................................................................................ 12 Figure 4. Control Port Timing - SPI Format ............................................................................................... 13 Figure 5. Typical Connection Diagram ...................................................................................................... 19 Figure 6. Full-Scale Analog Input .............................................................................................................. 20 Figure 7. Full-Scale Output ....................................................................................................................... 21 Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, or 3) .................................................................... 22 Figure 9. CS42516 Clock Generation ....................................................................................................... 24 Figure 10. I²S Serial Audio Formats .......................................................................................................... 28 Figure 11. Left-Justified Serial Audio Formats .......................................................................................... 29 Figure 12. Right-Justified Serial Audio Formats ........................................................................................ 29 Figure 13. One Line Mode #1 Serial Audio Format ................................................................................... 30 Figure 14. One Line Mode #2 Serial Audio Format ................................................................................... 30 Figure 15. ADCIN1/ADCIN2 Serial Audio Format ..................................................................................... 31 Figure 16. OLM Configuration #1 .............................................................................................................. 32 Figure 17. OLM Configuration #2 .............................................................................................................. 33 Figure 18. OLM Configuration #3 .............................................................................................................. 34 Figure 19. OLM Configuration #4 .............................................................................................................. 35 Figure 20. OLM Configuration #5 .............................................................................................................. 36 Figure 21. Control Port Timing in SPI Mode ............................................................................................. 37 Figure 22. Control Port Timing, I²C Write .................................................................................................. 38 Figure 23. Control Port Timing, I²C Read .................................................................................................. 38 Figure 24. Recommended Analog Input Buffer ......................................................................................... 73 Figure 25. Recommended Analog Output Buffer ...................................................................................... 73 Figure 26. Channel Status Data Buffer Structure ...................................................................................... 75 Figure 27. PLL Block Diagram .................................................................................................................. 77 Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2 .............................................. 79 Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3 ...................................................... 79 Figure 30. Recommended Layout Example .............................................................................................. 81 Figure 31. Consumer Input Circuit ............................................................................................................ 82 Figure 32. S/PDIF MUX Input Circuit ........................................................................................................ 82 Figure 33. TTL/CMOS Input Circuit ........................................................................................................... 82 Figure 34. Single-Speed Mode Stopband Rejection ................................................................................. 83 Figure 35. Single-Speed Mode Transition Band ....................................................................................... 83 Figure 36. Single-Speed Mode Transition Band (Detail) ........................................................................... 83 Figure 37. Single-Speed Mode Passband Ripple ..................................................................................... 83 Figure 38. Double-Speed Mode Stopband Rejection ................................................................................ 83 Figure 39. Double-Speed Mode Transition Band ...................................................................................... 83 Figure 40. Double-Speed Mode Transition Band (Detail) ......................................................................... 84 Figure 41. Double-Speed Mode Passband Ripple .................................................................................... 84 Figure 42. Quad-Speed Mode Stopband Rejection .................................................................................. 844 DS583F2

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CS42516Figure 43. Quad-Speed Mode Transition Band ........................................................................................ 84 Figure 44. Quad-Speed Mode Transition Band (Detail) ............................................................................ 84 Figure 45. Quad-Speed Mode Passband Ripple ...................................................................................... 84 Figure 46. Single-Speed (fast) Stopband Rejection .................................................................................. 85 Figure 47. Single-Speed (fast) Transition Band ........................................................................................ 85 Figure 48. Single-Speed (fast) Transition Band (detail) ............................................................................ 85 Figure 49. Single-Speed (fast) Passband Ripple ...................................................................................... 85 Figure 50. Single-Speed (slow) Stopband Rejection ................................................................................ 85 Figure 51. Single-Speed (slow) Transition Band ....................................................................................... 85 Figure 52. Single-Speed (slow) Transition Band (detail) ........................................................................... 86 Figure 53. Single-Speed (slow) Passband Ripple ..................................................................................... 86 Figure 54. Double-Speed (fast) Stopband Rejection ................................................................................ 86 Figure 55. Double-Speed (fast) Transition Band ....................................................................................... 86 Figure 56. Double-Speed (fast) Transition Band (detail) ........................................................................... 86 Figure 57. Double-Speed (fast) Passband Ripple ..................................................................................... 86 Figure 58. Double-Speed (slow) Stopband Rejection ............................................................................... 87 Figure 59. Double-Speed (slow) Transition Band ..................................................................................... 87 Figure 60. Double-Speed (slow) Transition Band (detail) ......................................................................... 87 Figure 61. Double-Speed (slow) Passband Ripple ................................................................................... 87 Figure 62. Quad-Speed (fast) Stopband Rejection ................................................................................... 87 Figure 63. Quad-Speed (fast) Transition Band ......................................................................................... 87 Figure 64. Quad-Speed (fast) Transition Band (detail) ............................................................................. 88 Figure 65. Quad-Speed (fast) Passband Ripple ....................................................................................... 88 Figure 66. Quad-Speed (slow) Stopband Rejection .................................................................................. 88 Figure 67. Quad-Speed (slow) Transition Band ........................................................................................ 88 Figure 68. Quad-Speed (slow) Transition Band (detail) ............................................................................ 88 Figure 69. Quad-Speed (slow) Passband Ripple ...................................................................................... 88 LIST OF TABLES Table 1. Common OMCK Clock Frequencies ............................................................................................ 25 Table 2. Common PLL Output Clock Frequencies..................................................................................... 25 Table 3. Slave Mode Clock Ratios ............................................................................................................. 26 Table 4. Serial Audio Port Channel Allocations ......................................................................................... 27 Table 5. DAC De-Emphasis ....................................................................................................................... 48 Table 6. Receiver De-Emphasis ................................................................................................................ 48 Table 7. Digital Interface Formats .............................................................................................................. 49 Table 8. ADC One-Line Mode.................................................................................................................... 49 Table 9. DAC One-Line Mode.................................................................................................................... 49 Table 10. RMCK Divider Settings .............................................................................................................. 52 Table 11. OMCK Frequency Settings ........................................................................................................ 52 Table 12. Master Clock Source Select....................................................................................................... 53 Table 13. AES Format Detection ............................................................................................................... 54 Table 14. Receiver Clock Frequency Detection......................................................................................... 55 Table 15. Example Digital Volume Settings ............................................................................................... 58 Table 16. ATAPI Decode ........................................................................................................................... 60 Table 17. Example ADC Input Gain Settings ............................................................................................. 61 Table 18. TXP Output Selection................................................................................................................. 63 Table 19. Receiver Input Selection ............................................................................................................ 63 Table 20. Auxiliary Data Width Selection ................................................................................................... 66 Table 21. External PLL Component Values & Locking Modes .................................................................. 77DS583F2 5

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CS425161. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over/under voltage is limited by the input current. Parameter Symbol Min Typ Max Units DC Power Supply Analog Digital Serial Port Interface Control Port Interface VA / VARX VD VLS VLC 4.75 3.13 1.8 1.8 5.0 3.3 5.0 5.0 5.25 5.25 5.25 5.25 V V V V Ambient Operating Temperature (power applied) TA -10 - +70 C Parameters Symbol Min Max Units DC Power Supply Analog Digital Serial Port Interface Control Port Interface VA / VARX VD VLS VLC -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 V V V V Input Current (Note 1) Iin - ±10 mA Analog Input Voltage (Note 2) VIN AGND-0.7 VA+0.7 V Digital Input Voltage Serial Port Interface (Note 2) Control Port Interface S/PDIF interface VIND-S VIND-C VIND-SP -0.3 -0.3 -0.3 VLS+ 0.4 VLC+ 0.4 VARX+0.4 V V V Ambient Operating Temperature(power applied) TA TA -20 -50 +85 +95 °C °C Storage Temperature Tstg -65 +150 °C6 DS583F2

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CS42516ANALOG INPUT CHARACTERISTICS (TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Mea- surement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.; PDN_RCVR = 1; SW_CTRL[1:0] = ‘01’; OMCK = 12.288 MHz; Single-Speed Mode CX_SCLK = 3.072 MHz; Dou- ble-Speed Mode CX_SCLK = 6.144 MHz; Quad-Speed Mode CX_SCLK = 12.288 MHz.) Notes: 3. Referred to the typical full-scale voltage. 4. Measured between AIN+ and AIN- Parameter Symbol Min Typ Max Unit Single-Speed Mode (Fs=48 kHz) Dynamic Range A-weighted unweighted 108 105 114 111 - - dB dB Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB THD+N - - - -100 -91 -51 -94 - - dB dB dB Double-Speed Mode (Fs=96 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 - 114 111 108 - - - dB dB dB Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N - - - - -100 -91 -51 -97 -94 - - - dB dB dB dB Quad-Speed Mode (Fs=192 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 - 114 111 108 - - - dB dB dB Total Harmonic Distortion+ Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N - - - - -100 -91 -51 -97 -94 - - - dB dB dB dB Dynamic Performance for All Modes Interchannel Isolation - 110 - dB Interchannel Phase Deviation - 0.0001 - Degree DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Drift - +/-100 - ppm/°C Offset Error HPF_FREEZE disabled HPF_FREEZE enabled - - 0 100 - - LSB LSB Analog Input Full-scale Differential Input Voltage 1.05 VA 1.10 VA 1.16 VA Vpp Input Impedance (Differential) (Note 4) 17 - - k Common Mode Rejection Ratio CMRR - 82 - dBDS583F2 7

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CS42516A/D DIGITAL FILTER CHARACTERISTICS Notes: 5. The filter frequency response scales precisely with Fs. 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. Parameter Symbol Min Typ Max Unit Single-Speed Mode (2 to 50 kHz sample rates) Passband (-0.1 dB) (Note 5) 0 - 0.47 Fs Passband Ripple - - 0.035 dB Stopband (Note 5) 0.58 - - Fs Stopband Attenuation -95 - - dB Total Group Delay (Fs = Output Sample Rate) tgd - 12/Fs - s Group Delay Variation vs. Frequency tgd - - 0.0 s Double-Speed Mode (50 to 100 kHz sample rates) Passband (-0.1 dB) (Note 5) 0 - 0.45 Fs Passband Ripple - - 0.035 dB Stopband (Note 5) 0.68 - - Fs Stopband Attenuation -92 - - dB Total Group Delay (Fs = Output Sample Rate) tgd - 9/Fs - s Group Delay Variation vs. Frequency tgd - - 0.0 s Quad-Speed Mode (100 to 192 kHz sample rates) Passband (-0.1 dB) (Note 5) 0 - 0.24 Fs Passband Ripple - - 0.035 dB Stopband (Note 5) 0.78 - - Fs Stopband Attenuation -97 - - dB Total Group Delay (Fs = Output Sample Rate) tgd - 5/Fs - s Group Delay Variation vs. Frequency tgd - - 0.0 s High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB (Note 6) - 1 20 - - Hz Hz Phase Deviation @ 20 Hz (Note 6) - 10 - Deg Passband Ripple - - 0 dB Filter Setting Time - 105/Fs - s8 DS583F2

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CS42516ANALOG OUTPUT CHARACTERISTICS (TA = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measure- ment Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load RL = 3 k, CL = 30 pF; PDN_RCVR = 1; SW_CTRL[1:0] = ‘01’; OMCK = 12.288 MHz; Single-Speed Mode, CX_SCLK = 3.072 MHz; Double-Speed Mode, CX_SCLK = 6.144 MHz; Quad-Speed Mode, CX_SCLK = 12.288 MHz.) Notes: 7. One LSB of triangular PDF dither is added to data. 8. Performance limited by 16-bit quantization noise. Parameter Symbol Min Typ Max Unit Dynamic performance for all modes Dynamic Range (Note 7) 24-bit A-Weighted unweighted 16-bit A-Weighted (Note 8) unweighted 104 101 - - 110 107 97 94 - - - - dB dB dB dB Total Harmonic Distortion + Noise 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB (Note 8) -20 dB -60 dB THD+N - - - - - - -100 -91 -51 -94 -74 -34 -94 - - - - dB dB dB dB dB dB Idle Channel Noise/Signal-to-Noise Ratio (A-Weighted) - 110 - dB Interchannel Isolation (1 kHz) - 90 - dB Analog Output Characteristics for all modes Unloaded Full-Scale Differential Output Voltage VFS .89 VA .94 VA .99 VA Vpp Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 300 - ppm/°C Output Impedance ZOUT - 150 -  AC-Load Resistance RL 3 - - k Load Capacitance CL - - 30 pFDS583F2 9

CS42516-CQZReviews

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5 / 5 (161)
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Jon*****Nayar

January 11, 2020

DELIVERY AND COMMUNICATION EXTRA SELLER TOP 5 STARS on my list

Waylo*****shnan

December 26, 2019

Quality made product satisfied with my purchase. Thanks.

Kais*****lein

December 20, 2019

Great communication with sales. A pleasure to do business with you.

Kayla*****lasquez

November 30, 2019

Very professional sellers, they have adopted MSL packaging for different parts.

Arl*****emp

November 2, 2019

This product works great what more can I say.

Vane*****Parikh

October 21, 2019

Completely satisfied of CS42516-CQZ , I always find what I need. The site is easy to get the components .

Kings*****aniel

October 20, 2019

These are a great value at this price.

Dougl*****dgers

October 14, 2019

You're my good supplier. I appreciate Heisener Electronics on many levels.

Dar***** Bhat

October 5, 2019

Received Quickly. Excellent Communication. Capacitors Look Excellent

And***** Rama

September 22, 2019

It works fine and does what it has designed for. No regrets.

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CS42516-CQZRelated Products

hotCS42516-CQZ CS45SL2GA330JAGKA TDK Corporation, CAP CER SL SAFETY DISC RADIAL, Radial, Disc, - View
hotCS42516-CQZ WM8310CGEB/V Cirrus Logic Inc., IC REG BUCK 169VFBGA, 169-TFBGA, - View
hotCS42516-CQZ CS4412A-CNZR Cirrus Logic Inc., IC AMP AUDIO PWR 30W QUAD 48QFN, 48-QFN, - View
hotCS42516-CQZ CS8900A-CQ3Z Cirrus Logic Inc., IC LAN ETHERNET CTLR 3V 100LQFP, 100-LQFP, - View
hotCS42516-CQZ CS42418-CQZ/C1 Cirrus Logic Inc., IC CODEC 8CH 192KHZ 64LQFP, 64-LQFP, - View
hotCS42516-CQZ CS42426-CQZR/C1 Cirrus Logic Inc., IC CODEC 6CH 192KHZ 64LQFP, 64-LQFP, - View
hotCS42516-CQZ CS4207-DNZR Cirrus Logic Inc., IC CODEC AUD HDPN AMP COMM 48QFN, 48-WFQFN Exposed Pad, - View
hotCS42516-CQZ CS4244-CNZ Cirrus Logic Inc., IC AUDIO CODEC PCM/TDM 40QFN, 40-VFQFN Exposed Pad, - View
hotCS42516-CQZ CS47L35-CWZR Cirrus Logic Inc., IC LOW PRW AUDIO HUB, 101-UFBGA, WLCSP, - View
hotCS42516-CQZ CS5016-BL16Z Cirrus Logic Inc., IC ADC 16BIT SELF-CALBR 44-PLCC, 44-LCC (J-Lead), - View
hotCS42516-CQZ WM8711CLGEFL/R Cirrus Logic Inc., IC DAC 24BIT STEREO LP 24QFN, 28-VFQFN Exposed Pad, - View
hotCS42516-CQZ CS4351-DZZ Cirrus Logic Inc., IC DAC STER 112DB 192KHZ 20TSSOP, 20-TSSOP (0.173", 4.40mm Width), - View

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