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CS4350192-kHz Stereo DAC with Integrated PLLFeatures
Advanced multibit delta-sigma architecture
109-dB dynamic range
-91-dB THD+N
24-bit conversion
Supports audio sample rates up to 192 kHz
Low-latency digital filtering
Single-ended or differential analog output
architecture
Integrated PLL locks to incoming left-right
clock
– Eliminates the need for external master-
clock routing
– Reduces interference and jitter sensitivity
– No external loop filter components required
Automatic sample-rate range detection
Popguard® technology for control of clicks and
pops
Hardware popguard disable for fast startups
Supports all standard serial audio formats
including time-division multiplexed (TDM)
+1.5- to 5.0-V logic supplies for serial port
+3.3- to 5.0-V control port interface
Control Port Mode Features
SPI™ and I²C Modes
ATAPI mixing
Mute control for individual channels
Digital volume control with soft ramp
– 127.5-dB attenuation
– 0.5-dB step size
– Zero-crossing click-free transitionsPCM
Serial
Interface
Serial Audio Input
Right
Channel
Output
Left
Channel
Output
Reset
3.3 V to 5.0 V
Register/
Hardware
ConfigurationHardware or I2C/
SPI Control Data
3.3 V to 5.0 V
LRCK R
M
C
K
RMCK
Recovered MCLK
1.5 V to 5.0 V
Internal Voltage
Reference
and RegulationPhase Locked Loop
Interpolation
Filter with
Volume
Control
Interpolation
Filter with
Volume
Control
Multibit
Modulator
Multibit
Modulator
L
e
ve
l T
ra
n
sl
at
o
r
L
e
ve
l T
ra
n
sl
a
to
r
Amp
+
Filter
Amp
+
Filter
Left and
Right Mute
Controls
External
Mute
Control
DAC
DACCopyright Cirrus Logic, Inc. 2006–2017
(All Rights Reserved)
http://www.cirrus.com
FEB ‘17
DS691F4
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CS4350Description
The CS4350 is a complete stereo digital-to-analog system including PLL-based master clock derivation, digital in-
terpolation, 5th-order multibit delta-sigma digital-to-analog conversion, digital de-emphasis, volume control, channel
mixing, and analog filtering. The advantages of this architecture include ideal differential linearity, no distortion
mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jit-
ter, and a minimal set of external components.
The CS4350 supports all standard digital audio interface formats, including TDM.
The CS4350 is available in a 24-pin QFN package in Commercial grade (-40° to +85°C).
The CS4350 is available in a 24-pin TSSOP package in both Commercial (-40° to +85°C) and Automotive grades
(-40° to +105°C).
The CDB4350 Customer Demonstration board is also available for device evaluation and implementation sugges-
tions. Please refer to “Ordering Information” on page 40 for complete ordering information.
These features are ideal for cost-sensitive, two-channel audio systems, including DVD players and recorders, set-
top boxes, digital TVs, mini-component systems, mixing consoles and automotive audio systems. 2 DS691F4
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CS4350TABLE OF CONTENTS
1 PIN DESCRIPTION................................................................................................................................... 6
1.1 TSSOP Pinout ................................................................................................................................. 6
1.2 QFN Pinout ...................................................................................................................................... 6
2 CHARACTERISTICS AND SPECIFICATIONS........................................................................................ 8
2.1 Recommended Operating Conditions ............................................................................................. 8
2.2 Absolute Maximum Ratings............................................................................................................. 8
2.3 DAC Analog Characteristics - Commercial (-CZZ,-CNZ)................................................................. 9
2.4 DAC Analog Characteristics - Automotive (-DZZ) ......................................................................... 10
2.5 Combined Interpolation and On-Chip Analog Filter Response...................................................... 12
2.6 Switching Specifications - Serial Audio Interface........................................................................... 13
2.7 Switching Characteristics - Control Port - I²C Format.................................................................... 14
2.8 Switching Characteristics - Control Port - SPI Format................................................................... 15
2.9 Digital Characteristics .................................................................................................................... 16
2.10 Power and Thermal Characteristics............................................................................................. 16
3 TYPICAL CONNECTION DIAGRAM ................................................................................................... 17
4 APPLICATIONS ..................................................................................................................................... 18
4.1 Sample Rate Range and Oversampling Mode Detect................................................................... 18
4.1.1 Sample Rate Auto-Detect .................................................................................................... 18
4.2 System Clocking............................................................................................................................ 18
4.2.1 Recovered Master Clock (RMCK)........................................................................................ 18
4.3 Digital Interface Format ................................................................................................................. 19
4.3.1 Time-Division Multiplex (TDM) Mode ................................................................................... 20
4.4 De-Emphasis ................................................................................................................................. 21
4.5 Mute Control .................................................................................................................................. 21
4.6 Recommended Power-Up Sequence ............................................................................................ 21
4.6.1 Stand-Alone Mode ............................................................................................................... 21
4.6.2 Control Port Mode ................................................................................................................ 22
4.7 Popguard Transient Control .......................................................................................................... 22
4.7.1 Power-Up ............................................................................................................................. 22
4.7.2 Power-Down......................................................................................................................... 22
4.7.3 Discharge Time .................................................................................................................... 22
4.8 Analog Output and Filtering........................................................................................................... 23
4.9 Grounding and Power Supply Arrangements ................................................................................ 23
4.9.1 Capacitor Placement............................................................................................................ 23
5 STAND-ALONE OPERATION................................................................................................................ 24
5.1 Serial Port Format Selection.......................................................................................................... 24
5.2 De-Emphasis Control .................................................................................................................... 24
5.3 Popguard Transient Control .......................................................................................................... 24
6 CONTROL PORT OPERATION ............................................................................................................. 24
6.1 MAP Auto Increment ..................................................................................................................... 24
6.2 I²C Mode........................................................................................................................................ 24
6.2.1 I²C Write ............................................................................................................................... 25
6.2.2 I²C Read............................................................................................................................... 25
6.3 SPI Mode....................................................................................................................................... 26
6.3.1 SPI Write .............................................................................................................................. 26
6.3.2 SPI Read.............................................................................................................................. 26
6.4 Memory Address Pointer (MAP) ................................................................................................... 27
6.4.1 INCR (Auto Map Increment Enable) .................................................................................... 27
6.4.2 MAP (Memory Address Pointer) .......................................................................................... 27
7 REGISTER QUICK REFERENCE .......................................................................................................... 28
8 REGISTER DESCRIPTION .................................................................................................................... 29
8.1 Device and Revision ID - Register 01h.......................................................................................... 29DS691F4 3
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CS43508.2 Mode Control - Register 02h ......................................................................................................... 29
8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4 .......................................................................... 29
8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ........................................................................... 30
8.2.3 Functional Mode (FM[1:0]) Bits 1-0...................................................................................... 30
8.3 Volume Mixing and Inversion Control - Register 03h .................................................................... 30
8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ................................................... 30
8.3.2 Invert Signal Polarity (INVERT_A) Bit 6 ............................................................................... 30
8.3.3 Invert Signal Polarity (INVERT_B) Bit 5 ............................................................................... 31
8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 .................................................... 31
8.4 Mute Control - Register 04h .......................................................................................................... 32
8.4.1 Auto-Mute (AMUTE) Bit 7 .................................................................................................... 32
8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 .......................................................................... 32
8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3................................. 32
8.5 Channel A & B Volume Control - Register 05h & 06h ................................................................... 33
8.6 Ramp and Filter Control - Register 07h......................................................................................... 33
8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6 ....................................................... 33
8.6.2 Soft Volume Ramp-Up after Error (RMP_UP) Bit 5 ............................................................. 34
8.6.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4 ........................................... 34
8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2.......................................................................... 34
8.7 Misc. Control - Register 08h .......................................................................................................... 34
8.7.1 Power Down (PDN) Bit 7...................................................................................................... 34
8.7.2 Freeze Controls (FREEZE) Bit 5.......................................................................................... 35
8.7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 35
8.7.4 RMCK control (RMCK_CTRL[1:0]) Bits 3:2 ......................................................................... 35
8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1 .................................................................... 35
9 FILTER PLOTS ................................................................................................................................... 36
10 PARAMETER DEFINITIONS................................................................................................................ 37
11 PACKAGE DIMENSIONS .................................................................................................................... 38
11.1 24L TSSOP (4.4 mm body) Package Drawing ............................................................................ 38
11.2 24L QFN (4.00 mm BODY) PACKAGE DRAWING..................................................................... 39
12 THERMAL CHARACTERISTICS ......................................................................................................... 40
12.1 QFN Thermal Pad ....................................................................................................................... 40
13 ORDERING INFORMATION ............................................................................................................... 40
14 REVISION HISTORY ........................................................................................................................... 414 DS691F4
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CS4350LIST OF FIGURES
Figure 1. Equivalent Output Load .............................................................................................................. 11
Figure 2. Maximum Loading....................................................................................................................... 11
Figure 3. THD+N vs Output Amplitude for VA = 5.0 V ............................................................................... 11
Figure 4. THD+N vs Output Amplitude for VA = 3.3 V ............................................................................... 11
Figure 5. THD+N vs Output Amplitude for VA = 3.14 V ............................................................................. 11
Figure 6. Serial Port Timing, Non-TDM Mode............................................................................................ 14
Figure 7. Serial Port Timing, TDM Mode.................................................................................................... 14
Figure 8. Control Port Timing - I²C Format................................................................................................. 14
Figure 9. Control Port Timing - SPI Mode .................................................................................................. 15
Figure 10. Typical Connection Diagram..................................................................................................... 17
Figure 11. Left-Justified up to 24-Bit Data.................................................................................................. 19
Figure 12. I²S, up to 24-Bit Data ................................................................................................................ 19
Figure 13. Right-Justified Data................................................................................................................... 19
Figure 14. TDM Mode Connection Diagram .............................................................................................. 20
Figure 15. TDM Mode Timing .................................................................................................................... 20
Figure 16. De-Emphasis Curve.................................................................................................................. 21
Figure 17. Differential to Single-Ended Output Filter ................................................................................. 23
Figure 18. Passive Single-Ended Output Filter .......................................................................................... 23
Figure 19. Control Port Timing, I²C Mode .................................................................................................. 26
Figure 20. Control Port Timing, SPI Mode ................................................................................................. 27
Figure 21. De-Emphasis Curve.................................................................................................................. 30
Figure 22. ATAPI Block Diagram ............................................................................................................... 31
Figure 23. Stopband Rejection (fast), all Modes ........................................................................................ 36
Figure 24. Stopband Rejection (slow), all Modes....................................................................................... 36
Figure 25. Single-Speed (fast) Passband Detail ........................................................................................ 36
Figure 26. Single-Speed (slow) Passband Detail....................................................................................... 36
Figure 27. Double-Speed (fast) Passband Detail....................................................................................... 36
Figure 28. Double-Speed (slow) Passband Detail ..................................................................................... 36
Figure 29. Quad-Speed (fast) Passband Detail ......................................................................................... 37
Figure 30. Quad-Speed (slow) Passband Detail........................................................................................ 37
LIST OF TABLES
Table 1. Recommended Operating Conditions ............................................................................................ 8
Table 2. Absolute Maximum Ratings ........................................................................................................... 8
Table 3. DAC Analog Characteristics - Commercial (-CZZ,-CNZ) ............................................................... 9
Table 4. DAC Analog Characteristics - Automotive (-DZZ)........................................................................ 10
Table 5. Combined Interpolation and On-Chip Analog Filter Response .................................................... 12
Table 6. Switching Specifications - Serial Audio Interface ......................................................................... 13
Table 7. Switching Characteristics - Control Port - I²C Format .................................................................. 14
Table 8. Switching Characteristics - Control Port - SPI Format ................................................................. 15
Table 9. Digital Characteristics .................................................................................................................. 16
Table 10. Power and Thermal Characteristics ........................................................................................... 16
Table 11. CS4350 Auto-Detect .................................................................................................................. 18
Table 12. Digital Interface Format - Stand-Alone Mode............................................................................. 24
Table 13. Digital Interface Formats ............................................................................................................ 29
Table 14. ATAPI Decode ........................................................................................................................... 31
Table 15. Example Digital Volume Settings ............................................................................................... 33
Table 16. Thermal Characteristics ............................................................................................................. 40DS691F4 5
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CS43501 PIN DESCRIPTION
1.1 TSSOP Pinout
1.2 QFN Pinout
DIF2(AD1/CDOUT) RST
DEM(AD0/CS) AOUTB-
DIF0(SDA/CDIN) AOUTB+
DIF1(SCL/CCLK) BMUTEC
VLC VQ
VD_FILT GND
GND VA
RMCK VBIAS+
VLS AMUTEC
SCLK AOUTA+
SDIN AOUTA-
LRCK TSTO
2
3
4
5
6
7
8 17
18
19
20
21
22
23
9
10
11
12 13
14
15
16
241
D
IF
0(
S
D
A
_C
D
IN
)
D
E
M
(A
D
0/
C
S
)
D
IF
2
(A
D
1
/C
D
O
U
T
)
R
S
T
A
O
U
T
B
–
A
O
U
T
B
+
S
C
L
K
S
D
IN
LR
C
K
A
O
U
T
A
–
A
O
U
T
A
+
DIF1(SCL/CCLK)
VLC
VD_FILT
GND
RMCK
BMUTEC
VQ
GND
VBIAS+
TSTO
Thermal Pad
VLS
A
M
U
T
E
C
VA
87
6
5
4
3
2
1
9 10 11 12
192021222324
13
14
15
16
17
18
Top-Down (Through Package) View
24-Pin QFN Package
Thermal Pad6 DS691F4
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CS4350
Pi
VL
VD
GN
RM
VL
SC
SD
LR
TS
AO
AO
-
AM
BM
VB
VA
VQ
RS
Co
AD e
AD
SD
SC
St
DI
DI
DI
l
DE
Th
Th
-
n Name TSSOP
#
QFN
#
Pin Description
C 5 2 Control Interface Power (Input) - Positive power for the hardware/software control interface
_FILT 6 3 Regulator Voltage (Output) - Filter connection for internal voltage regulator
D 7, 19 4,16 Ground (Input) - Ground reference
CK 8 5 Recovered Master Clock (Output) - Outputs a master clock derived from LRCK
S 9 6 Serial Audio Interface Power (Input) - Positive power for the serial audio interface
LK 10 7 Serial Clock (Input) - Serial bit-clock for the serial audio interface
IN 11 8 Serial Audio Data Input (Input) - Input for two’s complement serial audio data
CK 12 9
Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line
TO 13 13 Test Output - These pins need to be floating and not connected to any trace or plane.
UTA+,-
UTB+,-
14, 15,
22, 23
11, 10
19, 20
Differential Analog Outputs (Output) - The full-scale differential output level is specified in “DAC Ana
log Characteristics - Commercial (-CZZ,-CNZ)” on page 9.
UTEC
UTEC
16, 21
12
18
Mute Control (Output) - Control signals for optional mute circuit.
IAS+ 17 14 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC
18 15 Analog Power (Input) - Positive power supply for the analog section
20 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage
T 24 21
Reset (Input) - When pulled low, device will power down and reset all internal registers to their default
settings.
ntrol Port Definitions
1/CDOUT 1 22 Address Bit 1/Serial Control Data Out (I/O) - Chip address bit 1 in I²C Mode or data output in SPI Mod
0/CS 2 23 Address Bit 0/Chip Select (Input) - Chip address bit 0 in I²C Mode or Chip Select in SPI Mode
A/CDIN 3 24 Serial Control Data In (I/O) - Input/Output for I²C data. Input for SPI data
L/CCLK 4 1 Serial Control Port Clock (Input) - Serial clock for the control port interface
and-Alone Definitions
F0
F1
F2
1
3
4
24
1
22
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Seria
Clock, and Serial Audio Data
M 2 23
De-emphasis (Input) - Selects the standard 15 s/50 s digital de-emphasis filter response for
44.1 kHz sample rates
ermal Pad (QFN package only)
ermal Pad n/a —
Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 40 for more informa
tion.DS691F4 7
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CS43502 CHARACTERISTICS AND SPECIFICATIONS
2.1 Recommended Operating Conditions
GND = 0 V; all voltages with respect to ground.
Notes: 1. RMCK output frequency is dependent on VLS.
See Table 6 for supported RMCK frequencies with respect to VLS.
2.2 Absolute Maximum Ratings
GND = 0 V; all voltages with respect to ground (Note 2).
Notes: 2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies.
Table 1. Recommended Operating Conditions
Parameters Symbol Min Typ Max Units
DC Power Supply Analog power VA 4.75 5.0 5.25 V
3.14 3.3 3.46 V
Serial Audio Interface power(Note 1) VLS 1.35 3.3 5.25 V
Control Interface power VLC 3.14 3.3 5.25 V
Ambient Operating Temperature (Power Applied)
Commercial (-CZZ,-CNZ) TA -40 - +85 °C
Automotive (-DZZ) TA -40 - +105 °C
Table 2. Absolute Maximum Ratings
Parameters Symbol Min Max Units
DC Power Supply Analog power VA -0.3 6.0 V
Serial Audio Interface power VLS -0.3 6.0 V
Control Interface power VLC -0.3 6.0 V
Input Current (Note 3) Iin - ±10 mA
Digital Input Voltage Serial Audio Interface VIN-LS -0.3 VLS+ 0.4 V
Control Interface VIN-LC -0.3 VLC+ 0.4 V
Ambient Operating Temperature (power applied) TA -55 125 °C
Storage Temperature Tstg -65 150 °C8 DS691F4
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CS43502.3 DAC Analog Characteristics - Commercial (-CZZ,-CNZ)
Test conditions (unless otherwise specified): VLS = VLC = 3.3 V; TA = 25° C; Input test signal is a 997 Hz
sine wave; Valid with the recommended capacitor values on VD_FILT, VQ, VBIAS (as shown in the typical
connection diagram in Figure 10) and output circuits as shown in Figure 17 and Figure 18; Fs = 48 kHz,
96 kHz, and 192 kHz; measurement bandwidth 10 Hz to 20 kHz.
Notes: 4. One LSB of triangular PDF dither is added to data
5. RL and CL represent the minimum resistance and maximum capacitance required for the CS4350’s in-
ternal op-amp to remain stable. See Figure 1 and Figure 2 for more details.
Table 3. DAC Analog Characteristics - Commercial (-CZZ,-CNZ)
Parameter Symbol Min Typ Max Unit
VA= 5.0 V Single-ended/Differential
Dynamic Range (Note 4) 24-bit A-Weighted
unweighted
16-bit A-Weighted
unweighted
98/106
95/103
-
-
101/109
98/106
95/96
92/93
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 4)
24-bit 0 dB
-20 dB
-60 dB
16-bit 0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-
-91
-78/-86
-38/-46
-90
-72/-73
-32/-33
-86/-87
-
-35/-43
-
-
-
dB
dB
dB
dB
dB
dB
VA= 3.3 V Single-ended/Differential
Dynamic Range (Note 4) 24-bit A-Weighted
unweighted
16-bit A-Weighted
unweighted
98/106
95/103
-
-
101/109
98/106
95/96
92/93
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 4)
24-bit 0 dB
-2 dB
-20 dB
-60 dB
16-bit 0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-
-86
-91/-93
-78/-86
-38/-46
-83
-72/-73
-32/-33
-77
-
-
-35/-43
-
-
-
dB
dB
dB
dB
dB
dB
dB
VA= 3.3 to 5.0 V
Interchannel Isolation (1 kHz) - 100 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 dB
Gain Drift - -400 - ppm/°C
Analog Output
Full Scale Output Voltage - Single Ended -CZZ
-CNZ
2.61
2.45
2.78
2.59
2.96
2.91
Vpp
Vpp
Full Scale Output Voltage - Differential -CZZ
-CNZ
5.22
4.90
5.56
5.18
5.92
5.82
Vpp
Vpp
Quiescent Voltage VQ - 0.5•VA - VDC
Max DC Current draw from an AOUT pin IOUTmax - 10 - A
Max Current draw from VQ IQmax - 100 - A
Max AC-Load Resistance (Note 5) RL - 3 - k
Max Load Capacitance (Note 5) CL - 100 - pF
Output Impedance ZOUT - 100 - DS691F4 9
