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CY22381SXI-146T

hot CY22381SXI-146T

CY22381SXI-146T

For Reference Only

Part Number CY22381SXI-146T
Manufacturer Cypress Semiconductor Corp
Description IC CLOCK GENERATOR
Datasheet CY22381SXI-146T Datasheet
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CY22381SXI-146T Specifications

ManufacturerCypress Semiconductor Corp
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet CY22381SXI-146T Datasheet
Package-
Series*

CY22381SXI-146T Datasheet

Page 1

Page 2

CY22381 CY223811 Three-PLL General Purpose FLASH Programmable Clock Generator Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-07012 Rev. *F Revised December 11, 2008 Features ■ Three integrated phase-locked loops ■ Ultra-wide divide counters (eight-bit Q, eleven-bit P, and seven-bit post divide) ■ Improved linear crystal load capacitors ■ Flash programmability ■ Field programmability ■ Low-jitter, high-accuracy outputs ■ Power-management options (Shutdown, OE, Suspend) ■ Configurable crystal drive strength ■ Frequency select option through external LVTTL Input ■ 3.3V operation ■ 8-pin SOIC package (CY22381) ■ 8-pin SOIC package with NiPdAu lead finish (CY223811) ■ CyClocks RT™ support Benefits ■ Generates up to three unique frequencies on three outputs up to 200 MHz from an external source. Functional upgrade for current CY2081 family. ■ Allows for 0 ppm frequency generation and frequency conversion under the most demanding applications ■ Improves frequency accuracy over temperature, age, process, and initial offset ■ Non-volatile programming enables easy customization, ultra-fast turnaround, performance tweaking, design timing margin testing, inventory control, lower part count, and more secure product supply. Can also be programmed multiple times which reduces programming errors and provides an easy upgrade path for existing designs ■ In-house programming of samples and prototype quantities is available using the CY3672 FTG development Kit. Production quantities are available through Cypress’s value-added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. ■ Performance suitable for high-end multimedia, communications, industrial, A/D converters, and consumer applications ■ Supports numerous low-power application schemes and reduces EMI by allowing unused outputs to be turned off ■ Adjust crystal drive strength for compatibility with virtually all crystals ■ External frequency select option for PLL1, CLKA, and CLKB ■ Industry standard supply voltage ■ Industry standard packaging saves on board space ■ Easy-to-use software support for design entry XTALIN XTALOUT FS/SUSPEND SHUTDOWN/OE CONFIGURATION FLASH OSC. PLL1 11-BIT P 8-BIT Q PLL2 11-BIT P 8-BIT Q PLL3 11-BIT P 8-BIT Q 4 × 3 Switch Crosspoint Divider 7-BIT Divider 7-BIT Divider 7-BIT CLKA CLKB CLKC Logic Block Diagram [+] Feedback

Page 3

CY22381 CY223811 Document #: 38-07012 Rev. *F Page 2 of 9 Pinouts Figure 1. CY22381, CY223811- 8-pin SOIC Operation The CY22381 is an upgrade to the existing CY2081. The new device has a wider frequency range, greater flexibility, improved performance, and incorporates many features that reduce PLL sensitivity to external system issues. The device has three PLLs that allow each output to operate at an independent frequencies. These three PLLs are completely programmable. The CY223811 is the CY22381 with NiPdAu lead finish. Configurable PLLs PLL1 generates a frequency that is equal to the reference divided by an eight-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL1 is sent to the crosspoint switch. The frequency of PLL1 can optionally be changed by using the external CMOS general purpose input. See the following section on “General-Purpose Input” for more detail. PLL2 generates a frequency that is equal to the reference divided by an eight-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL2 is sent to the crosspoint switch. PLL3 generates a frequency that is equal to the reference divided by an eight-bit divider (Q) and multiplied by an 11-bit divider in the PLL feedback loop (P). The output of PLL3 is sent to the cross-point switch. General-Purpose Input The CY22381 features an output control pin (pin 8) that can be programmed to control one of four features. When programmed as a Frequency Select (FS), the input can select between two arbitrarily programmed frequency settings. The Frequency Select can change the following; the frequency of PLL1, the output divider of CLKB, and the output divider of CLKA. Any divider change as a result of switching the FS input is guaranteed to be glitch free. The general-purpose input can simultaneously control the Suspend feature, turning off a set of PLLs and outputs determined during programming. When programmed as an Output Enable (OE) the input forces all outputs to be placed in a three-state condition when LOW. When programmed as a Shutdown, the input forces a full chip shutdown mode when LOW. Crystal Input The input crystal oscillator is an important feature of this device because of its flexibility and performance features. The oscillator inverter has programmable drive strength. This allows for maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. The input load capacitors are placed on-die to reduce external component cost. These capacitors are true parallel-plate capacitors for ultra-linear performance. These were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. Non-linear (FET gate) crystal load capacitors must not be used for MPEG, POTS dial tone, communications, or other applications that are sensitive to absolute frequency requirements The value of the load capacitors is determined by six bits in a programmable register. The load capacitance can be set with a resolution of 0.375pF for a total crystal load range of 6pF to 30pF. For driven clock inputs the input load capacitors may be completely bypassed. This enables the clock chip to accept driven frequency inputs up to 166 MHz. If the application requires a driven input, then XTALOUT must be left floating. Pin Definitions Name Pin Number Description CLKC 1 Configurable clock output C GND 2 Ground XTALIN 3 Reference crystal input or external reference clock input XTALOUT 4 Reference crystal feedback (float if XTALIN is driven by external reference clock) CLKB 5 Configurable clock output B CLKA 6 Configurable clock output A VDD 7 Power supply FS/SUSPEND/ OE/SHUTDOWN 8 General Purpose Input. Can be Frequency Control, Suspend mode control, Output Enable, or full-chip shutdown. 1 2 3 4 5 6 7 8CLKC GND XTALIN XTALOUT FS/SUSPEND/OE/SHUTDOWN VDD CLKA CLKB [+] Feedback

Page 4

CY22381 CY223811 Document #: 38-07012 Rev. *F Page 3 of 9 Output Configuration Under normal operation there are four internal frequency sources that may be routed through a programmable crosspoint switch to any of the three outputs through programmable seven-bit output dividers. The four sources are: reference, PLL1, PLL2, and PLL3. The following is a description of each output. CLKA’s output originates from the crosspoint switch and goes through a programmable seven-bit post divider. The seven-bit post divider derives its value from one of two programmable registers controlled by FS. CLKB’s output originates from the crosspoint switch and goes through a programmable seven-bit post divider. The seven-bit post divider derives its value from one of two programmable registers controlled by FS. CLKC’s output originates from the crosspoint switch and goes through a programmable seven-bit post divider. The seven-bit post divider derives its value from one programmable register. The Clock outputs have been designed to drive a single point load with a total lumped load capacitance of 15pF. While driving multiple loads is possible with the proper termination, it is generally not recommended. Power-Saving Features When configured as OE, the general-purpose input three-states all outputs when pulled LOW. When configured as Shutdown, a LOW on this pin three-states all outputs and shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins is less than 5 μA (typical). After leaving shutdown mode, the PLLs has to relock. When configured as SUSPEND, the general-purpose input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output forces a three-state condition. Improving Jitter Jitter Optimization Control is useful in mitigating problems related to similar clocks switching at the same moment and causing excess jitter. If one PLL is driving more than one output, the negative phase of the PLL can be selected for one of the outputs. This prevents the output edges from aligning, allowing superior jitter performance. CyClocks RT Software CyClocks RT is our second-generation application that allows users to configure this device. The easy-to-use interface offers complete control of the many features of this family including input frequency, PLL and output frequencies, and different functional options. Data sheet frequency range limitations are checked and performance tuning is automatically applied. You can download a free copy of CyClocks RT on Cypress’s web site at http://www.cypress.com. [+] Feedback

Page 5

CY22381 CY223811 Document #: 38-07012 Rev. *F Page 4 of 9 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply Voltage................................................–0.5V to +7.0V DC Input Voltage ..............................–0.5V to + (VDD + 0.5V) Storage Temperature .................................. –65°C to +125°C Junction Temperature .................................................. 125°C Data Retention at Tj = 125°C ................................> 10 years Maximum Programming Cycles........................................100 Package Power Dissipation...................................... 250 mW Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... ≥ 2000V Latch up (per JEDEC 17) .................................... ≥ ±200 mA Operating Conditions Parameter Description Min Typ Max Unit VDD Supply Voltage 3.135 3.3 3.465 V TA Commercial Operating Temperature, Ambient 0 – +70 °C Industrial Operating Temperature, Ambient –40 – +85 °C CLOAD_OUT Max. Load Capacitance – – 15 pF fREF External Reference Crystal 8 – 30 MHz External Reference Clock[2], Commercial 1 – 166 MHz External Reference Clock[2], Industrial 1 – 150 MHz tPU Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms Electrical Characteristics Parameter Description Conditions[1] Min Typ Max Unit IOH Output High Current[3] VOH = VDD – 0.5, VDD = 3.3 V 12 24 – mA IOL Output Low Current[3] VOL = 0.5V, VDD = 3.3 V 12 24 – mA CXTAL_MIN Crystal Load Capacitance[3] Capload at minimum setting – 6 – pF CXTAL_MAX Crystal Load Capacitance[3] Capload at maximum setting – 30 – pF CIN Input Pin Capacitance[3] Except crystal pins – 7 – pF VIH HIGH-level Input Voltage CMOS levels,% of VDD 70% – – VDD VIL LOW-level Input Voltage CMOS levels,% of VDD – – 30% VDD IIH Input HIGH Current VIN = VDD – 0.3 V – <1 10 μA IIL Input LOW Current VIN = +0.3 V – <1 10 μA IOZ Output Leakage Current Three-state outputs – – 10 μA IDD Total Power Supply Current 3.3 V Power Supply; 3 outputs at 50 MHz – 35 – mA 3.3 V Power Supply; 3 outputs at 166 MHz – 70 – mA IDDS Total Power Supply Current in Shutdown Mode Shutdown active – 5 20 μA Notes 1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions. 2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 3. Guaranteed by design, not 100% tested. [+] Feedback

Page 6

CY22381 CY223811 Document #: 38-07012 Rev. *F Page 5 of 9 Switching Characteristics Parameter Name Description Min Typ. Max Unit 1/t1 Output Frequency[3, 4] Clock output limit, Commercial – – 200 MHz Clock output limit, Industrial – – 166 MHz t2 Output Duty Cycle[3, 5] Duty cycle for outputs, defined as t2 ÷ t1, Fout < 100 MHz, divider >= 2, measured at VDD/2 45% 50% 55% Duty cycle for outputs, defined as t2 ÷ t1, Fout > 100 MHz or divider = 1, measured at VDD/2 40% 50% 60% t3 Rising Edge Slew Rate[3] Output clock rise time, 20% to 80% of VDD 0.75 1.4 – V/ns t4 Falling Edge Slew Rate[3] Output clock fall time, 20% to 80% of VDD 0.75 1.4 – V/ns t5 Output Three-state Timing[3] Time for output to enter or leave three-state mode after SHUTDOWN/OE switches – 150 300 ns t6 Clock Jitter[3, 6] Peak-to-peak period jitter, CLK outputs measured at VDD/2 – 200 – ps t7 Lock Time[3] PLL Lock Time from Power up – 1.0 3 ms Switching Waveforms Notes 4. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications. 5. Reference Output duty cycle depends on XTALIN duty cycle. 6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate. t1 OUTPUT t2 t3 t4 Figure 2. All Outputs, Duty Cycle and Rise and Fall Time t5 OE ALL OUTPUTS t5 THREE-STATE Figure 3. Output Three-State Timing CLK OUTPUT t6 Figure 4. CLK Output Jitter [+] Feedback

Page 7

CY22381 CY223811 Document #: 38-07012 Rev. *F Page 6 of 9 Test Circuit Switching Waveforms (continued) SELECT OLD SELECT NEW SELECT STABLE Fold Fnewt7 OUTPUT Figure 5. Frequency Change 0.1 mF VDD CLKout CLOAD GND OUTPUTS [+] Feedback

Page 8

CY22381 CY223811 Document #: 38-07012 Rev. *F Page 7 of 9 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY22381FC[8] 8-SOIC Commercial (TA=0°C to 70°C) 3.3V CY22381FCT[8] 8-SOIC – Tape and Reel Commercial (TA=0°C to 70°C) 3.3V CY22381SI-xxxT[7, 8] 8-SOIC – Tape and Reel Industrial (TA=–40°C to 85°C) 3.3V CY3672-USB FTG Programmer CY3699 CY22381F Adapter for CY3672-USB Pb-Free CY223811FXI 8-SOIC with NiPdAu lead frame Industrial (TA=–40°C to 85°C) 3.3V CY22381FSZC[9] 8-SOIC Commercial (TA=0°C to 70°C) 3.3V CY22381FXC[9] 8-SOIC Commercial (TA=0°C to 70°C) 3.3V CY22381FXCT 8-SOIC – Tape and Reel Commercial (TA=0°C to 70°C) 3.3V CY22381FXI 8-SOIC Industrial (TA=–40°C to 85°C) 3.3V CY22381FXIT 8-SOIC – Tape and Reel Industrial (TA=–40°C to 85°C) 3.3V CY22381SXC-xxx[7] 8-SOIC Commercial (TA=0°C to 70°C) 3.3V CY22381SXC-xxxT[7] 8-SOIC – Tape and Reel Commercial (TA=0°C to 70°C) 3.3V CY22381SXI-xxx[7] 8-SOIC Industrial (TA=–40°C to 85°C) 3.3V CY22381SXI-xxxT[7] 8-SOIC – Tape and Reel Industrial (TA=–40°C to 85°C) 3.3V Notes 7. The CY22381SI-xxx, CY22381SXC-xxx and CY22381SXI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of 100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. 8. Not recommended for new designs. 9. The CY22381FSZC and CY22381FXC are identical. For new designs, use CY22381FXC. [+] Feedback

Page 9

CY22381 CY223811 Document #: 38-07012 Rev. *F Page 8 of 9 Package Drawing and Dimensions SEATING PLANE PIN 1 ID 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 0°~8° 0.016[0.406] 0.010[0.254] X 45° 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.004[0.102] 8 Lead (150 Mil) SOIC - S08 14 5 8 3. REFERENCE JEDEC MS-012 PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 4. PACKAGE WEIGHT 0.07gms 51-85066-*C Figure 6. 8-Pin (150-Mil) SOIC S8 [+] Feedback

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December 11, 2019

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