Contact Us
SalesDept@heisener.com +86-755-83210559 ext. 811

CY28411ZXC

hotCY28411ZXC

CY28411ZXC

For Reference Only

Part Number CY28411ZXC
Manufacturer Silicon Labs
Description IC CLOCK CK410M ALVISO 56TSSOP
Datasheet CY28411ZXC Datasheet
Package 56-TFSOP (0.240", 6.10mm Width)
In Stock 32,782 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 18 - Jul 23 (Choose Expedited Shipping)
Request for Quotation

Part Number # CY28411ZXC (Clock/Timing - Application Specific) is manufactured by Silicon Labs and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For CY28411ZXC specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add CY28411ZXC with quantity into BOM. Heisener.com does NOT require any registration to request a quote of CY28411ZXC.

CY28411ZXC Specifications

ManufacturerSilicon Labs
CategoryIntegrated Circuits (ICs) - Clock/Timing - Application Specific
Datasheet CY28411ZXCDatasheet
Package56-TFSOP (0.240", 6.10mm Width)
Series-
PLLYes
Main PurposeIntel CPU Servers
InputLVTTL, Crystal
OutputHCSL, LVCMOS
Number of Circuits1
Ratio - Input:Output3:19
Differential - Input:OutputNo/Yes
Frequency - Max133MHz
Voltage - Supply3.135 V ~ 3.465 V
Operating Temperature0°C ~ 85°C
Mounting TypeSurface Mount
Package / Case56-TFSOP (0.240", 6.10mm Width)
Supplier Device Package56-TSSOP

CY28411ZXC Datasheet

Page 1

Page 2

Clock Generator for Intel®Alviso Chipset CY28411Features • Compliant to Intel CK410M • Supports Intel Pentium-M CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 48 MHz USB clocks • 33 MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages CPU SRC PCI REF DOT96 USB_48 x2 / x3 x7 / x8 x 6 x 1 x 1 x 1 Block Diagram Pin Configuration VDD_PCI VSS_PCI PCI4 PCI5 VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1 VTT_PWRGD#/PD VDD_48 USB_48/FS_A VSS_48 DOT96T DOT96C FS_B/TEST_MODE SRCT0 SRCC0 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 PCI2 PCI_STP# SRCC5 CPUT2_ITP/SRCT7 VSSA VDDA IREF CPUT1 CPUC1 VDD_CPU CPUT0 CPUC0 VSS_CPU SDATA SCLK VDD_REF XIN VSS_REF FS_C/TEST_SEL REF CPU_STP# CPUC2_ITP/SRCC7 SRC4_SATAT SRC4_SATAC VDD_SRC VDD_SRC SRCT6 SRCT5 VSS_SRC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 31 30 29 VDD_REF XTAL PLL Ref FreqXOUT XIN OSC SCLK PLL1 I2C Logic VDD_48 MHz SDATA VDD_PCI Divider Network VDD_CPU FS_[C:A] REF VTT_PWRGD# IREF PCI[2:5] PLL2 CPUT[0:1], CPUC[0:1], VDD_SRC SRCT[0:6], SRCC[0:6] USB_48 CPU_STP# PCI_STP# PCI3 SRCC6 XOUT C Y 28 411 56 SSOP/TSSOP DOT96T DOT96C VDD_PCIF PCIF[0:1] CPU(T/C)2_ITP] PD ........................ Document #: 38-07594 Rev. *B Page 1 of 18 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com

Page 3

CY28411 Pin Definitions Pin No. Name Type Description 54 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active low. 44,43,41,40 CPUT/C O, DIF Differential CPU clock outputs. 36,35 CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 14,15 DOT96T, DOT96C O, DIF Fixed 96 MHz clock output. 12 FS_A/USB_48 I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 16 FS_B/TEST_MODE I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when in test mode 0 = Hi-Z, 1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 53 FS_C/TEST_SEL I 3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is asserted low. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi- cations. 39 IREF I A precision resistor is attached to this pin, which is connected to the internal current reference. 56,3,4,5 PCI O, SE 33 MHz clocks. 55 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# active low. 8 PCIF0/ITP_EN I/O, SE 33 MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC7 9 PCIF1 O, SE 33 MHz clocks. 52 REF O, SE Reference clock. 3.3V 14.318-MHz clock output. 46 SCLK I SMBus-compatible SCLOCK. 47 SDATA I/O SMBus-compatible SDATA. 26,27 SRC4_SATAT, SRC4_SATAC O, DIF Differential serial reference clock. Recommended output for SATA. 24,25,22,23, 19,20,17,18, 33,32,31,30 SRCT/C O, DIF Differential serial reference clocks. 11 VDD_48 PWR 3.3V power supply for outputs. 42 VDD_CPU PWR 3.3V power supply for outputs. 1,7 VDD_PCI PWR 3.3V power supply for outputs. 48 VDD_REF PWR 3.3V power supply for outputs. 21,28,34 VDD_SRC PWR 3.3V power supply for outputs. 37 VDDA PWR 3.3V power supply for PLL. 13 VSS_48 GND Ground for outputs. 45 VSS_CPU GND Ground for outputs. 2,6 VSS_PCI GND Ground for outputs. 51 VSS_REF GND Ground for outputs. 29 VSS_SRC GND Ground for outputs. 38 VSSA GND Ground for PLL. 10 VTT_PWRGD#/PD I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active low) assertion, this pin becomes a real-time input for asserting power down (active high). 50 XIN I 14.318 MHz crystal input. 49 XOUT O, SE 14.318 MHz crystal output.........................Document #: 38-07594 Rev. *B Page 2 of 18

Page 4

CY28411 Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B and FS_C input values. For all logic levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B and FS_C transitions will be ignored, except in test mode. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Frequency Select Table FS_A, FS_B and FS_C FS_C FS_B FS_A CPU SRC PCIF/PCI REF0 DOT96 USB MID 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 96 MHz 48 MHz 0 1 1 RESERVED 0 1 0 0 0 0 MID 0 0 MID 1 0 MID 1 1 1 0 x Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 0 REF/2 REF/8 REF/24 REF REF REF 1 1 1 REF/2 REF/8 REF/24 REF REF REF Table 2. Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Block Read Protocol Bit Description Bit Description 1 Start 1 Start 8:2 Slave address – 7 bits 8:2 Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start........................Document #: 38-07594 Rev. *B Page 3 of 18

Page 5

CY28411 Control Registers 28 Acknowledge from slave 27:21 Slave address – 7 bits 36:29 Data byte 1 – 8 bits 28 Read = 1 37 Acknowledge from slave 29 Acknowledge from slave 45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits 46 Acknowledge from slave 38 Acknowledge .... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits .... Data Byte N –8 bits 47 Acknowledge .... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits .... Stop 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 1 Start 1 Start 8:2 Slave address – 7 bits 8:2 Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte – 8 bits 20 Repeated start 28 Acknowledge from slave 27:21 Slave address – 7 bits 29 Stop 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Block Read Protocol Bit Description Bit Description Byte 0:Control Register 0 Bit @Pup Name Description 7 1 CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Hi-Z), 1 = Enable 6 1 SRC[T/C]6 SRC[T/C]6 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable ........................Document #: 38-07594 Rev. *B Page 4 of 18

Page 6

CY28411 2 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 SRC[T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name Description 7 1 PCIF0 PCIF0 Output Enable 0 = Disabled, 1 = Enabled 6 1 DOT_96T/C DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled 5 1 USB_48 USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled 4 1 REF REF Output Enable 0 = Disabled, 1 = Enabled 3 0 Reserved Reserved 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled 0 0 CPUT/C SRCT/C PCIF PCI Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name Description 7 1 PCI5 PCI5 Output Enable 0 = Disabled, 1 = Enabled 6 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 3 1 Reserved Reserved, Set = 1 2 1 Reserved Reserved, Set = 1 1 1 Reserved Reserved, Set = 1 0 1 PCIF1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Byte 3: Control Register 3 Bit @Pup Name Description 7 0 SRC7 Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 6 0 SRC6 Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 5 0 SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 0:Control Register 0 (continued) Bit @Pup Name Description........................Document #: 38-07594 Rev. *B Page 5 of 18

Page 7

CY28411 4 0 SRC4 Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 SRC3 Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 0 SRC2 Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 SRC1 Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 0 0 SRC0 Allow control of SRC[T/C]0 with assertion of PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 4: Control Register 4 Bit @Pup Name Description 7 0 Reserved Reserved, Set = 0 6 0 DOT96T/C DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Hi-Z 5 0 Reserved Reserved, Set = 0 4 0 PCIF1 Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 PCIF0 Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Byte 5: Control Register 5 Bit @Pup Name Description 7 0 SRC[T/C][7:0] SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted 6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted 5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted 4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted 3 0 SRC[T/C][7:0] SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted Byte 3: Control Register 3 (continued) Bit @Pup Name Description........................Document #: 38-07594 Rev. *B Page 6 of 18

Page 8

CY28411 Crystal Recommendations The CY28411 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28411 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm perfor- mance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Byte 6: Control Register 6 Bit @Pup Name Description 7 0 REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N Clock 6 0 Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Hi-Z mode, 5 0 Reserved Reserved, Set = 0 4 1 REF REF Output Drive Strength 0 = Low, 1 = High 3 1 PCIF, SRC, PCI SW PCI_STP Function 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. 2 Externally selected CPUT/C FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during VTT_PWRGD# assertion 1 Externally selected CPUT/C FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during VTT_PWRGD# assertion 0 Externally selected CPUT/C FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during VTT_PWRGD# assertion Byte 7: Vendor ID Bit @Pup Name Description 7 0 Revision Code Bit 3 Revision Code Bit 3 6 0 Revision Code Bit 2 Revision Code Bit 2 5 0 Revision Code Bit 1 Revision Code Bit 1 4 1 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm........................Document #: 38-07594 Rev. *B Page 7 of 18

Page 9

CY28411 Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capac- itance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs..............................................Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs..............................................Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) Figure 1. Crystal Capacitive Clarification XTAL Ce2Ce1 Cs1 Cs2 X1 X2 Ci1 Ci2 Clock Chip Trace 2.8pF Trim 33pF Pin 3 to 6p Figure 2. Crystal Loading Example Load Capacitance (each side) Total Capacitance (as seen by the crystal) Ce = 2 * CL – (Cs + Ci) Ce1 + Cs1 + Ci1 1 + Ce2 + Cs2 + Ci2 1( ) 1=CLe........................Document #: 38-07594 Rev. *B Page 8 of 18

Page 10

CY28411 PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthe- sizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) – Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must held high or Hi-Zd (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition within four clock periods. When the SMBus PD drive mode bit corre- sponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tristate. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,166,200,266,333 and 400MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 uS after asserting Vtt_PwrGd#. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. Figure 3. Power-down Assertion Timing Waveform PD USB, 48MHz DOT96T DOT96C SRCT 100MHz SRCC 100MHz CPUT, 133MHz PCI, 33 MHz REF CPUC, 133MHz Figure 4. Power-down Deassertion Timing Waveform DOT96C PD CPUC, 133MHz CPUT, 133MHz SRCC 100MHz USB, 48MHz DOT96T SRCT 100MHz Tstable <1.8nS PCI, 33MHz REF Tdrive_PWRDN# <300S, >200mV........................Document #: 38-07594 Rev. *B Page 9 of 18

CY28411ZXC Reviews

Average User Rating
5 / 5 (154)
★ ★ ★ ★ ★
5 ★
139
4 ★
15
3 ★
0
2 ★
0
1 ★
0

Write a Review

Not Rated
Thanks for Your Review!

Jayle*****anchard

June 17, 2020

All OK, fast delivery, good quality. Product works as it should, Nice Seller.

Rosal*****ntoya

June 17, 2020

Received the parts, and all parts are in tight packaging without any problems, professional seller.

Ellia*****owers

June 16, 2020

Very supportive of my small orders, but very glad easy to work with. Hard to see how it could be any more efficient!

Bla*****Guha

June 14, 2020

I enjoy Good service from Heisener team , I can get good quality components what I want in heisener.com.

Vaug*****iles

June 12, 2020

Very good connector, easy to realise and with Low price

Joe*****roff

June 7, 2020

Purchasing from Heisener means the real part is obtained no worried for product quality.

Madi***** Ravel

June 5, 2020

Good! quick and convenient delivery. product tracking with good advice.

Harr*****ncock

May 31, 2020

Work Great. Would recommend. Only used 2. So I have 248 extras. Best deal by far that's why I got these.

Juli***** Cruz

May 25, 2020

Used it on my system it works perfect as I need.

Toma*****mpton

May 19, 2020

Purchased this in May and didn't use it until last week. worked and all was good.

CY28411ZXC Guarantees

Service Guarantee

Service Guarantees

We guarantee 100% customer satisfaction.

Our experienced sales team and tech support team back our services to satisfy all our customers.

Quality Guarantee

Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

CY28411ZXC Packaging

Verify Products
Customized Labels
Professional Packaging
Sealing
Packing
Insepction

CY28411ZXC Related Products

9C18000014 9C18000014 TXC CORPORATION, CRYSTAL 18MHZ 20PF SMD, HC49/US, - View
hotMC33884DW MC33884DW NXP, IC SWITCH SDI MONITOR 24-SOIC, 24-SOIC (0.295", 7.50mm Width), - View
RNC55J5620FSBSL RNC55J5620FSBSL Vishay Dale, RES 562 OHM 1/8W 1% AXIAL, Axial, - View
CRCW0603115KFKTA CRCW0603115KFKTA Vishay Dale, RES SMD 115K OHM 1% 1/10W 0603, 0603 (1608 Metric), - View
26S120C 26S120C Murata Power Solutions Inc., FIXED IND 12UH 2.55A 58 MOHM, Nonstandard, - View
431301-25-0 431301-25-0 Curtis Industries, CONN BARRIER STRP 25CIRC 0.438", -, - View
DW-11-15-G-S-520 DW-11-15-G-S-520 Samtec Inc., .025" BOARD SPACERS, -, - View
1774018 1774018 Phoenix Contact, CONN HOOD TOP SZHV10/16 PG29, -, - View
CTV07RW-21-121P-P15AD CTV07RW-21-121P-P15AD Amphenol Aerospace Operations, CONN RCPT MALE 121POS GOLD SLDR, -, - View
TV07RQDZ-25-17SD-LC TV07RQDZ-25-17SD-LC Amphenol Aerospace Operations, CONN RCPT HSG FMALE 42POS PNL MT, -, - View
D38999/26MD18SE-LC D38999/26MD18SE-LC Amphenol Aerospace Operations, CONN PLG HSG FMALE 18POS INLINE, -, - View
ECA30DTBD-S664 ECA30DTBD-S664 Sullins Connector Solutions, CONN EDGE DUAL FMALE 60POS 0.125, -, - View
Payment Methods
Delivery Services

Quick Inquiry

CY28411ZXC

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

View the Certificates

Do you have any question about CY28411ZXC?

+86-755-83210559 ext. 811 SalesDept@heisener.com heisener007 2354944915 Send Message

CY28411ZXC Tags

  • CY28411ZXC
  • CY28411ZXC PDF
  • CY28411ZXC datasheet
  • CY28411ZXC specification
  • CY28411ZXC image
  • Silicon Labs
  • Silicon Labs CY28411ZXC
  • buy CY28411ZXC
  • CY28411ZXC price
  • CY28411ZXC distributor
  • CY28411ZXC supplier
  • CY28411ZXC wholesales

CY28411ZXC is Available in