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Part Number CY7C1021B-15VXC
Manufacturer Cypress Semiconductor Corp
Description IC SRAM 1MBIT 15NS 44SOJ
Datasheet CY7C1021B-15VXC Datasheet
Package 44-BSOJ (0.400", 10.16mm Width)
In Stock 534 piece(s)
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Part Number # CY7C1021B-15VXC (Memory) is manufactured by Cypress Semiconductor Corp and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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CY7C1021B-15VXC Specifications

ManufacturerCypress Semiconductor Corp
CategoryIntegrated Circuits (ICs) - Memory
Datasheet CY7C1021B-15VXCDatasheet
Package44-BSOJ (0.400", 10.16mm Width)
Memory TypeVolatile
Memory FormatSRAM
TechnologySRAM - Asynchronous
Memory Size1Mb (64K x 16)
Memory InterfaceParallel
Clock Frequency-
Write Cycle Time - Word, Page15ns
Access Time15ns
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case44-BSOJ (0.400", 10.16mm Width)
Supplier Device Package44-SOJ

CY7C1021B-15VXC Datasheet

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1-Mbit (64K x 16) Static RAM CY7C1021B Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05145 Rev. *C Revised September 28, 2006 Features • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C — Automotive: –40°C to 125°C • High speed — tAA = 12 ns (Commercial & Industrial) — tAA = 15 ns (Automotive) • CMOS for optimum speed/power • Low active power — 770 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in Pb-free and non Pb-free 44-pin TSOP II and 44-pin 400-mil-wide SOJ Functional Description[1] The CY7C1021B is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021B is available in standard 44-pin TSOP Type II and 44-pin 400-mil-wide SOJ packages. Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Logic Block Diagram 64K x 16 RAM Array I/O1–I/O8 R O W D E C O D E R A7 A6 A5 A4 A3 A0 COLUMN DECODER A 9 A 10 A 11 A 12 A 13 A 14 A 15 512 X 2048 S E N S E A M P S DATA IN DRIVERS OE A2 A1 I/O9–I/O16 CE WE BLE BHE A 8 [+] Feedback

Page 3

CY7C1021B Document #: 38-05145 Rev. *C Page 2 of 10 Pin Configurations Selection Guide -12 -15 Maximum Access Time (ns) 12 15 Maximum Operating Current (mA) Com’l/Ind’l 140 130 Automotive 130 Maximum CMOS Standby Current (mA) Com’l/Ind’l 10 10 Automotive 15 L Version 0.5 0.5 WE 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 Top View SOJ/TSOP II 12 13 41 44 43 42 16 15 29 30 VCC A15 A14 A13 A12 NC A4 A3 OE VSS A5 I/O16 A2 CE I/O3 I/O1 I/O2 BHE NC A1 A0 18 17 20 19 I/O4 27 28 25 26 22 21 23 24 NC VSS I/O7 I/O5 I/O6 I/O8 A6 A7 BLE VCC I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 A8 A9 A10 A11 Pin Definitions Pin Name SOJ, TSOP–Pin Number I/O Type Description A0–A15 1–5,18–21, 24–27, 42–44 Input Address Inputs used to select one of the address locations. I/O1–I/O16 7–10, 13–16, 29–32, 35–38 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. NC 22, 23, 28 No Connect No Connects. Not connected to the die. WE 17 Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. CE 6 Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9, BLE controls I/O8–I/O1. OE 41 Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. VSS 12, 34 Ground Ground for the device. Should be connected to ground of the system. VCC 11, 33 Power Supply Power Supply inputs to the device. [+] Feedback

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CY7C1021B Document #: 38-05145 Rev. *C Page 3 of 10 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied.............................................–55°C to +125°C Supply Voltage on VCC Relative to GND [2] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ......................................–0.5V to VCC+0.5V DC Input Voltage[2]...................................–0.5V to VCC+0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Ambient Temperature (TA) [3] VCC Commercial 0°C to +70°C 5V ± 10% Industrial –40°C to +85°C 5V ± 10% Automotive –40°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions -12 -15 UnitMin. Max. Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V VIH Input HIGH Voltage 2.2 6.0 2.2 6.0 V VIL Input LOW Voltage [2] –0.5 0.8 –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC Com’l/Ind’l –1 +1 –1 +1 µA Auto –4 +4 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled Com’l/Ind’l –1 +1 –1 +1 µA Auto –4 +4 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com’l/Ind’l 140 130 mA Auto 130 mA ISB1 Automatic CE Power Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Com’l/Ind’l 40 40 mA Auto 50 mA ISB2 Automatic CE Power Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l/Ind’l 10 10 mA Auto 15 mA L Version 0.5 0.5 mA Capacitance[4] Parameter Description Test Conditions Max. Unit CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 8 pF COUT Output Capacitance 8 pF Thermal Resistance[4] Parameter Description Test Conditions 44-pin SOJ 44-pin TSOP-II Unit ΘJA Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 64.32 76.89 °C/W ΘJC Thermal Resistance (Junction to Case) 31.03 14.28 °C/W Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 3. TA is the “Instant On” case temperature. 4. Tested initially and after any design or process changes that may affect these parameters. [+] Feedback

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CY7C1021B Document #: 38-05145 Rev. *C Page 4 of 10 AC Test Loads and Waveforms 90% 10% 3.0V GND 90% 10% ALL INPUT PULSES 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE(a) (b) OUTPUT R 481Ω R 481Ω R2 255Ω R2 255Ω 167 Equivalent to: THÉVENIN EQUIVALENT 1.73V 30 pF Rise Time: 1 V/ns Fall Time: 1 V/ns Switching CharacteristicsOver the Operating Range[5] Parameter Description 7C1021B-12 7C1021B-15 UnitMin. Max. Min. Max. Read Cycle tRC Read Cycle Time 12 15 ns tAA Address to Data Valid 12 15 ns tOHA Data Hold from Address Change 3 3 ns tACE CE LOW to Data Valid 12 15 ns tDOE OE LOW to Data Valid 6 7 ns tLZOE OE LOW to Low Z [6] 0 0 ns tHZOE OE HIGH to High Z [6, 7] 6 7 ns tLZCE CE LOW to Low Z [6] 3 3 ns tHZCE CE HIGH to High Z [6, 7] 6 7 ns tPU CE LOW to Power-Up 0 0 ns tPD CE HIGH to Power-Down 12 15 ns tDBE Byte Enable to Data Valid 6 7 ns tLZBE Byte Enable to Low Z 0 0 ns tHZBE Byte Disable to High Z 6 7 ns Write Cycle[8] tWC Write Cycle Time 12 15 ns tSCE CE LOW to Write End 9 10 ns tAW Address Set-Up to Write End 8 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tSD Data Set-Up to Write End 6 8 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z [6] 3 3 ns tHZWE WE LOW to High Z [6, 7] 6 7 ns tBW Byte Enable to End of Write 8 9 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. [+] Feedback

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CY7C1021B Document #: 38-05145 Rev. *C Page 5 of 10 Switching Waveforms Read Cycle No. 1[9, 10] Read Cycle No. 2 (OE Controlled)[10, 11] Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. PREVIOUS DATA VALID DATA VALID tRC tAA tOHA ADDRESS DATA OUT 50%50% DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tHZBE tPD HIGH ICC ISB IMPEDANCE DATA tDBE tLZBE tHZCE I C ISB ADDRESS OE CE BHE, BLE OUT VCC SUPPLY CURRENT [+] Feedback

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CY7C1021B Document #: 38-05145 Rev. *C Page 6 of 10 Write Cycle No. 1 (CE Controlled)[12, 13] Write Cycle No. 2 (BLE or BHE Controlled) Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Switching Waveforms (continued) tHDtSD tSCEtSA tHA tAW tPWE tWC BW DATA ADDRESS BHE, t CE WE BLE I/O tHDtSD tBWtSA tHA tAW tPWE tWC tSCE DATA I/O ADDRESS BHE, BLE WE CE [+] Feedback

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CY7C1021B Document #: 38-05145 Rev. *C Page 7 of 10 Write Cycle No. 3 (WE Controlled, OE LOW) Switching Waveforms (continued) tHDtSD tSCE tHA tAW tPWE tWC tBW DATA I/O ADDRESS CE WE BHE, BLE tSA tLZWE tHZWE Truth Table CE OE WE BLE BHE I/O1–I/O8 I/O9–I/O16 Mode Power H X X X X High Z High Z Power-Down Standby (ISB) L L H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L X L L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C1021B-12VC 51-85082 44-pin (400-Mil) Molded SOJ Commercial CY7C1021B-12VXC 44-pin (400-Mil) Molded SOJ (Pb-Free) CY7C1021B-12ZC 51-85087 44-pin TSOP Type II CY7C1021B-12ZXC 44-pin TSOP Type II (Pb-Free) CY7C1021B-12VI 51-85082 44-pin (400-Mil) Molded SOJ Industrial CY7C1021B-12VXI 44-pin (400-Mil) Molded SOJ (Pb-Free) [+] Feedback

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CY7C1021B Document #: 38-05145 Rev. *C Page 8 of 10 15 CY7C1021B-15VC 51-85082 44-pin (400-Mil) Molded SOJ Commercial CY7C1021B-15VXC 44-pin (400-Mil) Molded SOJ (Pb-Free) CY7C1021B-15ZC 51-85087 44-pin TSOP Type II CY7C1021B-15ZXC 44-pin TSOP Type II (Pb-Free) CY7C1021B-15VI 51-85082 44-pin (400-Mil) Molded SOJ Industrial CY7C1021B-15VXI 44-pin (400-Mil) Molded SOJ (Pb-Free) CY7C1021B-15ZI 51-85087 44-pin TSOP Type II CY7C1021BL-15ZI 44-pin TSOP Type II CY7C1021B-15ZXI 44-pin TSOP Type II (Pb-Free) CY7C1021BL-15ZXI 44-pin TSOP Type II (Pb-Free) CY7C1021B-15VE 51-85082 44-pin (400-Mil) Molded SOJ Automotive CY7C1021B-15VXE 44-pin (400-Mil) Molded SOJ (Pb-Free) CY7C1021B-15ZE 51-85087 44-pin TSOP Type II CY7C1021B-15ZSXE 44-pin TSOP Type II (Pb-Free) Ordering Information (continued) Speed (ns) Ordering Code Package Name Package Type Operating Range Package Diagrams 1 22 2344 0.395 0.405 0.435 0.445 1.120 1.130 0.045 MAX. 0.023 0.033 0.013 0.023 0.050 TYP. 0.095 0.115 0.128 0.148 0.025 MIN. 0.082 MIN. 0°-10° 0.365 0.375 0.007 0.013 SEATING PLANE DIMENSIONS IN INCHES MIN. MAX. 0.004 44-pin (400-Mil) Molded SOJ (51-85082) 51-85082-*B [+] Feedback

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CY7C1021B Document #: 38-05145 Rev. *C Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. All products and company names mentioned in this document may be the trademarks of their respective holders. Package Diagrams (continued) 44-Pin TSOP II (51-85087) 51-85087-*A [+] Feedback

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August 16, 2020

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