1 of 8
Converts CMOS RAMs into Nonvolatile
Unconditionally Write Protects when VCC is
Automatically Switches to Battery when
Space-Saving 8-Pin PDIP or 16-Pin SO
Consumes <100nA of Battery Current
Tests Battery Condition on Power up
Provides for Redundant Batteries
Optional 5% or 10% Power-Fail Detection
Low Forward Voltage Drop on the VCC
Optional Industrial (N) Temperature Range of
-40°C to +85°C
VCCO - RAM Supply
VBAT1 - + Battery 1
TOL - Power Supply Tolerance
GND - Ground
CE - Chip Enable Input
CEO - Chip Enable Output
VBAT2 - + Battery 2
VCCI - + Supply
NC - No Connect
The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of
converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance
condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and
the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a low-
leakage CMOS process which affords precise voltage detection at extremely low battery consumption.
The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the
DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation
can be achieved.
Nonvolatile Controller Chip
DS1210 8-pin PDIP (300 mils)
DS1210S 16-pin SO (300 mils)
19-6294; Rev 6/12
2 of 8
The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM.
First, a switch is provided to direct power from the battery or the incoming supply (VCCI) depending on
which is greater. This switch has a voltage drop of less than 0.3V.
The second function which the nonvolatile controller provides is power-fail detection. The DS1210
constantly monitors the incoming supply. When the supply goes out of tolerance, a precision comparator
detects power-fail and inhibits chip enable ( CEO ).
The third function of write protection is accomplished by holding the CEO output signal to within 0.2
volts of the VCCI or battery supply. If CE input is low at the time power-fail detection occurs, the CEO
output is kept in its present state until CE is returned high. The delay of write protection until the current
memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the range of
4.75 volts to 4.5 volts with the tolerance (TOL) pin grounded. If TOL in connected to VCCO, then power-
fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions CEO will
follow CE with a maximum propagation delay of 20ns.
The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided.
Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the
battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore,
be determined by performing a read cycle after power-up to any location in memory, verifying that
memory location content. A subsequent write cycle can then be executed to the same memory location
altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V
and data is in danger of being corrupted.
The fifth function of the nonvolatile controller provides for battery redundancy. In many applications,
data integrity is paramount. In these applications it is often desirable to use two batteries to ensure
reliability. The DS1210 controller provides an internal isolation switch which allows the connection of
two batteries. During battery backup operation the battery with the highest voltage is selected for use. If
one battery should fail, the other will take over the load. The switch to a redundant battery is transparent
to circuit operation and to the user. A battery status warning will occur when the battery in use falls below
2.0 volts. A grounded VBAT2 pin will not activate a battery-fail warning. In applications where battery
redundancy is not required, a single battery should be connected to the BAT1 pin, and the BAT2 battery
pin must be grounded. The nonvolatile controller contains circuitry to turn off the battery backup. This is
to maintain the battery(s) at its highest capacity until the equipment is powered up and valid data is
written to the SRAM. While in the freshness seal mode the CEO and VCCO will be forced to VOL. When
the batteries are first attached to one or both of the VBAT pins, VCCO will not provide battery back-up until
VCCI exceeds VCCTP, as set by the TOL pin, and then falls below VBAT.
Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section
A shows the connections necessary to write protect the RAM when VCC is less than 4.75 volts and to back
up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when VCC is
less than 4.75 volts and to delay its restart on power-up to prevent spurious writes.
3 of 8
SECTION A - BATTERY BACKUP Figure 1
BATTERY BACKUP CURRENT DRAIN EXAMPLE
DS1210 IBAT 100 nA
RAM ICC02 10 µA
Total Drain 10.1 µA
SECTION B - PROCESSOR RESET
4 of 8
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature Range 0°C to +70°C, -40°C to +85°C for N parts
Storage Temperature Range -55°C to +125°C
Soldering Temperature (reflow, SO) +260°C
Lead Temperature (soldering, 10s) +300°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
Junction-to-Ambient Thermal Resistance (θJA).…………………...…………………………...….110°C/W
Junction-to-Case Thermal Resistance (θJC)…………………………………………………………40°C/W
Junction-to-Ambient Thermal Resistance (θJA).…………………………………………………….70°C/W
Junction-to-Case Thermal Resistance (θJC)…………………………………………………………23°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board for the SO.
For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
RECOMMENDED OPERATING CONDITIONS (Note 10)
PARAMETER SYMBOL 4BMIN TYP MAX UNITS 0BNOTES
TOL = GND Supply Voltage VCCI 4.75 5.0 5.5 V 2
TOL = VCCO Supply Voltage VCCI 4.5 5.0 5.5 V 2
Logic 1 Input VIH 2.2 VCC+0.3 V 2
Logic 0 Input VIL -0.3 +0.8 V 2
Battery Input VBAT1,
2.0 4.0 V 2, 3
DC ELECTRICAL CHARACTERISTICS (Note 10; VCCI = 4.75 to 5.5V, TOL = GND)
(VCCI = 4.5 to 5.5V, TOL = VCCO)
PARAMETER SYMBOL MIN TYP MAX UNITS 1BNOTES
Supply Current ICCI 5 mA 4
Supply Voltage VCCO VCC-0.2 V 2
Supply Current ICCO1 80 mA 5
Input Leakage IIL -1.0 +1.0 µA
Output Leakage ILO -1.0 +1.0 µA
CEO Output @ 2.4V IOH -1.0 mA 6
CEO Output @ 0.4V IOL 4.0 mA 6
VCC Trip Point (TOL=GND) VCCTP 4.50 4.62 4.74 V 2
VCC Trip Point (TOL=VCCO) VCCTP 4.25 4.37 4.49 V 2
CEO Output VOHL VBAT-0.2 V 8
VBAT1 or VBAT2
Battery Current IBAT 100 nA 3, 4
Battery Backup Current
@ VCCO = VBAT – 0.3V
ICCO2 50 µA 7, 8
5 of 8
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS 2BNOTES
Input Capacitance CIN 5 pF
Output Capacitance COUT 7 pF
AC ELECTRICAL CHARACTERISTICS (Note 10; VCCI = 4.75V to 5.5V, TOL = GND)
(VCCI = 4.5V to 5.5V, TOL = VCCO)
PARAMETER SYMBOL MIN TYP MAX UNITS 3BNOTES
CE Propagation Delay tPD 5 10 20 ns 6
CE High to Power-Fail tPF 0 ns
AC ELECTRICAL CHARACTERISTICS (Note 10; VCCI = 4.75V, TOL = GND)
(VCCI < 4.5, TOL = VCCO)
Recovery at Power Up tREC 2 80 125 ms
VCC Slew Rate Power-Down tF 300 µs
VCC Slew Rate Power-Down tFB 10 µs
VCC Slew Rate Power-Up tR 0 µs
CE Pulse Width tCE 1.5 µs 9
2. All voltages are referenced to ground.
3. Only one battery input is required. Unused battery inputs must be grounded.
4. Measured with VCCO and CEO open.
5. ICC01 is the maximum average load which the DS1210 can supply to the memories.
6. Measured with a load as shown in Figure 2.
7. ICC02 is the maximum average load current which the DS1210 can supply to the memories in the battery backup mode.
8. tCE max must be met to ensure data integrity on power loss.
9. CEO can only sustain leakage current in the battery backup mode.
10. All AC and DC electrical characteristics are valid for the full temperature range. For commercial products, this range is 0
to +70°C. For industrial products (N), this range is -40°C to +85°C.
11. DS1210 is recognized by Underwriters Laboratories (UL) under file E99151.
6 of 8
TIMING DIAGRAM: POWER-UP
TIMING DIAGRAM: POWER-DOWN
OUTPUT LOAD Figure 2
7 of 8
PART TEMP RANGE PIN-PACKAGE
DS1210+ 0°C to +70°C 8 PDIP
DS1210N+ -40°C to +85°C 8 PDIP
DS1210S+ 0°C to +70°C 16 SO
DS1210SN+ -40°C to +85°C 16 SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
8 PDIP P8+4 21-0043
16 SO W16+2 21-0042 90-0107