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DS1230Y-150

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DS1230Y-150

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Part Number DS1230Y-150
Manufacturer Maxim Integrated
Description IC NVSRAM 256KBIT 150NS 28EDIP
Datasheet DS1230Y-150 Datasheet
Package 28-DIP Module (0.600", 15.24mm)
In Stock 171,584 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 27 - Oct 2 (Choose Expedited Shipping)
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Part Number # DS1230Y-150 (Memory) is manufactured by Maxim Integrated and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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DS1230Y-150 Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Memory
Datasheet DS1230Y-150Datasheet
Package28-DIP Module (0.600", 15.24mm)
Series-
Memory TypeNon-Volatile
Memory FormatNVSRAM
TechnologyNVSRAM (Non-Volatile SRAM)
Memory Size256Kb (32K x 8)
Memory InterfaceParallel
Clock Frequency-
Write Cycle Time - Word, Page150ns
Access Time150ns
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeThrough Hole
Package / Case28-DIP Module (0.600", 15.24mm)
Supplier Device Package28-EDIP

DS1230Y-150 Datasheet

Page 1

Page 2

1 of 10 FEATURES  10 years minimum data retention in the absence of external power  Data is automatically protected during power loss  Replaces 32k x 8 volatile static RAM, EEPROM or Flash memory  Unlimited write cycles  Low-power CMOS  Read and write access times of 70 ns  Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time  Full ±10% VCC operating range (DS1230Y)  Optional ±5% VCC operating range (DS1230AB)  Optional industrial temperature range of -40°C to +85°C, designated IND  JEDEC standard 28-pin DIP package  PowerCap Module (PCM) package - Directly surface-mountable module - Replaceable snap-on PowerCap provides lithium backup battery - Standardized pinout for all nonvolatile SRAM products - Detachment feature on PowerCap allows easy removal using a regular screwdriver PIN ASSIGNMENT PIN DESCRIPTION A0 - A14 - Address Inputs DQ0 - DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable VCC - Power (+5V) GND - Ground NC - No Connect DS1230Y/AB 256k Nonvolatile SRAM www.maxim-ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 27 28-Pin Encapsulated Package 740-mil Extended A14 A7 A5 A4 A3 A2 A1 A0 DQ1 DQ0 VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ5 DQ6 28 26 25 24 23 22 21 20 19 18 17 15 16 A12 A6 DQ2 GND DQ4 DQ3 1 NC 2 3 NC NC NC VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NC A14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34 NC GND VBAT 34-Pin PowerCap Module (PCM) (Uses DS9034PC+ or DS9034PCI+ PowerCap) 19-5635; Rev 11/10

Page 3

DS1230Y/AB 2 of 10 DESCRIPTION The DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1230 devices can be used in place of existing 32k x 8 static RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230 devices in the Low Profile Module package are specifically designed for surface-mount applications. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. READ MODE The DS1230 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A0 - A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1230 devices execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1230AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1230Y provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high- impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1230AB and 4.5 volts for the DS1230Y. FRESHNESS SEAL Each DS1230 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium energy source is enabled for battery back-up operation.

Page 4

DS1230Y/AB 3 of 10 PACKAGES The DS1230 devices are available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM). The 28-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1230 PCM device to be surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow soldering. After a DS1230 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper attachment. DS1230 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for further information.

Page 5

DS1230Y/AB 4 of 10 ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground -0.3V to +6.0V Operating Temperature Range Commercial: 0°C to +70°C Industrial: -40°C to +85°C Storage Temperature Range EDIP -40°C to +85°C PowerCap -55°C to +125°C Lead Temperature (soldering, 10s) +260°C Note: EDIP is wave or hand soldered only. Soldering Temperature (reflow, PowerCap) +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES DS1230AB Power Supply Voltage VCC 4.75 5.0 5.25 V DS1230Y Power Supply Voltage VCC 4.5 5.0 5.5 V Logic 1 VIH 2.2 VCC V Logic 0 VIL 0.0 0.8 V DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1230AB) (TA: See Note 10) (VCC = 5V ±10% for DS1230Y) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -1.0 +1.0 µA I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA Output Current @ 2.4V IOH -1.0 mA Output Current @ 0.4V IOL 2.0 mA Standby Current CE =2.2V ICCS1 200 600 µA Standby Current CE =VCC-0.5V ICCS2 50 150 µA Operating Current ICCO1 85 mA Write Protection Voltage (DS1230AB) VTP 4.50 4.62 4.75 V Write Protection Voltage (DS1230Y) VTP 4.25 4.37 4.5 V CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 5 10 pF Input/Output Capacitance CI/O 5 10 pF

Page 6

DS1230Y/AB 5 of 10 AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1230AB) (TA: See Note 10) (VCC = 5V ±10% for DS1230Y) PARAMETER SYMBOL DS1230AB-70 DS1230Y-70 UNITS NOTES MIN MAX Read Cycle Time tRC 70 ns Access Time tACC 70 ns OE to Output Valid tOE 35 ns CE to Output Valid tCO 70 ns OE or CE to Output Active tCOE 5 ns 5 Output High-Z from Deselection tOD 25 ns 5 Output Hold from Address Change tOH 5 ns Write Cycle Time tWC 70 ns Write Pulse Width tWP 55 ns 3 Address Setup Time tAW 0 ns Write Recovery Time tWR1 tWR2 5 15 ns 12 13 Output High-Z from WE tODW 25 ns 5 Output Active from WE tOEW 5 ns 5 Data Setup Time tDS 30 ns 4 Data Hold Time tDH1 tDH2 0 10 ns 12 13

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DS1230Y/AB 6 of 10 READ CYCLE SEE NOTE 1 WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12

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DS1230Y/AB 7 of 10 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8, and 13 POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING (TA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC Fail Detect to CE and WE Inactive tPD 1.5 µs 11 VCC slew from VTP to 0V tF 150 µs VCC slew from 0V to VTP tR 150 µs VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms

Page 9

DS1230Y/AB 8 of 10 (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention Time tDR 10 years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a Read Cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1230 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to +85°C. 11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. DS1230 modules are recognized by Underwriters Laboratories (UL) under file E99151. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Output Load: 100 pF + 1TTL Gate Cycle = 200 ns for operating current Input Pulse Levels: 0 - 3.0V All voltages are referenced to ground Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns

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DS1230Y/AB 9 of 10 ORDERING INFORMATION PART TEMP RANGE SUPPLY TOLERANCE PIN-PACKAGE SPEED GRADE (ns) DS1230AB-70+ 0°C to +70°C 5V ± 5% 28 740 EDIP 70 DS1230ABP-70+ 0°C to +70°C 5V ± 5% 34 PowerCap* 70 DS1230AB-70IND+ -40°C to +85°C 5V ± 5% 28 740 EDIP 70 DS1230ABP-70IND+ -40°C to +85°C 5V ± 5% 34 PowerCap* 70 DS1230Y-70+ 0°C to +70°C 5V ± 10% 28 740 EDIP 70 DS1230YP-70+ 0°C to +70°C 5V ± 10% 34 PowerCap* 70 DS1230Y-70IND+ -40°C to +85°C 5V ± 10% 28 740 EDIP 70 DS1230YP-70IND+ -40°C to +85°C 5V ± 10% 34 PowerCap* 70 +Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 EDIP MDT28+3 — 21-0245 34 PCAP PC2+4 — 21-0246

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