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DS1672-33+

hot DS1672-33+

DS1672-33+

For Reference Only

Part Number DS1672-33+
Manufacturer Maxim Integrated
Description IC RTC BINARY CNT I2C 8-DIP
Datasheet DS1672-33+ Datasheet
Package 8-DIP (0.300", 7.62mm)
In Stock 421 piece(s)
Unit Price $ 2.83 *
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DS1672-33+

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DS1672-33+ Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Clock/Timing - Real Time Clocks
Datasheet DS1672-33+ Datasheet
Package8-DIP (0.300", 7.62mm)
Series-
TypeBinary Counter
FeaturesTrickle-Charger
Time FormatBinary
Date FormatBinary
InterfaceI2C, 2-Wire Serial
Voltage - Supply2.97 V ~ 3.63 V
Voltage - Supply, Battery1.3 V ~ 3.63 V
Current - Timekeeping (Max)500µA @ 3.63V
Operating Temperature-40°C ~ 85°C
Mounting TypeThrough Hole
Package / Case8-DIP (0.300", 7.62mm)
Supplier Device Package8-PDIP

DS1672-33+ Datasheet

Page 1

Page 2

1 of 15 GENERAL DESCRIPTION The DS1672 incorporates a 32-bit counter and power-monitoring functions. The 32-bit counter is designed to count seconds and can be used to derive time-of-day, week, month, month, and year by using a software algorithm. A precision, temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated that forces the reset to the active state. When VCC returns to an in-tolerance condition, the reset signal is kept in the active state for a period of time to allow the power supply and processor to stabilize. FEATURES  32-Bit Counter  I2C Serial Interface  Automatic Power-Fail Detect and Switch Circuitry  Power-Fail Reset Output  Low-Voltage Oscillator Operation (1.3V min)  Trickle-Charge Capability  Underwriters Laboratories (UL) Recognized  -40°C to +85°C Operating Range PIN CONFIGURATION . TYPICAL OPERATING CIRCUIT PDIP SO µSOP TOP VIEW 1 2 3 4 8 7 6 5 VCC RST SCL SDA X1 X2 VBACKUP GND DS1672 DS1672 I2C 32-Bit Binary Counter RTC 19-6032; Rev 9/11

Page 3

DS1672 2 of 15 ORDERING INFORMATION PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK* DS1672-2+ -40°C to +85°C 2.0 8 PDIP (300 mils) DS1672-2 DS1672-3+ -40°C to +85°C 3.0 8 PDIP (300 mils) DS1672-3 DS1672-33+ -40°C to +85°C 3.3 8 PDIP (300 mils) DS1672-33 DS1672S-2+ -40°C to +85°C 2.0 8 SO (150 mils) D1672-2 DS1672S-3+ -40°C to +85°C 3.0 8 SO (150 mils) D1672-3 DS1672S-33+ -40°C to +85°C 3.3 8 SO (150 mils) D167233 DS1672S-3+T&R -40°C to +85°C 3.0 8 SO (150 mils)/Tape and Reel D1672-3 DS1672S-33+T&R -40°C to +85°C 3.3 8 SO (150 mils)/Tape and Reel D167233 DS1672U-2+ -40°C to +85°C 2.0 8 µSOP(3mm) 1672 rr -2 DS1672U-3+ -40°C to +85°C 3.0 8 µSOP(3mm) 1672 rr -3 DS1672U-33+ -40°C to +85°C 3.3 8 µSOP(3mm) 1672 rr -33 DS1672U-33+T&R -40°C to +85°C 3.3 8 µSOP(3mm)/Tape and Reel 1672 rr -33 + Denotes a lead-free/RoHS-compliant device. * A “+” anywhere on the top mark denotes a lead-free device. rr = 2-digit alphanumeric revision code.

Page 4

DS1672 3 of 15 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +6.0V Operating Temperature Range (noncondensing) ...…………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………….-55°C to +125°C Soldering Temperature (reflow)………………………………………….…………………. +260°C Lead Temperature (soldering, 10s) ……………………………………………………………….. +260°C This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C) (Note 1) PARAMETER SYMBOL MIN TYP MAX UNITS Supply Voltage DS1672-2 VCC 1.8 2.0 5.5 V DS1672-3 VCC 2.7 3.0 5.5 DS1672-33 VCC 2.97 3.3 5.5 Logic 1 VIH 0.7 x VCC VCC + 0.5 V Logic 0 VIL -0.5 +0.3 x VCC V Backup Supply Voltage VBACKUP 1.3 3.0 3.63 V Note 1: All voltages referenced to ground. DC ELECTRICAL CHARACTERISTICS (VCCMIN < VCC < VCCMAX, TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Supply Current (Note 2) ICCA -2: VCC = 2.2V 600 µA -3: VCC = 3.3V -33: VCC = 3.63V Standby Current (Note 3) ICCS -2: VCC = 2.2V 500 µA -3: VCC = 3.3V -33: VCC = 3.63V Power-Fail Voltage VPF -2: 2.70 2.88 2.97 V -3: 2.45 2.60 2.70 -33: 1.58 1.70 1.80 VBACKUP Leakage Current IBACKUPLKG 25 50 nA Logic 0 Output (Note 4) IOL VOL = 0.4V 3 mA Logic 0 Output (Note 4, DS1672-2 Only) IOL VCC > 2V; VOL = 0.4V 3 mA VCC < 2V; VOL = VCC * 0.2 Note 1: All voltages referenced to ground. Note 2: ICCA specified with SCL clocking at max frequency (400kHz), trickle charger disabled. Note 3: ICCS specified with VCC = VCCTYP and SDA, SCL = VCCTYP, trickle charger disabled. Note 4: SDA and RST.

Page 5

DS1672 4 of 15 DC ELECTRICAL CHARACTERISTICS (VCC = 0V, TA = -40°C to +85°C.) (Note 5) PARAMETER SYMBOL MIN TYP MAX UNITS VBACKUP Current (Oscillator On) IBACKUPOSC 0.425 1 µA VBACKUP Current (Oscillator Off) IBACKUP 200 nA Note 5: Using the recommended crystal on X1 and X2. CRYSTAL SPECIFICATIONS* PARAMETER SYMBOL MIN TYP MAX UNITS Nominal Frequency fO 32.768 kHz Series Resistance ESR 45 kΩ Load Capacitance CL 6 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications

Page 6

DS1672 5 of 15 AC ELECTRICAL CHARACTERISTICS (VCC = 0V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL Fast mode 100 400 kHz Standard mode 100 Bus Free Time Between a STOP and START Condition tBUF Fast mode 1.3 µs Standard mode 4.7 Hold Time (Repeated) START Condition (Note 6) tHD:STA Fast mode 0.6 µs Standard mode 4.0 LOW Period of SCL Clock tLOW Fast mode 1.3 µs Standard mode 4.7 HIGH Period of SCL Clock tHIGH Fast mode 0.6 µs Standard mode 4.0 Setup Time for a Repeated START Condition tSU:STA Fast mode 0.6 µs Standard mode 4.7 Data Hold Time (Notes 7, 8) tHD:DAT Fast mode 0 0.9 µs Standard mode 0 Data Setup Time (Note 9) tSU:DAT Fast mode 100 ns Standard mode 250 Rise Time of Both SDA and SCL Signals (Note 10) tR Fast mode 20 + 0.1CB 300 ns Standard mode 1000 Fall Time of Both SDA and SCL Signals (Note 10) tF Fast mode 20 + 0.1CB 300 ns Standard mode 300 Setup Time for STOP Condition tSU:STO Fast mode 0.6 µs Standard mode 4.0 Capacitive Load for Each Bus Line (Note 10) CB 400 pF I/O Capacitance CI/O 10 pF Note 6: After this period, the first clock pulse is generated. Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Note 8:The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: CB–Total capacitance of one bus line in pF.

Page 7

DS1672 6 of 15 POWER-UP/POWER-DOWN CHARACTERISTICS (TA = -40°C to +85°C) PARAMETER SYMBOL MIN TYP MAX UNITS VCC Detect to RST (VCC Falling) tRPD 10 µs VCC Detect to RST (VCC Rising) (Note 11) tRPU 250 ms VCC Fall Time; VPF(MAX) to VPF(MIN) tF 300 µs VCC Rise Time; VPF(MIN) to VPF(MAX) tR 0 µs Note 11: If the EOSC bit in the control register is set to logic 1, tRPU is equal to 250ms plus the startup time of the crystal oscillator. Warning: Negative undershoots below –0.3V while the part is in battery-backed mode can cause loss of data. Figure 1. Timing Diagram SCL START SDA STOP tBUF REPEATED START tHD:STAtLOW tHD:STA tHD:DAT tSU:DATtHIGH tSU:STA tF tSU:STO Figure 2. Power-Up/Power-Down Timing OUTPUTS VCC VPF(max) INPUTS HIGH IMPEDANCE RST DON'T CARE VALID RECOGNIZED RECOGNIZED VALID tRPD VPF(min) tF tPD tR tRPU

Page 8

DS1672 7 of 15 PIN DESCRIPTION PIN NAME FUNCTION 1, 2 X1, X2 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. The DS1672 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is left unconnected. 3 VBACKUP Battery Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 1.3V and 3.63V for proper operation. Diodes placed in series between the power source and the VBACKUP pin may result in improper operation. If a backup supply is not required, VBACKUP must be grounded. UL recognized to ensure against reverse charging current when used in conjunction with a lithium battery (charger disabled). See “Conditions of Acceptability” at www.maxim-ic.com/qa/info/ul. 4 GND Ground. 5 SDA Serial-Data Input/Output. SDA is the input/output pin for the I 2C serial interface. The SDA pin is open drain and requires an external pullup resistor. 6 SCL I 2C Serial-Clock Input. SCL is used to synchronize data movement on the serial interface and requires an external pullup resistor. 7 RST Active-Low Reset Output. It functions as a microprocessor reset signal. This pin is an open-drain output and requires an external pullup resistor. 8 VCC Power pin for Primary Power Supply. When VCC is applied within normal limits, the device is fully accessible and data can be written and read. When VCC is below VPF, reads and writes are inhibited. Figure 3. Recommended Layout for Crystal LOCAL GROUND PLANE (LAYER 2) CRYSTAL X1 X2 GND

Page 9

DS1672 8 of 15 Detailed Description The DS1672 provides a 32-bit counter that increments once-per-second. The counter data is accessible via an I2C serial interface. A precision, temperature-compensated, voltage reference and comparator circuit monitors VCC. When VCC drops below VPF, RST becomes active and the interface is disabled to prevent data corruption. The device switches to the backup supply input, which maintains oscillator and counter operation while VCC is absent. When VCC rises above VPF, RST remains low for a period of time (tRPU) to allow VCC to stabilize. The block diagram in Figure 4 shows the main elements of the DS1672. As shown, communications to and from the DS1672 occur serially over a I2C, bidirectional bus. The DS1672 operates as a slave device on the I2C bus. Access is obtained by implementing a START condition and providing a device identification code followed by a register address. Subsequent registers can be accessed sequentially until a STOP condition is executed. Figure 4. Block Diagram Oscillator Circuit The DS1672 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 4 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second. Table 1. Crystal Specifications* PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Nominal Frequency FO 32.768 kHz Series Resistance ESR 45 kΩ Load Capacitance CL 6 pF * The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Clock Accuracy The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was 32-Bit Counter (4 Bytes) I2C Interface Power Control Address Register Control Logic 1Hz VCC VBACKUP GND SCL SDA Control Trickle Charger X1 X2 RST Dallas Semiconductor DS1672 CL CL N Oscillator and divider

Page 10

DS1672 9 of 15 trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application Note 5: “Crystal Considerations with Dallas Real-Time Clocks” for detailed information. Address Map The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h–03h). The control register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated in Table 2. If the master continues to send or request more data after the address pointer has reached 05h, the address pointer will wrap around to location 00h. Table 2. Registers ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 FUNCTION 00h LSB Counter Byte 1 01h Counter Byte 2 02h Counter Byte 3 03h MSB Counter Byte 4 04h EOSC Control 05h TCS TCS TCS TCS DS DS RS RS Trickle Charger Power Control The device is fully accessible and data can be written and ready only when VCC is greater than VPF. However, when VCC falls below VPF, (point at which write protection occurs) the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. Oscillator and counter operation are maintained from the VBACKUP source until VCC is returned to nominal levels (see Table 3). Table 3. Power Control SUPPLY CONDITION READ/WRITE ACCESS RST POWERED BY VCC < VPF, VCC < VBACKUP No Active VBACKUP VCC < VPF, VCC > VBACKUP No Active VCC VCC > VPF, VCC < VBACKUP Yes Inactive VCC VCC > VPF, VCC > VBACKUP Yes Inactive VCC Oscillator Control The EOSC bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the DS1672 is placed into a low-power standby mode (IBACKUP) when in back-up mode. When the DS1672 is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit; however, the counter is incremented only when EOSC is a logic 0. Microprocessor Monitor A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the power- fail trip point, the RST signal (open drain) is pulled active, and read/write access is inhibited. When VCC returns to nominal levels, the RST signal is kept in the active state for tRPU (typically) to allow the power supply and microprocessor to stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable the oscillator during write protection), the reset signal will be kept in an active state for tRPU plus the startup time of the oscillator.

DS1672-33+ Reviews

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Nao*****Tata

December 4, 2019

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December 4, 2019

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November 2, 2019

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August 7, 2019

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