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Part Number DS87C520-ENL+
Manufacturer Maxim Integrated
Description IC MCU 8BIT 16KB OTP 44TQFP
Datasheet DS87C520-ENL+ Datasheet
Package 44-TQFP
In Stock 213 piece(s)
Unit Price $ 67.0400 *
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Estimated Delivery Time Jan 24 - Jan 29 (Choose Expedited Shipping)
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Part Number # DS87C520-ENL+ (Embedded - Microcontrollers) is manufactured by Maxim Integrated and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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DS87C520-ENL+ Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet DS87C520-ENL+Datasheet
Core Processor8051
Core Size8-Bit
PeripheralsPower-Fail Reset, WDT
Number of I/O32
Program Memory Size16KB (16K x 8)
Program Memory TypeOTP
RAM Size1K x 8
Voltage - Supply (Vcc/Vdd)4.5 V ~ 5.5 V
Data Converters-
Oscillator TypeExternal
Operating Temperature-40°C ~ 85°C (TA)
Mounting Type-
Package / Case44-TQFP
Supplier Device Package44-TQFP (10x10)

DS87C520-ENL+ Datasheet

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1 of 43 REV: 022207 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: FEATURES  80C52 Compatible 8051 Pin- and Instruction-Set Compatible Four 8-Bit I/O Ports Three 16-Bit Timer/Counters 256 Bytes Scratchpad RAM  Large On-Chip Memory 16kB Program Memory 1kB Extra On-Chip SRAM for MOVX  ROMSIZE Feature Selects Internal ROM Size from 0 to 16kB Allows Access to Entire External Memory Map Dynamically Adjustable by Software Useful as Boot Block for External Flash  High-Speed Architecture 4 Clocks/Machine Cycle (8051 = 12) Runs DC to 33MHz Clock Rates Single-Cycle Instruction in 121ns Dual Data Pointer Optional Variable Length MOVX to Access Fast/Slow RAM/Peripherals  Power Management Mode Programmable Clock Source to Save Power CPU Runs from (crystal/64) or (crystal/1024) Provides Automatic Hardware and Software Exit  EMI Reduction Mode Disables ALE  Two Full-Duplex Hardware Serial Ports  High Integration Controller Includes: Power-Fail Reset Early-Warning Power-Fail Interrupt Programmable Watchdog Timer  13 Interrupt Sources with Six External  Available in 40-pin PDIP, 44-Pin PLCC, 44-Pin TQFP, and 40-Pin Windowed CERDIP  Factory Mask DS83C520 or EPROM (OTP) DS87C520 PIN CONFIGURATIONS DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers TOP VIEW The High-Speed Microcontroller User’s Guide must be used in conjunction with this data sheet. Download it at:

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 2 of 43 ORDERING INFORMATION PART TEMP RANGE MAX CLOCK SPEED (MHz) PIN-PACKAGE DS87C520-MCL 0˚C to +70˚C 33 40 Plastic DIP DS87C520-MCL+ 0˚C to +70˚C 33 40 Plastic DIP DS87C520-QCL 0˚C to +70˚C 33 44 PLCC DS87C520-QCL+ 0˚C to +70˚C 33 44 PLCC DS87C520-ECL 0˚C to +70˚C 33 44 TQFP DS87C520-ECL+ 0˚C to +70˚C 33 44 TQFP DS87C520-MNL -40˚C to +85˚C 33 40 Plastic DIP DS87C520-MNL+ -40˚C to +85˚C 33 40 Plastic DIP DS87C520-QNL -40˚C to +85˚C 33 44 PLCC DS87C520-QNL+ -40˚C to +85˚C 33 44 PLCC DS87C520-ENL -40˚C to +85˚C 33 44 TQFP DS87C520-ENL+ -40˚C to +85˚C 33 44 TQFP DS87C520-WCL* 0˚C to +70˚C 33 40 Windowed CERDIP DS83C520-MCL 0˚C to +70˚C 33 40 Plastic DIP DS83C520-MCL+ 0˚C to +70˚C 33 40 Plastic DIP DS83C520-QCL 0˚C to +70˚C 33 44 PLCC DS83C520-QCL+ 0˚C to +70˚C 33 44 PLCC DS83C520-ECL 0˚C to +70˚C 33 44 TQFP DS83C520-ECL+ 0˚C to +70˚C 33 44 TQFP DS83C520-MNL -40˚C to +85˚C 33 40 Plastic DIP DS83C520-MNL+ -40˚C to +85˚C 33 40 Plastic DIP DS83C520-QNL -40˚C to +85˚C 33 44 PLCC DS83C520-QNL+ -40˚C to +85˚C 33 44 PLCC DS83C520-ENL -40˚C to +85˚C 33 44 TQFP DS83C520-ENL+ -40˚C to +85˚C 33 44 TQFP + Denotes a lead(Pb)-free/RoHS-compliant device. * The windowed ceramic DIP package is intrinsically lead(Pb) free.

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 3 of 43 DESCRIPTION The DS87C520/DS83C520 EPROM/ROM high-speed microcontrollers are fast 8051-compatible microcontrollers. They feature a redesigned processor core without wasted clock and memory cycles. As a result, the devices execute every 8051 instruction between 1.5 and 3 times faster than the original for the same crystal speed. Typical applications will see a speed improvement of 2.5 times using the same code and the same crystal. The DS87C520/DS83C520 offer a maximum crystal speed of 33MHz, resulting in apparent execution speeds of 82.5MHz (approximately 2.5X). The DS87C520/DS83C520 are pin compatible with all three packages of the standard 8051, and include standard resources such as three timer/counters, serial port, and four 8-bit I/O ports. They feature 16kB of EPROM or mask ROM with an extra 1kB of data RAM. Both OTP and windowed packages are available. Besides greater speed, the microcontroller includes a second full hardware serial port, seven additional interrupts, programmable Watchdog Timer, Brownout Monitor, and Power-Fail Reset. The device also provides dual data pointers (DPTRs) to speed block data memory moves. It also can adjust the speed of MOVX data memory access from two to nine machine cycles for flexibility in selecting external memory and peripherals. A new Power Management Mode (PMM) is useful for portable applications. This feature allows software to select a lower speed clock as the main time base. While normal operation has a machine cycle rate of 4 clocks per cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. For example, at 12MHz, standard operation has a machine cycle rate of 3MHz. In Power Management Mode, software can select either 187.5kHz or 11.7kHz machine cycle rate. There is a corresponding reduction in power consumption when the processor runs slower. The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE signal when it is unneeded. The DS83C520 is a factory mask ROM version of the DS87C520 designed for high-volume, cost- sensitive applications. It is identical in all respects to the DS87C520, except that the 16kB of EPROM is replaced by a user-supplied application program. All references to features of the DS87C520 will apply to the DS83C520, with the exception of EPROM-specific features where noted. Please contact your local Dallas Semiconductor sales representative for ordering information.

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 4 of 43 Figure 1. Block Diagram PIN DESCRIPTION PIN DIP PLCC TQFP NAME FUNCTION 40 44 38 VCC Positive Supply Voltage. +5V 20 1, 22, 23 16, 17, 39 GND Digital Circuit Ground 9 10 4 RST Reset Input. The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wired OR external reset sources. An RC is not required for power-up, as the device provides this function internally. 18 20 14 XTAL2 19 21 15 XTAL1 Crystal Oscillator Pins. XTAL1 and XTAL2 provide support for parallel-resonant, AT-cut crystals. XTAL1 acts also as an input if there is an external clock source in place of a crystal. XTAL2 serves as the output of the crystal amplifier. 29 32 26 PSEN Program Store-Enable Output. This active-low signal is commonly connected to optional external ROM memory as a chip enable. PSEN provides an active-low pulse and is driven high when external ROM is not being accessed. DS87C520/ DS83C520

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 5 of 43 PIN DESCRIPTION (continued) PIN DIP PLCC TQFP NAME FUNCTION 30 33 27 ALE Address Latch Enable Output. The ALE functions as a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the DS87C520/DS83C520 are in a reset condition. ALE can also be disabled and forced high by writing ALEOFF = 1 (PMR.2). ALE operates independently of ALEOFF during external memory accesses. 39 43 37 P0.0 (AD0) 38 42 36 P0.1 (AD1) 37 41 35 P0.2 (AD2) 36 40 34 P0.3 (AD3) 35 39 33 P0.4 (AD4) 34 38 32 P0.5 (AD5) 33 37 31 P0.6 (AD6) 32 36 30 P0.7 (AD7) Port 0 (AD0–7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an alternate function Port 0 can function as the multiplexed address/data bus to access off-chip memory. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data bus. This bus is used to read external ROM and read/write external RAM memory or peripherals. When used as a memory bus, the port provides active high drivers. The reset condition of Port 0 is tri-state. Pullup resistors are required when using Port 0 as an I/O port. 1 2 40 P1.0 2 3 41 P1.1 3 4 42 P1.2 4 5 43 P1.3 5 6 44 P1.4 6 7 1 P1.5 7 8 2 P1.6 8 9 3 P1.7 Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1. The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input state; a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the DS87C520/DS83C520 will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes the output high (and input) state. The alternate modes of Port 1 are out-lines as follows. Port Alternate Function P1.0 T2 External I/O for Timer/Counter 2 P1.1 T2EX EX Timer/Counter 2 Capture/Reload Trigger P1.2 RXD1 Serial Port 1 Input P1.3 TXD1 Serial Port 1 Output P1.4 INT2 External Interrupt 2 (Positive Edge Detect) P1.5 INT3 External Interrupt 3 (Negative Edge Detect) P1.6 INT4 External Interrupt 4 (Positive Edge Detect) P1.7 INT5 External Interrupt 5 (Negative Edge Detect)

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 6 of 43 PIN DESCRIPTION (continued) PIN DIP PLCC TQFP NAME FUNCTION 21 24 18 P2.0 (A8) 22 25 19 P2.1 (A9) 23 26 20 P2.2 (A10) 24 27 21 P2.3 (A11) 25 28 22 P2.4 (A12) 26 29 23 P2.5 (A13) 27 30 24 P2.6 (A14) 28 31 25 P2.7 (A15) Port 2 (A8–15), I/O. Port 2 is a bidirectional I/O port. The reset condition of Port 2 is logic high. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the DS87C520/DS83C520 will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. As an alternate function Port 2 can function as MSB of the external address bus. This bus can be used to read external ROM and read/write external RAM memory or peripherals. 10 11 5 P3.0 11 13 7 P3.1 12 14 8 P3.2 13 15 9 P3.3 14 16 10 P3.4 15 17 11 P3.5 16 18 12 P3.6 17 19 13 P3.7 Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for External Interrupts, Serial Port 0, Timer 0 and 1 Inputs, and RD and WR strobes. The reset condition of Port 3 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the DS87C520/DS83C520 will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. The alternate modes of Port 3 are outlined below. Port Alternate Mode P3.0 RXD0 Serial Port 0 Input P3.1 TXD0 Serial Port 0 Output P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 External Input P3.5 T1 Timer 1 External Input P3.6 WR External Data Memory Write Strobe P3.7 RD External Data Memory Read Strobe 31 35 29 EA External Access Input, Active Low. Connect to ground to force the DS87C520/DS83C520 to use an external ROM. The internal RAM is still accessible as determined by register settings. Connect EA to VCC to use internal ROM. — 12, 34 6, 28 N.C. Not Connected. These pins should not be connected. They are reserved for use with future devices in this family.

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 7 of 43 COMPATIBILITY The DS87C520/DS83C520 are fully static CMOS 8051-compatible microcontrollers designed for high performance. In most cases, the DS87C520/DS83C520 can drop into an existing socket for the 8xc51 family to improve the operation significantly. While remaining familiar to 8051 family users, the devices have many new features. In general, software written for existing 8051-based systems works without modification on the DS87C520/DS83C520. The exception is critical timing since the high-speed microcontrollers performs instructions much faster than the original for any given crystal selection. The DS87C520/DS83C520 run the standard 8051 family instruction set and are pin compatible with DIP, PLCC, or TQFP packages. The DS87C520/DS83C520 provide three 16-bit timer/counters, full-duplex serial port (2), 256 bytes of direct RAM plus 1kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051 product. Timers will default to a 12-clock per cycle operation to keep their timing compatible with original 8051 family systems. However, timers are individually programmable to run at the new four clocks per cycle if desired. The PCA is not supported. The DS87C520/DS83C520 provide several new hardware features implemented by new special function registers. A summary of these SFRs is provided below. PERFORMANCE OVERVIEW The DS87C520/DS83C520 feature a high-speed 8051-compatible core. Higher speed comes not just from increasing the clock frequency but also from a newer, more efficient design. This updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS87C520/DS83C520, the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions. The majority of instructions on the DS87C520/DS83C520 will see the full 3-to-1 speed improvement. Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the original 8051. The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of individual programs will depend on the actual instructions used. Speed-sensitive applications would make the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. These architecture improvements produce a peak instruction cycle in 121ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. INSTRUCTION SET SUMMARY All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks. For absolute timing of real-time events, the timing of software loops can be calculated using a table in the High-Speed Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation.

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 8 of 43 The relative time of two instructions might be different in the new architecture than it was previously. For example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS87C520/DS83C520, the MOVX instruction takes as little as two machine cycles or eight oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the DS87C520/DS83C520 usually use one instruction cycle for each instruction byte. The user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the original architecture, all were one or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for details and individual instruction timing. SPECIAL FUNCTION REGISTERS Special Function Registers (SFRs) control most special features of the DS87C520/DS83C520. This allows the DS87C520/DS83C520 to have many new features but use the same instruction set as the 8051. When writing software to use a new feature, an equate statement defines the SFR to an assembler or compiler. This is the only change needed to access the new function. The DS87C520/DS83C520 duplicate the SFRs contained in the standard 80C52. Table 1 shows the register addresses and bit locations. The High-Speed Microcontroller User’s Guide describes all SFRs.

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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers 9 of 43 Table 1. Special Function Register Locations REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h SP 81h DPL 82h DPH 83h DPL1 84h DPH1 85h DPS 0 0 0 0 0 0 0 SEL 86h PCON SMOD_0 SMOD0 — — GF1 GF0 STOP IDLE 87h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h TMOD GATE C/T M1 M0 GATE C/T M1 M0 89h TL0 8Ah TL1 8Bh TH0 8Ch TH1 8Dh CKCON WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh PORT1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h EXIF IE5 IE4 IE3 IE XT/RG RGMD RGSL BGS 91h SCON0 SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h SBUF0 99h P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h SADDR0 A9h SADDR1 AAh P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 B0h IP — PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h SADEN0 B9h SADEN1 BAh SCON1 SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 R1_1 C0h SBUF1 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 C1h ROMSIZE — — — — — RMS2 RMS1 RMS0 C2h PMR CD1 CD0 SWB — XTOFF ALEOFF DME1 DME0 C4h STATUS PIP HIP LIP XTUP SPTA1 SPTA1 SPTA0 SPRA0 C5h TA C7h T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 C/RL2 C8h T2MOD — — — — — — T2OE DCEN C9h RCAP2L CAh RCAP2H CBh TL2 CCh TH2 CDh PSW CY AC F0 RS1 RS0 OV FL P D0h WDCON SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT D8h ACC E0h EIE — — — EWDI EX5 EX4 EX3 EX2 E8h B F0h EIP — — — PWDI PX5 PX4 PX3 PX2 F8h Note: New functions are in bold.

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December 24, 2020

I tested some and all look good.


December 19, 2020

Sure appreciate your quality, expertise and professional service. Thank you so much!!!


December 17, 2020

I have used 2 of the 10 units so far and they work fine.

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