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EL5171ISZ

hot EL5171ISZ

EL5171ISZ

For Reference Only

Part Number EL5171ISZ
Manufacturer Renesas Electronics America
Description IC OPAMP DIFF 100MHZ 8SOIC
Datasheet EL5171ISZ Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 718 piece(s)
Unit Price $ 2.45 *
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EL5171ISZ

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EL5171ISZ Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps
Datasheet EL5171ISZ Datasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
Amplifier TypeDifferential
Number of Circuits1
Output TypeDifferential
Slew Rate800 V/µs
Gain Bandwidth Product100MHz
-3db Bandwidth250MHz
Current - Input Bias6µA
Voltage - Input Offset1.5mV
Current - Supply7.5mA
Current - Output / Channel120mA
Voltage - Supply, Single/Dual (±)4.75 V ~ 11 V, ±2.38 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

EL5171ISZ Datasheet

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FN7307 Rev 9.00 August 14, 2015 EL5171, EL5371 250MHz Differential Twisted-Pair Drivers DATASHEETThe EL5171 and EL5371 are single and triple bandwidth amplifiers with an output in differential form. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The input signal is single-ended and the outputs are always differential. On the EL5171 and EL5371, two feedback inputs provide the user with the ability to set the gain of each device (stable at minimum gain of one). For a fixed gain of two, please see EL5170 and EL5370. The output common mode level for each channel is set by the associated VREF pin, which have a -3dB bandwidth of over 50MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL5171 and EL5371 are specified for operation over the full -40°C to +85°C temperature range. Features • Fully differential outputs and feedback • Input range ±2.3V typ. • 250MHz 3dB bandwidth • 800V/µs slew rate • Low distortion at 5MHz • Single 5V or dual ±5V supplies • 90mA maximum output current • Low power - 8mA per channel • Pb-free available (RoHS compliant) Applications • Twisted-pair driver • Differential line driver • VGA over twisted-pair • ADSL/HDSL driver • Single-ended to differential amplification • Transmission of analog signals in a noisy environment Pinouts EL5171 (8 LD SOIC) TOP VIEW EL5371 (28 LD QSOP) TOP VIEW - + FBP IN+ REF FBN OUT+ VS- VS+ OUT- 1 2 3 4 8 7 6 5 1 2 3 4 28 27 26 25 5 6 7 24 23 22 8 21 9 10 20 19 11 12 13 18 17 16 14 15 - + - + - + OUT1 FBP1 FBN1 OUT1B VSP VSN OUT2 FBP2 FBN2 OUT2B OUT3 FBP3 FBN3 OUT3B NC INP1 INN1 REF1 NC INP2 INN2 REF2 NC INP3 INN3 REF3 NC ENFN7307 Rev 9.00 Page 1 of 15 August 14, 2015

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EL5171, EL5371Pin Descriptions EL5171 EL5371 PIN NAME PIN FUNCTION 1 FBP Feedback from non-inverting output 2 IN+ Non-inverting input 3 REF Reference input, sets common-mode output voltage 4 FBN Feedback from inverting output 5 OUT- Inverting output 6 VS+ Positive supply 7 VS- Negative supply 8 OUT+ Non-inverting output 17, 21, 27 FBP3, FBP2, FBP1 Feedback from non-inverting output 2, 6, 10 INP1, INP2, INP3 Non-inverting inputs 4, 8, 12 REF1, REF2, REF3 Reference input, sets common-mode output voltage 3, 7, 11 INN1, INN2, INN3 Inverting inputs, note that on EL5171, this pin is also the REF pin 16, 20, 26 FBN3, FBN2, FBN1 Feedback from inverting output 15, 19, 25 OUT3B, OUT2B, OUT1B Inverting outputs 24 VSP Positive supply 23 VSN Negative supply 18, 22, 28 OUT3, OUT2, OUT1 Non-inverting outputs 1, 5, 9, 13 NC No connects, grounded for best crosstalk performance 14 EN ENABLE Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING PACKAGE (Pb-free) PKG. DWG. # EL5171ISZ 5171ISZ 8 Ld SOIC M8.15E EL5371IUZ (No longer available, recommended replacement: EL5373IUZ) EL5371IUZ 28 Ld QSOP M28.15 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for EL5171, EL5371. For more information on MSL please see tech brief TB363.FN7307 Rev 9.00 Page 2 of 15 August 14, 2015

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EL5171, EL5371IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Input Voltage (IN+, IN- to VS+, VS-) . . . . . . . . . . . . . VS- - 0.3V to VS+ + 0.3V Differential Input Voltage (IN+ to IN-). . . . . . . . . . . . . . . . . . . . . . . . . . ±4.8V Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNIT AC PERFORMANCE BW -3dB Bandwidth AV = 1, CLD = 2.7pF 250 MHz AV = 2, RF = 500, CLD = 2.7pF 60 MHz AV = 10, RF = 500, CLD = 2.7pF 10 MHz BW ±0.1dB Bandwidth AV = 1, CLD = 2.7pF 50 MHz SR Slew Rate (EL5171) VOUT = 3VP-P, 20% to 80% 600 800 1000 V/µs Slew Rate (EL5371) VOUT = 3VP-P, 20% to 80% 540 700 1000 V/µs tSTL Settling Time to 0.1% VOUT = 2VP-P 10 ns tOVR Output Overdrive Recovery Time 20 ns GBWP Gain Bandwidth Product 100 MHz VREFBW (-3dB) VREF -3dB Bandwidth AV =1, CLD = 2.7pF 50 MHz VREFSR+ VREF Slew Rate - Rise VOUT = 2VP-P, 20% to 80% 90 V/µs VREFSR- VREF Slew Rate - Fall VOUT = 2VP-P, 20% to 80% 50 V/µs VN Input Voltage Noise at 10kHz 26 nV/Hz IN Input Current Noise at 10kHz 2 pA/Hz HD2 Second Harmonic Distortion VOUT = 2VP-P, 5MHz -94 dBc VOUT = 2VP-P, 20MHz -94 dBc HD3 Third Harmonic Distortion VOUT = 2VP-P, 5MHz -77 dBc VOUT = 2VP-P, 20MHz -75 dBc dG Differential Gain at 3.58MHz RL = 300, AV = 2 0.1 % d Differential Phase at 3.58MHz RL = 300, AV = 2 0.5 ° eS Channel Separation at f = 1MHz 90 dB INPUT CHARACTERISTICS VOS Input Referred Offset Voltage ±1.5 ±25 mV IIN Input Bias Current (VIN+, VIN-) -14 -6 -3 µA IREF Input Bias Current (VREF) 0.5 1.3 4 µA RIN Differential Input Resistance 300 k CIN Differential Input Capacitance 1 pF DMIR Differential Mode Input Range ±2.1 ±2.3 ±2.5 V CMIR+ Common Mode Positive Input Range at VIN+, VIN- Tested only for EL5371 3.1 3.4 VFN7307 Rev 9.00 Page 3 of 15 August 14, 2015

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EL5171, EL5371CMIR- Common Mode Negative Input Range at VIN+, VIN- Tested only for EL5371 -4.5 -4.2 V VREFIN + Positive Reference Input Voltage Range (EL5371) VIN+ = VIN- = 0V 3.5 ±3.8 V VREFIN - Negative Reference Input Voltage Range (EL5371) VIN+ = VIN- = 0V -3.3 -3 V VREFOS Output Offset Relative to VREF (EL5371) ±60 ±100 mV CMRR Input Common Mode Rejection Ratio (EL5371) VIN = ±2.5V 70 82 dB Gain Gain Accuracy VIN = 1 (EL5171) 0.981 0.996 1.011 V VIN = 1 (EL5371) 0.978 0.993 1.008 V OUTPUT CHARACTERISTICS VOUT Output Voltage Swing RL = 500 to GND (EL5171) ±3.4 V RL = 500 to GND (EL5371) ±3.6 ±3.9 V IOUT(Max) Maximum Output Current RL = 10, VIN = ±3.24 (EL5171) ±70 ±90 ±120 mA RL = 10, VIN = ±3.24 (EL5371) ±50 ±70 ±90 mA ROUT Output Impedance 130 m SUPPLY VSUPPLY Supply Operating Range VS+ to VS- 4.75 11 V IS(ON) Power Supply Current - Per Channel 6.8 7.5 8.2 mA IS(OFF)+ Positive Power Supply Current - Disabled (EL5371) EN pin tied to 4.8V 1.7 10 µA IS(OFF)- Negative Power Supply Current - Disabled (EL5371) -200 -120 µA PSRR Power Supply Rejection Ratio VS from ±4.5V to ±5.5V (EL5171) 70 84 dB VS from ±4.5V to ±5.5V (EL5371) 65 83 dB ENABLE (EL5371 ONLY) tEN Enable Time 215 ns tDS Disable Time 0.95 µs VIH EN Pin Voltage for Power-Up VS+ -1.5 V VIL EN Pin Voltage for Shutdown VS+ -0.5 V IIH-EN EN Pin Input Current High At VEN = 5V 122 130 µA IIL-EN EN Pin Input Current Low At VEN = 0V -10 -8 µA NOTE: 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNITFN7307 Rev 9.00 Page 4 of 15 August 14, 2015

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F N 7 30 7 R e v 9 .0 0 P ag e 5 of 1 5 A u gu st 14 , 20 15 E L 5 17 1 , E L 53 7 1 CL2 5pF CL2B 5pF CL3 5pF CL3B 5pF RLD1 1k RLD2 1k RLD3 1kConnection Diagrams FIGURE 1. EL5171 FIGURE 2. EL5371 FBP INP REF FBN OUT VSN VSP OUTB 1 2 3 4 8 7 6 5 INP REF CL2 OUTB OUT -5V +5V RF3 RF1 RG 5pF RLD 1k CL1 5pF RS1 50 RS1 50 1 2 3 4 20 19 18 17 5 6 7 12 11 9 8 10 24 23 22 21 28 27 26 25 INP1 INN1 REF1 INP2 INN2 REF2 INP3 INN3 REF3 EN OUT1 FBP1 FBN1 OUT1B VSP VSN OUT2 FBP2 FBN2 OUT2B OUT3 FBP3 FBn3 OUT3B14 13 15 16 ENABLE RSR3 50 RSN3 50 RSP3 50 RSR2 50 RSN2 50 RSP2 50 RSR1 50 RSN1 50 RSP1 50 INP1 INN1 REF1 INP2 INN2 REF2 INP3 INN3 REF3 -5V RG RF RF RG RF RF RG RF RF +5V NC NC NC NC CL1 5pF CL1B 5pF

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EL5171, EL5371Typical Performance Curves FIGURE 3. FREQUENCY RESPONSE FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS GAIN FIGURE 5. FREQUENCY RESPONSE vs RLD FIGURE 6. FREQUENCY RESPONSE vs CLD FIGURE 7. FREQUENCY RESPONSE FIGURE 8. FREQUENCY RESPONSE vs RLD 4 3 1 0 -2 -3 -5 -6 10M 100M 1G M A G N IT U D E ( d B ) FREQUENCY (Hz) -4 -1 2 1M VOP-P = 200mV VOP-P = 1VP-P AV = 1, RLD = 1k, CLD = 2.7pF 4 3 1 0 -2 -3 -5 -6 10M 100M 1G FREQUENCY (Hz) -4 -1 2 1M AV = 1 N O R M A L IZ E D M A G N IT U D E ( d B ) AV = 2AV = 5 AV = 10 RLD = 1k, CLD = 2.7pF 4 3 1 0 -2 -3 -5 -6 10M 100M 1G N O R M A L IZ E D G A IN ( d B ) FREQUENCY (Hz) -4 -1 2 1M RLD = 1k RLD = 200 RLD = 500 AV = 1, CLD = 2.7pF 5 4 2 1 -1 -2 -4 -5 10M 100M 1G FREQUENCY (Hz) -3 0 3 1M CLD = 56pF CLD = 34pF CLD = 23pF CLD = 9pF CLD = 2.7pF M A G N IT U D E ( d B ) AV = 1, RLD = 1k 10 9 7 6 4 3 1 0 10M 100M 400M N O R M A L IZ E D G A IN ( d B ) FREQUENCY (Hz) 2 5 8 1M RF = 1k RF = 200 RF = 500 AV = 2, RLD = 1k, CLD = 2.7pF 10 9 7 6 4 3 1 0 10M 100M 400M N O R M A L IZ E D G A IN ( d B ) FREQUENCY (Hz) 2 5 8 1M RLD = 1k RLD = 200 RLD = 500 AV = 2, RF = 1k, CLD = 2.7pFFN7307 Rev 9.00 Page 6 of 15 August 14, 2015

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EL5171, EL5371FIGURE 9. FREQUENCY RESPONSE - VREF FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 11. PSRR vs FREQUENCY FIGURE 12. CMRR vs FREQUENCY FIGURE 13. VOLTAGE AND CURRENT NOISE vs FREQUENCY FIGURE 14. CHANNEL ISOLATION vs FREQUENCY Typical Performance Curves (Continued) 5 4 2 1 -1 -2 -4 -5 1M 10M 100M M A G N IT U D E ( d B ) FREQUENCY (Hz) -3 0 3 100k 100 10 1 0.1 100k 1M 100M IM P E D A N C E (  ) FREQUENCY (Hz) 10k 10M 0 -10 -30 -50 -60 -80 -90 10k 1M 100M P S R R ( d B ) FREQUENCY (Hz) -70 -40 -20 1k 100k 10M PSRR+ PSRR- 1M 100M C M R R ( d B ) FREQUENCY (Hz) 100k 10M 1G 100 90 70 60 40 30 10 0 20 50 80 1k 100 10 1 V O LT A G E N O IS E ( n V / H z) , 100 100k 10M FREQUENCY (Hz) 10 10k 1M1k EN INC U R R E N T N O IS E ( p A / H z) 1M 100M G A IN ( d B ) FREQUENCY (Hz) 100k 10M 1G -30 -40 -60 -70 -90 -100 -80 -50 CH1 <=> CH2, CH2 <=> CH3 CH1 <=> CH3FN7307 Rev 9.00 Page 7 of 15 August 14, 2015

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EL5171, EL5371FIGURE 15. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 16. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 17. HARMONIC DISTORTION vs RLD FIGURE 18. HARMONIC DISTORTION vs RLD FIGURE 19. HARMONIC DISTORTION vs FREQUENCY FIGURE 20. SMALL SIGNAL TRANSIENT RESPONSE Typical Performance Curves (Continued) D IS T O R T IO N ( d B ) VOP-P, DM (V) -100 -90 -80 -70 -60 -55 -50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 HD2 (f = 5MH z) -65 -75 -85 -95 HD3 (f = 20MHz) HD3 (f = 5MHz) VS = ±5V, AV = 1, RLD = 1k HD2 (f = 20M Hz) D IS T O R T IO N ( d B ) VOP-P, DM (V) -90 -80 -70 -60 -55 -50 1 2 3 4 5 6 7 8 9 -65 -75 -85 -95 10 HD2 (f = 5M Hz) HD2 (f = 20MHz) HD3 (f = 20MHz ) HD3 (f = 5MHz) VS = ±5V, AV = 1, RLD = 1k -50 -60 -65 -75 -90 D IS T O R T IO N ( d B ) 200 600 RLD () 100 800400 900 -100 300 500 700 -95 -85 -80 -70 -55 HD2 (f = 20MHz)HD2 (f = 5MHz) HD3 (f = 20MHz) HD3 (f = 5MHz) 1000 VS = ±5V, AV = 1, VOP-P, DM = 1V -40 -50 -60 -70 -90 D IS T O R T IO N ( d B ) -80 300 700 RLD () 200 900500 1000 -100 400 600 800 HD2 (f = 5MHz) HD2 (f = 20MHz) HD3 (f = 5MHz) HD3 (f = 20MHz) VS = ±5V, AV = 2, VOP-P, DM = 2V -90 -70 -60 -50 -40 20 30 40 50 60 FREQUENCY (MHz) D IS T O R T IO N ( d B ) 100 -80 HD2 (AV = 1) HD2 (AV = 2) -100 HD3 (AV = 1) HD 3 (AV = 2) VS = ±5V, RLD = 1k, VOP-P, DM = 1V for AV = 1, VOP-P, DM = 2V for AV = 2 10ns/DIV 50mV/DIVFN7307 Rev 9.00 Page 8 of 15 August 14, 2015

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EL5171, EL5371FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 22. ENABLED RESPONSE FIGURE 23. DISABLED RESPONSE FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Typical Performance Curves (Continued) 10ns/DIV 0.5V/DIV CH1 CH2 100ns/DIV M = 100ns, CH1 = 500mV/DIV, CH2 = 5V/DIV CH1 CH2 200ns/DIV M = 200ns, CH1 = 500mV/DIV, CH2 = 5V/DIV 1.2 1.0 0.8 0.6 0.4 0 0 25 50 75 100 150 AMBIENT TEMPERATURE (°C) P O W E R D IS S IP A T IO N ( W ) 12585 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.2 625mW JA = +160°C/W SO8 1.010W JA =+99°C/W QSOP28 1.4 1.2 1.0 0.8 0.6 0.2 0 0 25 50 75 100 150 AMBIENT TEMPERATURE (°C) P O W E R D IS S IP A T IO N ( W ) 12585 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.4 909mW JA = +110°C/W SO8 1.266W JA = +79°C/W QSOP28FN7307 Rev 9.00 Page 9 of 15 August 14, 2015

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EL5171, EL5371Simplified Schematic Description of Operation and Application Information Product Description The EL5171 and EL5371 are wide bandwidth, low power and single-ended to differential output amplifiers. The EL5171 is a single channel differential amplifier. Since the IN- pin and REF pin are tied together internally, the EL5171 can be used as a single-ended to differential converter. The EL5371 is a triple channel differential amplifier. The EL5371 has a separate IN- pin and REF pin for each channel. It can be used as a single/differential ended to differential converter. The EL5171 and EL5371 are internally compensated for closed loop gain of +1 or greater. Connected in gain of 1 and driving a 1k differential load, the EL5171 and EL5371 have a -3dB bandwidth of 250MHz. Driving a 200 differential load at gain of 2, the bandwidth is about 30MHz. The EL5371 is available with a power-down feature to reduce the power while the amplifier is disabled. Input, Output, and Supply Voltage Range The EL5171 and EL5371 have been designed to operate with a single supply voltage of 5V to 10V or split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.5V to 3.4V for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.8V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to become distorted. The output of the EL5171 and EL5371 can swing from -3.9V to +3.9V at 1k differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. Differential and Common Mode Gain Settings For EL5171, since the IN- pin and REF pin are bound together as the REF pin in an 8 Ld package, the signal at the REF pin is part of the common mode signal and also part of the differential mode signal. For the true balance differential outputs, the REF pin must be tied to the same bias level as the IN+ pin. For a ±5V supply, just tie the REF pin to GND if the IN+ pin is biased at 0V with a 50 or 75 termination resistor. For a single supply application, if the IN+ is biased to half of the rail, the REF pin should be biased to half of the rail also. The gain setting for EL5171 is expressed in Equation 1: Where: • VREF = 0V • RF1 = RF2 = RF The EL5371 has a separate IN- pin and REF pin. It can be used as a single/differential ended to differential converter. The voltage applied at REF pin can set the output common mode voltage and the gain is one. The gain setting for EL5371 is expressed in Equation 2: Where: • RF1 = RF2 = RF REF R10R9 RCD RCD OUT+ OUT- CC R6R5 CC R4R3 R7 R8 R2R1 VB1FBNFBPIN-IN+ VB2 VS+ VS- VODM VIN+ 1 RF1 RF2+ RG ---------------------------+       = VODM VIN+ 1 2RF RG ----------+       = (EQ. 1) VOCM VREF 0V== VODM VIN + VIN-  1 RF1 RF2+ RG ---------------------------+       –= VODM VIN + VIN-  1 2RF RG ----------+       –= (EQ. 2) VOCM VREF=FN7307 Rev 9.00 Page 10 of 15 August 14, 2015

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EL5171, EL5371FIGURE 26. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the OUT+ pin to the FBP pin and the OUT- pin to the FBN pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL5171 and EL5371 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 500 to 1k. The EL5171 and EL5371 have a gain bandwidth product of 100MHz for RLD = 1k. For gains 5, their bandwidth can be predicted by Equation 3: Driving Capacitive Loads and Cables The EL5171 and EL5371 can drive 50pF differential capacitor in parallel with 1k differential load with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss, which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down (for EL5371 only) The EL5371 can be disabled and its outputs placed in a high impedance state. The turn-off time is about 0.95µs and the turn-on time is about 215ns. When disabled, the amplifier's supply current is reduced to 1.7µA for IS+ and 120µA for IS- typically, thereby effectively eliminating the power consumption. The amplifier's power-down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to the VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at the EN pin is above VS+ - 0.5V. Output Drive Capability The EL5171 and EL5371 have internal short circuit protection. Its typical short circuit current is ±90mA for EL5171 and ±70mA for EL5371. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±60mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL5171 and EL5371, it is possible to exceed the +135°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 4: Where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or as represented in Equation 5: Where: VSTOT = Total supply voltage = VS+ - VS- ISMAX = Maximum quiescent supply current per channel VO = Maximum differential output voltage of the application RLD = Differential load resistance VO+ FBP RG RF2 IN+ IN- REF FBN VIN+ VIN- VREF RF1 VO- Gain BW 100MHz= (EQ. 3) PDMAX TJMAX TAMAX– JA --------------------------------------------= (EQ. 4) (EQ. 5)PD i VSTOT ISMAX V STOT VO – VO RLD -----------+       =FN7307 Rev 9.00 Page 11 of 15 August 14, 2015

Page 13

EL5171, EL5371ILOAD = Load current i = Number of channels By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided, if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side. Typical Applications FIGURE 27. TWISTED PAIR CABLE RECEIVER FIGURE 28. TRANSMIT EQUALIZER FBP RG RF IN+ IN- REF FBN RF RFR RGR IN+ IN- REF EL5172/ EL5372 EL5171/ EL5371 VO 50 50 RT TWISTED PAIR ZO = 100 VO+ FBP RF IN+ IN- REF FBN RF VO- RG RT RGC CL 75 fL fH FREQUENCY GAIN (dB) fH 1 2RGCCC ---------------------------- fL 1 2RGCC ------------------------DC Gain 1 2RF RG ----------+= HF Gain 1 2RF RG RGC --------------------------+=FN7307 Rev 9.00 Page 12 of 15 August 14, 2015

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EL5171, EL5371About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 14, 2015 FN7307.9 Updated the Ordering Information table on page 2. Added Revision History and About Intersil Sections.FN7307 Rev 9.00 Page 13 of 15 August 14, 2015

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EL5171, EL5371 FN7307 Rev 9.00 Page 14 of 15 August 14, 2015 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 Unless otherwise specified, tolerance : Decimal ± 0.05 The pin #1 identifier may be either a mold or mark feature. Interlead flash or protrusions shall not exceed 0.25mm per side. Dimension does not include interlead flash or protrusions. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. 5. 4. 2. Dimensions are in millimeters.1. NOTES: DETAIL "A" SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN TOP VIEW A B 4 4 0.25 AM C B C 0.10 C 5 ID MARK PIN NO.1 (0.35) x 45° SEATING PLANE GAUGE PLANE 0.25 (5.40) (1.50) 4.90 ± 0.10 3.90 ± 0.10 1.27 0.43 ± 0.076 0.63 ±0.23 4° ± 4° DETAIL "A" 0.22 ± 0.03 0.175 ± 0.075 1.45 ± 0.1 1.75 MAX (1.27) (0.60) 6.0 ± 0.20 Reference to JEDEC MS-012.6. SIDE VIEW “B”

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