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Part Number EP1C6T144C8N
Manufacturer Intel
Description IC FPGA 98 I/O 144TQFP
Datasheet EP1C6T144C8N Datasheet
Package 144-LQFP
In Stock 3,336 piece(s)
Unit Price $ 20.1200 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 21 - Sep 26 (Choose Expedited Shipping)
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Part Number # EP1C6T144C8N (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Intel and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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EP1C6T144C8N Specifications

CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet EP1C6T144C8NDatasheet
Number of LABs/CLBs598
Number of Logic Elements/Cells5980
Total RAM Bits92160
Number of I/O98
Number of Gates-
Voltage - Supply1.425 V ~ 1.575 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 85°C (TJ)
Package / Case144-LQFP
Supplier Device Package144-TQFP (20x20)

EP1C6T144C8N Datasheet

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Altera Corporation Section I–1 Preliminary Section I. Cyclone FPGA Family Data Sheet This section provides designers with the data sheet specifications for Cyclone® devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices. This section contains the following chapters: ■ Chapter 1. Introduction ■ Chapter 2. Cyclone Architecture ■ Chapter 3. Configuration and Testing ■ Chapter 4. DC and Switching Characteristics ■ Chapter 5. Reference and Ordering Information Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook.

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Section I–2 Altera Corporation Preliminary Revision History Cyclone Device Handbook, Volume 1

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Altera Corporation 1–1 May 2008 Preliminary 1. Introduction Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. Features The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions. Table 1–1. Cyclone Device Features (Part 1 of 2) Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 LEs 2,910 4,000 5,980 12,060 20,060 M4K RAM blocks (128 × 36 bits) 13 17 20 52 64 C51001-1.5

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1–2 Altera Corporation Preliminary May 2008 Cyclone Device Handbook, Volume 1 Cyclone devices are available in quad flat pack (QFP) and space-saving FineLine® BGA packages (see Tables 1–2 through 1–3). Vertical migration means you can migrate a design from one device to another that has the same dedicated pins, JTAG pins, and power pins, and are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must use the layout for the largest planned density in a package to provide the necessary power pins for migration. For I/O pin migration across densities, cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins can be migrated. The Quartus® II software can automatically cross-reference and place all pins for you when given a device migration list. If one device has power or ground pins, but these same pins are user I/O on a different device that is in the migration path,the Quartus II software ensures the pins are not used as user I/O in the Quartus II software. Ensure that these pins are connected Total RAM bits 59,904 78,336 92,160 239,616 294,912 PLLs 1 2 2 2 2 Maximum user I/O pins (1) 104 301 185 249 301 Note to Table 1–1: (1) This parameter includes global clock pins. Table 1–1. Cyclone Device Features (Part 2 of 2) Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Table 1–2. Cyclone Package Options and I/O Pin Counts Device 100-Pin TQFP (1) 144-Pin TQFP (1), (2) 240-Pin PQFP (1) 256-Pin FineLine BGA 324-Pin FineLine BGA 400-Pin FineLine BGA EP1C3 65 104 — — — — EP1C4 — — — — 249 301 EP1C6 — 98 185 185 — — EP1C12 — — 173 185 249 — EP1C20 — — — — 233 301 Notes to Table 1–2: (1) TQFP: thin quad flat pack. PQFP: plastic quad flat pack. (2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).

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Altera Corporation 1–3 May 2008 Preliminary Document Revision History to the appropriate plane on the board. The Quartus II software reserves I/O pins as power pins as necessary for layout with the larger densities in the same package having more power pins. Document Revision History Table 1–4 shows the revision history for this document. Table 1–3. Cyclone QFP and FineLine BGA Package Sizes Dimension 100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin FineLine BGA 324-Pin FineLine BGA 400-Pin FineLine BGA Pitch (mm) 0.5 0.5 0.5 1.0 1.0 1.0 Area (mm2) 256 484 1,024 289 361 441 Length × width (mm × mm) 16×16 22×22 34.6×34.6 17×17 19×19 21×21 Table 1–4. Document Revision History Date and Document Version Changes Made Summary of Changes May 2008 v1.5 Minor textual and style changes. — January 2007 v1.4 Added document revision history. — August 2005 v1.3 Minor updates. — October 2003 v1.2 Added 64-bit PCI support information. — September 2003 v1.1 ● Updated LVDS data rates to 640 Mbps from 311 Mbps. ● Updated RSDS feature information. — May 2003 v1.0 Added document to Cyclone Device Handbook. —

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1–4 Altera Corporation Preliminary May 2008 Cyclone Device Handbook, Volume 1

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Altera Corporation 2–1 May 2008 Preliminary 2. Cyclone Architecture Functional Description Cyclone® devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs. M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM. Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps). Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support. Figure 2–1 shows a diagram of the Cyclone EP1C12 device. C51002-1.6

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2–2 Altera Corporation Preliminary May 2008 Cyclone Device Handbook, Volume 1 Figure 2–1. Cyclone EP1C12 Device Block Diagram The number of M4K RAM blocks, PLLs, rows, and columns vary per device. Table 2–1 lists the resources available in each Cyclone device. Logic Array PLL IOEs M4K Blocks EP1C12 Device Table 2–1. Cyclone Device Resources Device M4K RAM PLLs LAB Columns LAB Rows Columns Blocks EP1C3 1 13 1 24 13 EP1C4 1 17 2 26 17 EP1C6 1 20 2 32 20 EP1C12 2 52 2 48 26 EP1C20 2 64 2 64 32

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Altera Corporation 2–3 May 2008 Preliminary Logic Array Blocks Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within a LAB. The Quartus® II Compiler places associated logic within a LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2–2 details the Cyclone LAB. Figure 2–2. Cyclone LAB Structure LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive a LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher Direct link interconnect from adjacent block Direct link interconnect to adjacent block Row Interconnect Column Interconnect Local InterconnectLAB Direct link interconnect from adjacent block Direct link interconnect to adjacent block

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August 7, 2020

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July 28, 2020

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July 28, 2020

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July 24, 2020

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July 10, 2020

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