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EP4SE530F43I3N

hotEP4SE530F43I3N

EP4SE530F43I3N

For Reference Only

Part Number EP4SE530F43I3N
Manufacturer Altera
Description IC FPGA 1120 I/O 1760FBGA
Datasheet EP4SE530F43I3NDatasheet
Package 1760-BBGA, FCBGA
In Stock 347 piece(s)
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EP4SE530F43I3NSpecifications

ManufacturerAltera
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet EP4SE530F43I3NDatasheet
Package1760-BBGA, FCBGA
SeriesSTRATIX? IV E
Number of LABs/CLBs21248
Number of Logic Elements/Cells531200
Total RAM Bits28033024
Number of I/O1120
Voltage - Supply0.87 V ~ 0.93 V
Mounting TypeSurface Mount
Operating Temperature-40°C ~ 100°C (TJ)
Package / Case1760-BBGA, FCBGA
Supplier Device Package1760-FCBGA (42.5x42.5)

EP4SE530F43I3NDatasheet

Page 1

Page 2

SIV51001-3.5 © 2016 Altera Corporation. All rights reserved. ALTERA, ARRI are trademarks of Altera Corporation and registered in the U.S trademarks or service marks are the property of their respectiv semiconductor products to current specifications in accordance services at any time without notice. Altera assumes no respons described herein except as expressly agreed to in writing by Al on any published information and before placing orders for pr Stratix IV Device Handbook Volume 1 January 2016 January 2016 SIV51001-3.51. Overview for the Stratix IV Device FamilyAltera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements. The Stratix IV device family contains three optimized variants to meet different application requirements: ■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits (Kb) RAM, and 1,288 18 x 18 bit multipliers ■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps ■ Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps The complete Altera high-end solution includes the lowest risk, lowest total cost path to volume using HardCopy® IV ASICs for all the family variants, a comprehensive portfolio of application solutions customized for end-markets, and the industry leading Quartus® II software to increase productivity and performance. f For information about upcoming Stratix IV device features, refer to the Upcoming Stratix IV Device Features document. f For information about changes to the currently published Stratix IV Device Handbook, refer to the Addendum to the Stratix IV Device Handbook chapter. This chapter contains the following sections: ■ “Feature Summary” on page 1–2 ■ “Architecture Features” on page 1–6 ■ “Integrated Software Platform” on page 1–19 ■ “Ordering Information” on page 1–19A, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos . Patent and Trademark Office and in other countries. All other words and logos identified as e holders as described at www.altera.com/common/legal.html. Altera warrants performance of its with Altera's standard warranty, but reserves the right to make changes to any products and ibility or liability arising out of the application or use of any information, product, or service tera. Altera customers are advised to obtain the latest version of device specifications before relying oducts or services. Feedback Subscribe ISO 9001:2008 Registered

Page 3

1–2 Chapter 1: Overview for the Stratix IV Device Family Feature SummaryFeature Summary The following list summarizes the Stratix IV device family features: ■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively ■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken ■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality f For more information, refer to the IP Compiler for PCI Express User Guide. ■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium ■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel ■ 72,600 to 813,050 equivalent LEs per device ■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers ■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz ■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device ■ Programmable power technology that minimizes power while maximizing device performance ■ Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards ■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks ■ High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps ■ Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1 ■ Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impactStratix IV Device Handbook January 2016 Altera Corporation Volume 1

Page 4

Chapter 1: Overview for the Stratix IV Device Family 1–3 Feature SummaryStratix IV GX Devices Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels per device: ■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support data rates between 600 Mbps and 8.5 Gbps ■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps 1 The actual number of transceiver channels per device varies with device selection. For more information about the exact transceiver count in each device, refer to Table 1–1 on page 1–11. 1 For more information about transceiver architecture, refer to the Transceiver Architecture in Stratix IV Devices chapter. Figure 1–1 shows a high-level Stratix IV GX chip view. Figure 1–1. Stratix IV GX Chip View (1) Note to Figure 1–1: (1) Resource counts vary with device selection, package selection, or both. General Purpose I/O and Memory Interface 600 Mbps-8.5 Gbps CDR-based Transceiver General Purpose I/O and 150 Mbps-1.6 Gbps LVDS interface with DPA and Soft-CDR T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k P C I E x p re s s H a rd I P B lo c k P C I E x p re s s H a rd I P B lo c k P C I E x p re s s H a rd I P B lo c k P C I E x p re s s H a rd I P B lo c k General Purpose I/O and Memory Interface PLL PLL PLL PLL PLL PLL General Purpose I/O and Memory Interface General Purpose I/O and Memory Interface PLL PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) Transceiver Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d LV D S I /O w it h D P A a n d S o ft C D R PLL PLL PLL PLL T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d LV D S I /O w it h D P A a n d S o ft C D R G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d LV D S I /O w it h D P A a n d S o ft C D R G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d LV D S I /O w it h D P A a n d S o ft C D R January 2016 Altera Corporation Stratix IV Device Handbook Volume 1

Page 5

1–4 Chapter 1: Overview for the Stratix IV Device Family Feature SummaryStratix IV E Device Stratix IV E devices provide an excellent solution for applications that do not require high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive. Figure 1–2 shows a high-level Stratix IV E chip view. Figure 1–2. Stratix IV E Chip View (1) Note to Figure 1–2: (1) Resource counts vary with device selection, package selection, or both. General Purpose I/O and Memory Interface General Purpose I/O and 150 Mbps-1.6 Gbps LVDS interface with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and Memory Interface PLL PLL PLL PLL PLL PLL PLL PLL PLL PLL General Purpose I/O and Memory Interface General Purpose I/O and Memory Interface PLL PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDR General Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDRStratix IV Device Handbook January 2016 Altera Corporation Volume 1

Page 6

Chapter 1: Overview for the Stratix IV Device Family 1–5 Feature SummaryStratix IV GT Devices Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device: ■ Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps ■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps 1 The actual number of transceiver channels per device varies with device selection. For more information about the exact transceiver count in each device, refer to Table 1–7 on page 1–16. 1 For more information about Stratix IV GT devices and transceiver architecture, refer to the Transceiver Architecture in Stratix IV Devices chapter. Figure 1–3 shows a high-level Stratix IV GT chip view. Figure 1–3. Stratix IV GT Chip View (1) Note to Figure 1–3: (1) Resource counts vary with device selection, package selection, or both. General Purpose I/O and Memory Interface 600 Mbps-11.3 Gbps CDR-based Transceiver General Purpose I/O and up to 1.6 Gbps LVDS interface with DPA and Soft-CDR P C I E x p re s s H a rd I P B lo c k P C I E x p re s s H a rd I P B lo c k P C I E x p re s s H a rd I P B lo c k P C I E x p re s s H a rd I P B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k General Purpose I/O and Memory Interface PLL PLL PLL PLL PLL PLL General Purpose I/O and Memory Interface General Purpose I/O and Memory Interface PLL PLL FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) Transceiver Block General Purpose I/O and High-Speed LVDS I/O with DPA and Soft CDR G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d L V D S I /O w it h D P A a n d S o ft C D R PLL PLL PLL PLL G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d L V D S I /O w it h D P A a n d S o ft C D R G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d L V D S I /O w it h D P A a n d S o ft C D R G e n e ra l P u rp o s e I/ O a n d H ig h -S p e e d L V D S I /O w it h D P A a n d S o ft C D R T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k T ra n s c e iv e r B lo c k January 2016 Altera Corporation Stratix IV Device Handbook Volume 1

Page 7

1–6 Chapter 1: Overview for the Stratix IV Device Family Architecture FeaturesArchitecture Features The Stratix IV device family features are divided into high-speed transceiver features and FPGA fabric and I/O features. 1 The high-speed transceiver features apply only to Stratix IV GX and Stratix IV GT devices. High-Speed Transceiver Features The following sections describe high-speed transceiver features for Stratix IV GX and GT devices. Highest Aggregate Data Bandwidth Up to 48 full-duplex transceiver channels supporting data rates up to 8.5 Gbps in Stratix IV GX devices and up to 11.3 Gbps in Stratix IV GT devices. Wide Range of Protocol Support Physical layer support for the following serial protocols: ■ Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON, SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken ■ Stratix IV GT—40G/100G Ethernet, SFI-S, Interlaken, SFI-5.1, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, 3G-SDI, and Fibre Channel ■ Extremely flexible and easy-to-configure transceiver data path to implement proprietary protocols ■ PCIe Support ■ Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCI Express base specification 2.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks f For more information, refer to the PCI Express Compiler User Guide. ■ Root complex and end-point applications ■ x1, x4, and x8 lane configurations ■ PIPE 2.0-compliant interface ■ Embedded circuitry to switch between Gen1 and Gen2 data rates ■ Built-in circuitry for electrical idle generation and detection, receiver detect, power state transitions, lane reversal, and polarity inversion ■ 8B/10B encoder and decoder, receiver synchronization state machine, and ± 300 parts per million (ppm) clock compensation circuitry ■ Transaction layer support for up to two virtual channels (VCs) Stratix IV Device Handbook January 2016 Altera Corporation Volume 1

Page 8

Chapter 1: Overview for the Stratix IV Device Family 1–7 Architecture Features■ XAUI/HiGig Support ■ Compliant to IEEE802.3ae specification ■ Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from idle ordered sets (||A||, ||K||, ||R||) at the transmitter and receiver, respectively ■ 8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and ± 100 ppm clock compensation circuitry ■ GbE Support ■ Compliant to IEEE802.3-2005 specification ■ Automatic idle ordered set (/I1/, /I2/) generation at the transmitter, depending on the current running disparity ■ 8B/10B encoder and decoder, receiver synchronization state machine, and ± 100 ppm clock compensation circuitry ■ Support for other protocol features such as MSB-to-LSB transmission in SONET/SDH configuration and spread-spectrum clocking in PCIe configurations Diagnostic Features ■ Serial loopback from the transmitter serializer to the receiver CDR for transceiver PCS and PMA diagnostics ■ Reverse serial loopback pre- and post-CDR to transmitter buffer for physical link diagnostics ■ Loopback master and slave capability in PCI Express hard IP blocks f For more information, refer to the PCI Express Compiler User Guide. Signal Integrity Stratix IV devices simplify the challenge of signal integrity through a number of chip, package, and board-level enhancements to enable efficient high-speed data transfer into and out of the device. These enhancements include: ■ Programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis levels to compensate for pre-cursor and post-cursor inter-symbol interference (ISI) ■ Up to 900% boost capability on the first pre-emphasis post-tap ■ User-controlled and adaptive 4-stage receiver equalization with up to 16 dB of high-frequency gain ■ On-die power supply regulators for transmitter and receiver phase-locked loop (PLL) charge pump and voltage controlled oscillator (VCO) for superior noise immunity ■ On-package and on-chip power supply decoupling to satisfy transient current requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors ■ Calibration circuitry for transmitter and receiver on-chip termination (OCT) resistorsJanuary 2016 Altera Corporation Stratix IV Device Handbook Volume 1

Page 9

1–8 Chapter 1: Overview for the Stratix IV Device Family Architecture FeaturesFPGA Fabric and I/O Features The following sections describe the Stratix IV FPGA fabric and I/O features. Device Core Features ■ Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in Stratix IV E devices, efficiently packed in unique and innovative adaptive logic modules (ALMs) ■ Ten ALMs per logic array block (LAB) deliver faster performance, improved logic utilization, and optimized routing ■ Programmable power technology, including a variety of process, circuit, and architecture optimizations and innovations ■ Programmable power technology available to select power-driven compilation options for reduced static power consumption Embedded Memory ■ TriMatrix embedded memory architecture provides three different memory block sizes to efficiently address the needs of diversified FPGA designs: ■ 640-bit MLAB ■ 9-Kb M9K ■ 144-Kb M144K ■ Up to 33,294 Kb of embedded memory operating at up to 600 MHz ■ Each memory block is independently configurable to be a single- or dual-port RAM, FIFO, ROM, or shift register Digital Signal Processing (DSP) Blocks ■ Flexible DSP blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz with rounding and saturation capabilities ■ Faster operation due to fully pipelined architecture and built-in addition, subtraction, and accumulation units to combine multiplication results ■ Optimally designed to support advanced features such as adaptive filtering, barrel shifters, and finite and infinite impulse response (FIR and IIR) filters Clock Networks ■ Up to 16 global clocks and 88 regional clocks optimally routed to meet the maximum performance of 800 MHz ■ Up to 112 and 132 periphery clocks in Stratix IV GX and Stratix IV E devices, respectively ■ Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in Stratix IV GX and Stratix IV GT devices ■ Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in Stratix IV E devicesStratix IV Device Handbook January 2016 Altera Corporation Volume 1

Page 10

Chapter 1: Overview for the Stratix IV Device Family 1–9 Architecture FeaturesPLLs ■ Three to 12 PLLs per device supporting spread-spectrum input tracking, programmable bandwidth, clock switchover, dynamic reconfiguration, and delay compensation ■ On-chip PLL power supply regulators to minimize noise coupling I/O Features ■ Sixteen to 24 modular I/O banks per device with 24 to 48 I/Os per bank designed and packaged for optimal simultaneous switching noise (SSN) performance and migration capability ■ Support for a wide range of industry I/O standards, including single-ended (LVTTL/CMOS/PCI/PCIX), differential (LVDS/mini-LVDS/RSDS), voltage-referenced single-ended and differential (SSTL/HSTL Class I/II) I/O standards ■ On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration for single-ended I/Os and on-chip differential (RD) termination for differential I/Os ■ Programmable output drive strength, slew rate control, bus hold, and weak pull-up capability for single-ended I/Os ■ User I/O:GND:VCC ratio of 8:1:1 to reduce loop inductance in the package—PCB interface ■ Programmable transmitter differential output voltage (VOD) and pre-emphasis for high-speed LVDS I/O High-Speed Differential I/O with DPA and Soft-CDR ■ Dedicated circuitry on the left and right sides of the device to support differential links at data rates from 150 Mbps to 1.6 Gbps ■ Up to 98 differential SERDES in Stratix IV GX devices, up to 132 differential SERDES in Stratix IV E devices, and up to 47 differential SERDES in Stratix IV GT devices ■ DPA circuitry at the receiver automatically compensates for channel-to-channel and channel-to-clock skew in source synchronous interfaces ■ Soft-CDR circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clocks at up to 1.6 Gbps data rate (SGMII and GbE) External Memory Interfaces ■ Support for existing and emerging memory interface standards such as DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM, QDRII+ SRAM, and RLDRAM II ■ DDR3 up to 1,067 Mbps/533 MHz ■ Programmable DQ group widths of 4 to 36 bits (includes parity bits) ■ Dynamic OCT, trace mismatch compensation, read-write leveling, and half-rate register capabilities provide a robust external memory interface solutionJanuary 2016 Altera Corporation Stratix IV Device Handbook Volume 1

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February 20, 2020

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December 26, 2019

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