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hot EPF10K30AQC208-2N


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Part Number EPF10K30AQC208-2N
Manufacturer Altera
Description IC FPGA 147 I/O 208QFP
Datasheet EPF10K30AQC208-2N Datasheet
Package 208-BQFP
In Stock 344 piece(s)
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EPF10K30AQC208-2N Specifications

CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet EPF10K30AQC208-2N Datasheet
Number of LABs/CLBs216
Number of Logic Elements/Cells1728
Total RAM Bits12288
Number of I/O147
Number of Gates69000
Voltage - Supply3 V ~ 3.6 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 70°C (TA)
Package / Case208-BQFP
Supplier Device Package208-QFP (28x28)

EPF10K30AQC208-2N Datasheet

Page 1

Page 2

FLEX 10K Embedded Programmable Logic Device Family January 2003, ver. 4.2 Data Sheet ® Includes FLEX 10KAFeatures... ■ The industry’s first embedded programmable logic device (PLD) family, providing System-on-a-Programmable-Chip (SOPC) integration – Embedded array for implementing megafunctions, such as efficient memory and specialized logic functions – Logic array for general logic functions ■ High density – 10,000 to 250,000 typical gates (see Tables 1 and 2) – Up to 40,960 RAM bits; 2,048 bits per embedded array block (EAB), all of which can be used without reducing logic capacity ■ System-level features – MultiVoltTM I/O interface support – 5.0-V tolerant input pins in FLEX® 10KA devices – Low power consumption (typical specification less than 0.5 mA in standby mode for most devices) – FLEX 10K and FLEX 10KA devices support peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 – FLEX 10KA devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3-V PCI compliance – Select FLEX 10KA devices support 5.0-V PCI buses with eight or fewer loads – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming any device logic Table 1. FLEX 10K Device Features Feature EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K40 EPF10K50 EPF10K50V Typical gates (logic and RAM) (1) 10,000 20,000 30,000 40,000 50,000 Maximum system gates 31,000 63,000 69,000 93,000 116,000 Logic elements (LEs) 576 1,152 1,728 2,304 2,880 Logic array blocks (LABs) 72 144 216 288 360 Embedded array blocks (EABs) 3 6 6 8 10 Total RAM bits 6,144 12,288 12,288 16,384 20,480 Maximum user I/O pins 150 189 246 189 310Altera Corporation 1 DS-F10K-4.2

Page 3

FLEX 10K Embedded Programmable Logic Device Family Data SheetNote to tables: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. ...and More Features – Devices are fabricated on advanced processes and operate with a 3.3-V or 5.0-V supply voltage (see Table 3 – In-circuit reconfigurability (ICR) via external configuration device, intelligent controller, or JTAG port – ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication – Built-in low-skew clock distribution trees – 100% functional testing of all devices; test vectors or scan chains are not required Table 2. FLEX 10K Device Features Feature EPF10K70 EPF10K100 EPF10K100A EPF10K130V EPF10K250A Typical gates (logic and RAM) (1) 70,000 100,000 130,000 250,000 Maximum system gates 118,000 158,000 211,000 310,000 LEs 3,744 4,992 6,656 12,160 LABs 468 624 832 1,520 EABs 9 12 16 20 Total RAM bits 18,432 24,576 32,768 40,960 Maximum user I/O pins 358 406 470 470 Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices 5.0-V Devices 3.3-V Devices EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 EPF10K10A EPF10K30A EPF10K50V EPF10K100A EPF10K130V EPF10K250A2 Altera Corporation

Page 4

FLEX 10K Embedded Programmable Logic Device Family Data SheetAltera Corporation 3 ■ Flexible interconnect – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state buses – Up to six global clock signals and four global clear signals ■ Powerful I/O pins – Individual tri-state output enable control for each pin – Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise – FLEX 10KA devices support hot-socketing ■ Peripheral register for fast setup and clock-to-output delay ■ Flexible package options – Available in a variety of packages with 84 to 600 pins (see Tables 4 and 5) – Pin-compatibility with other FLEX 10K devices in the same package – FineLine BGATM packages maximize board space efficiency ■ Software design support and automatic place-and-route provided by Altera development systems for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic

Page 5

FLEX 10K Embedded Programmable Logic Device Family Data SheetTable 4. FLEX 10K Package Options & I/O Pin Count Note (1) Device 84-Pin PLCC 100-Pin TQFP 144-Pin TQFP 208-Pin PQFP RQFP 240-Pin PQFP RQFP EPF10K10 59 102 134 EPF10K10A 66 102 134 EPF10K20 102 147 189 EPF10K30 147 189 EPF10K30A 102 147 189 EPF10K40 147 189 EPF10K50 189 EPF10K50V 189 EPF10K70 189 EPF10K100 EPF10K100A 189 EPF10K130V EPF10K250A Table 5. FLEX 10K Package Options & I/O Pin Count (Continued) Note (1) Device 503-Pin PGA 599-Pin PGA 256-Pin FineLine BGA 356-Pin BGA 484-Pin FineLine BGA 600-Pin BGA 403-Pin PGA EPF10K10 EPF10K10A 150 150 (2) EPF10K20 EPF10K30 246 EPF10K30A 191 246 246 EPF10K40 EPF10K50 274 310 EPF10K50V 274 EPF10K70 358 EPF10K100 406 EPF10K100A 274 369 406 EPF10K130V 470 470 EPF10K250A 470 4704 Altera Corporation

Page 6

FLEX 10K Embedded Programmable Logic Device Family Data SheetNotes to tables: (1) FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA), and FineLine BGATM packages. (2) This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set. General Description Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based on reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates all features necessary to implement common gate array megafunctions. With up to 250,000 gates, the FLEX 10K family provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. FLEX 10K devices are reconfigurable, which allows 100% testing prior to shipment. As a result, the designer is not required to generate test vectors for fault coverage purposes. Additionally, the designer does not need to manage inventories of different ASIC designs; FLEX 10K devices can be configured on the board for the specific functionality required. Table 6 shows FLEX 10K performance for some common designs. All performance values were obtained with Synopsys DesignWare or LPM functions. No special design technique was required to implement the applications; the designer simply inferred or instantiated a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Notes: (1) The speed grade of this application is limited because of clock high and low specifications. (2) This application uses combinatorial inputs and outputs. (3) This application uses registered inputs and outputs. Table 6. FLEX 10K & FLEX 10KA Performance Application Resources Used Performance Units LEs EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade 16-bit loadable counter (1) 16 0 204 166 125 95 MHz 16-bit accumulator (1) 16 0 204 166 125 95 MHz 16-to-1 multiplexer (2) 10 0 4.2 5.8 6.0 7.0 ns 256 × 8 RAM read cycle speed (3) 0 1 172 145 108 84 MHz 256 × 8 RAM write cycle speed (3) 0 1 106 89 68 63 MHzAltera Corporation 5

Page 7

FLEX 10K Embedded Programmable Logic Device Family Data SheetThe FLEX 10K architecture is similar to that of embedded gate arrays, the fastest-growing segment of the gate array market. As with standard gate arrays, embedded gate arrays implement general logic in a conventional “sea-of-gates” architecture. In addition, embedded gate arrays have dedicated die areas for implementing large, specialized functions. By embedding functions in silicon, embedded gate arrays provide reduced die area and increased speed compared to standard gate arrays. However, embedded megafunctions typically cannot be customized, limiting the designer’s options. In contrast, FLEX 10K devices are programmable, providing the designer with full control over embedded megafunctions and general logic while facilitating iterative design changes during debugging. Each FLEX 10K device contains an embedded array and a logic array. The embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (DSP), microcontroller, wide-data-path manipulation, and data-transformation functions. The logic array performs the same function as the sea-of-gates in the gate array: it is used to implement general logic, such as counters, adders, state machines, and multiplexers. The combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device. FLEX 10K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers the EPC1, EPC2, EPC16, and EPC1441 configuration devices, which configure FLEX 10K devices via a serial data stream. Configuration data can also be downloaded from system RAM or from Altera’s BitBlasterTM serial download cable or ByteBlasterMVTM parallel port download cable. After a FLEX 10K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 320 ms, real-time changes can be made during system operation. FLEX 10K devices contain an optimized interface that permits microprocessors to configure FLEX 10K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat a FLEX 10K device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to reconfigure the device.6 Altera Corporation

Page 8

FLEX 10K Embedded Programmable Logic Device Family Data Sheetf For more information, see the following documents: ■ Configuration Devices for APEX & FLEX Devices Data Sheet ■ BitBlaster Serial Download Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■ Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices) FLEX 10K devices are supported by Altera development systems; single, integrated packages that offer schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use device- specific features such as carry chains which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development systems include DesignWare functions that are optimized for the FLEX 10K architecture. The Altera development systems run on Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations. f See the MAX+PLUS II Programmable Logic Development System & Software Data Sheet for more information. Functional Description Each FLEX 10K device contains an embedded array to implement memory and specialized logic functions, and a logic array to implement general logic. The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 2,048 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions, such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions. Altera Corporation 7

Page 9

FLEX 10K Embedded Programmable Logic Device Family Data SheetThe logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect. An LE consists of a 4-input look-up table (LUT), a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic—8-bit counters, address decoders, or state machines—or combined across LABs to create larger logic blocks. Each LAB represents about 96 usable gates of logic. Signal interconnections within FLEX 10K devices and to and from device pins are provided by the FastTrack Interconnect, a series of fast, continuous row and column channels that run the entire length and width of the device. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 1.6 ns and hold times of 0 ns; as outputs, these registers provide clock-to-output times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. Figure 1 shows a block diagram of the FLEX 10K architecture. Each group of LEs is combined into an LAB; LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each row and column of the FastTrack Interconnect.8 Altera Corporation

Page 10

FLEX 10K Embedded Programmable Logic Device Family Data SheetFigure 1. FLEX 10K Device Block Diagram FLEX 10K devices provide six dedicated inputs that drive the flipflops’ control inputs to ensure the efficient distribution of high-speed, low-skew (less than 1.5 ns) control signals. These signals use dedicated routing channels that provide shorter delays and lower skews than the FastTrack Interconnect. Four of the dedicated inputs drive four global signals. These four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or an internally generated asynchronous clear signal that clears many registers in the device. Embedded Array Block The EAB is a flexible block of RAM with registers on the input and output ports, and is used to implement common gate array megafunctions. The EAB is also suitable for functions such as multipliers, vector scalars, and error correction circuits, because it is large and flexible. These functions can be combined in applications such as digital filters and microcontrollers. I/O Element (IOE) Logic Array Block (LAB) Row Interconnect IOEIOE IOEIOE IOE IOE IOE Local Interconnect IOEIOE IOEIOE IOEIOE IOEIOE IOEIOE Logic Element (LE) Column Interconnect IOE EAB EAB Logic Array IOEIOE IOEIOE IOEIOE Embedded Array Block (EAB) Embedded Array IOE IOE Logic Array IOE IOEAltera Corporation 9

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