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EPF10K50SFC256-3

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EPF10K50SFC256-3

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Part Number EPF10K50SFC256-3
Manufacturer Altera
Description IC FPGA 191 I/O 256FBGA
Datasheet EPF10K50SFC256-3 Datasheet
Package 256-BGA
In Stock 385 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # EPF10K50SFC256-3 (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Altera and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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EPF10K50SFC256-3 Specifications

ManufacturerAltera
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet EPF10K50SFC256-3Datasheet
Package256-BGA
SeriesFLEX-10KS?
Number of LABs/CLBs360
Number of Logic Elements/Cells2880
Total RAM Bits40960
Number of I/O191
Number of Gates199000
Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 70°C (TA)
Package / Case256-BGA
Supplier Device Package256-FBGA (17x17)

EPF10K50SFC256-3 Datasheet

Page 1

Page 2

FLEX 10KE Embedded Programmable Logic Device January 2003, ver. 2.5 Data Sheet ® Altera Corporation 1 Features... ■ Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – Dual-port capability with up to 16-bit width per embedded array block (EAB) – Logic array for general logic functions ■ High density – 30,000 to 200,000 typical gates (see Tables 1 and 2) – Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity ■ System-level features – MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices – Low power consumption – Bidirectional I/O performance (tSU and tCO) up to 212 MHz – Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz – -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic f For information on 5.0-V FLEX® 10K or 3.3-V FLEX 10KA devices, see the FLEX 10K Embedded Programmable Logic Family Data Sheet. Table 1. FLEX 10KE Device Features Feature EPF10K30E EPF10K50E EPF10K50S Typical gates (1) 30,000 50,000 Maximum system gates 119,000 199,000 Logic elements (LEs) 1,728 2,880 EABs 6 10 Total RAM bits 24,576 40,960 Maximum user I/O pins 220 254DS-F10KE-2.5

Page 3

FLEX 10KE Embedded Programmable Logic Devices Data SheetNote to tables: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. (2) New EPF10K100B designs should use EPF10K100E devices. ...and More Features – Fabricated on an advanced process and operate with a 2.5-V internal supply voltage – In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port – ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication – Built-in low-skew clock distribution trees – 100% functional testing of all devices; test vectors or scan chains are not required – Pull-up on I/O pins before and during configuration ■ Flexible interconnect – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state buses – Up to six global clock signals and four global clear signals ■ Powerful I/O pins – Individual tri-state output enable control for each pin – Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise – Clamp to VCCIO user-selectable on a pin-by-pin basis – Supports hot-socketing Table 2. FLEX 10KE Device Features Feature EPF10K100E (2) EPF10K130E EPF10K200E EPF10K200S Typical gates (1) 100,000 130,000 200,000 Maximum system gates 257,000 342,000 513,000 Logic elements (LEs) 4,992 6,656 9,984 EABs 12 16 24 Total RAM bits 49,152 65,536 98,304 Maximum user I/O pins 338 413 4702 Altera Corporation

Page 4

FLEX 10KE Embedded Programmable Logic Devices Data Sheet■ Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 ■ Flexible package options – Available in a variety of packages with 144 to 672 pins, including the innovative FineLine BGATM packages (see Tables 3 and 4) – SameFrameTM pin-out compatibility between FLEX 10KA and FLEX 10KE devices across a range of device densities and pin counts ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes: (1) FLEX 10KE device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), pin-grid array (PGA), and ball-grid array (BGA) packages. (2) Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When planning device migration, use the I/O pins that are common to all devices. (3) This option is supported with a 484-pin FineLine BGA package. By using SameFrame pin migration, all FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin, 484-pin, and 672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set. Table 3. FLEX 10KE Package Options & I/O Pin Count Notes (1), (2) Device 144-Pin TQFP 208-Pin PQFP 240-Pin PQFP RQFP 256-Pin FineLine BGA 356-Pin BGA 484-Pin FineLine BGA 599-Pin PGA 600-Pin BGA 672-Pin FineLine BGA EPF10K30E 102 147 176 220 220 (3) EPF10K50E 102 147 189 191 254 254 (3) EPF10K50S 102 147 189 191 220 254 254 (3) EPF10K100E 147 189 191 274 338 338 (3) EPF10K130E 186 274 369 424 413 EPF10K200E 470 470 470 EPF10K200S 182 274 369 470 470 470Altera Corporation 3

Page 5

FLEX 10KE Embedded Programmable Logic Devices Data Sheet General Description Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification. FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage. Table 5 shows FLEX 10KE performance for some common designs. All performance values were obtained with Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Table 4. FLEX 10KE Package Sizes Device 144- Pin TQFP 208-Pin PQFP 240-Pin PQFP RQFP 256-Pin FineLine BGA 356- Pin BGA 484-Pin FineLine BGA 599-Pin PGA 600- Pin BGA 672-Pin FineLine BGA Pitch (mm) 0.50 0.50 0.50 1.0 1.27 1.0 – 1.27 1.0 Area (mm2) 484 936 1,197 289 1,225 529 3,904 2,025 729 Length × width (mm × mm) 22 × 22 30.6 × 30.6 34.6 × 34.6 17 × 17 35 × 35 23 × 23 62.5 × 62.5 45 × 45 27 × 274 Altera Corporation

Page 6

FLEX 10KE Embedded Programmable Logic Devices Data SheetNotes: (1) This application uses combinatorial inputs and outputs. (2) This application uses registered inputs and outputs. Table 6 shows FLEX 10KE performance for more complex designs. These designs are available as Altera MegaCore® functions. Note: (1) These values are for calculation time. Calculation time = number of clocks required/fmax. Number of clocks required = ceiling [log 2 (points)/2] × [points +14 + ceiling] Table 5. FLEX 10KE Performance Application Resources Used Performance Units LEs EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade 16-bit loadable counter 16 0 285 250 200 MHz 16-bit accumulator 16 0 285 250 200 MHz 16-to-1 multiplexer (1) 10 0 3.5 4.9 7.0 ns 16-bit multiplier with 3-stage pipeline (2) 592 0 156 131 93 MHz 256 × 16 RAM read cycle speed (2) 0 1 196 154 118 MHz 256 × 16 RAM write cycle speed (2) 0 1 185 143 106 MHz Table 6. FLEX 10KE Performance for Complex Designs Application LEs Used Performance Units -1 Speed Grade -2 Speed Grade -3 Speed Grade 8-bit, 16-tap parallel finite impulse response (FIR) filter 597 192 156 116 MSPS 8-bit, 512-point fast Fourier transform (FFT) function 1,854 23.4 28.7 38.9 µs (1) 113 92 68 MHz a16450 universal asynchronous receiver/transmitter (UART) 342 36 28 20.5 MHzAltera Corporation 5

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FLEX 10KE Embedded Programmable Logic Devices Data SheetSimilar to the FLEX 10KE architecture, embedded gate arrays are the fastest-growing segment of the gate array market. As with standard gate arrays, embedded gate arrays implement general logic in a conventional “sea-of-gates” architecture. Additionally, embedded gate arrays have dedicated die areas for implementing large, specialized functions. By embedding functions in silicon, embedded gate arrays reduce die area and increase speed when compared to standard gate arrays. While embedded megafunctions typically cannot be customized, FLEX 10KE devices are programmable, providing the designer with full control over embedded megafunctions and general logic, while facilitating iterative design changes during debugging. Each FLEX 10KE device contains an embedded array and a logic array. The embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (DSP), wide data-path manipulation, microcontroller applications, and data- transformation functions. The logic array performs the same function as the sea-of-gates in the gate array and is used to implement general logic such as counters, adders, state machines, and multiplexers. The combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device. FLEX 10KE devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers the EPC1, EPC2, and EPC16 configuration devices, which configure FLEX 10KE devices via a serial data stream. Configuration data can also be downloaded from system RAM or via the Altera BitBlasterTM, ByteBlasterMVTM, or MasterBlaster download cables. After a FLEX 10KE device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 85 ms, real-time changes can be made during system operation. FLEX 10KE devices contain an interface that permits microprocessors to configure FLEX 10KE devices serially or in-parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat a FLEX 10KE device as memory and configure it by writing to a virtual memory location, making it easy to reconfigure the device.6 Altera Corporation

Page 8

FLEX 10KE Embedded Programmable Logic Devices Data Sheetf For more information on FLEX device configuration, see the following documents: ■ Configuration Devices for APEX & FLEX Devices Data Sheet ■ BitBlaster Serial Download Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■ MasterBlaster Download Cable Data Sheet ■ Application Note 116 (Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices) FLEX 10KE devices are supported by the Altera development systems, which are integrated packages that offer schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use device- specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development system includes DesignWare functions that are optimized for the FLEX 10KE architecture. The Altera development system runs on Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800. f See the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet for more information.Altera Corporation 7

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FLEX 10KE Embedded Programmable Logic Devices Data SheetFunctional Description Each FLEX 10KE device contains an enhanced embedded array to implement memory and specialized logic functions, and a logic array to implement general logic. The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 4,096 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions, such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions. The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect. An LE consists of a four-input look-up table (LUT), a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic—such as 8-bit counters, address decoders, or state machines—or combined across LABs to create larger logic blocks. Each LAB represents about 96 usable gates of logic. Signal interconnections within FLEX 10KE devices (as well as to and from device pins) are provided by the FastTrack Interconnect routing structure, which is a series of fast, continuous row and column channels that run the entire length and width of the device. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect routing structure. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 0.9 ns and hold times of 0 ns. As outputs, these registers provide clock-to-output times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. 8 Altera Corporation

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FLEX 10KE Embedded Programmable Logic Devices Data SheetFigure 1 shows a block diagram of the FLEX 10KE architecture. Each group of LEs is combined into an LAB; groups of LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect routing structure. IOEs are located at the end of each row and column of the FastTrack Interconnect routing structure. Figure 1. FLEX 10KE Device Block Diagram FLEX 10KE devices provide six dedicated inputs that drive the flipflops’ control inputs and ensure the efficient distribution of high-speed, low- skew (less than 1.5 ns) control signals. These signals use dedicated routing channels that provide shorter delays and lower skews than the FastTrack Interconnect routing structure. Four of the dedicated inputs drive four global signals. These four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or an internally generated asynchronous clear signal that clears many registers in the device. I/O Element (IOE) Logic Array Block (LAB) Row Interconnect IOEIOE IOEIOE IOE IOE IOE Local Interconnect IOEIOE IOEIOE IOEIOE IOEIOE IOEIOE Logic Element (LE) Column Interconnect IOE EAB EAB Logic Array IOEIOE IOEIOE IOEIOE Embedded Array Block (EAB) Embedded Array IOE IOE Logic Array IOE IOEAltera Corporation 9

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