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Part Number EPM3128ATC100-7N
Manufacturer Altera
Description IC CPLD 128MC 7.5NS 100TQFP
Datasheet EPM3128ATC100-7N Datasheet
Package 100-TQFP
In Stock 4,682 piece(s)
Unit Price $ 13.5100 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 26 - Oct 1 (Choose Expedited Shipping)
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Part Number # EPM3128ATC100-7N (Embedded - CPLDs (Complex Programmable Logic Devices)) is manufactured by Altera and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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EPM3128ATC100-7N Specifications

CategoryIntegrated Circuits (ICs) - Embedded - CPLDs (Complex Programmable Logic Devices)
Datasheet EPM3128ATC100-7NDatasheet
SeriesMAX? 3000A
Programmable TypeIn System Programmable
Delay Time tpd(1) Max7.5ns
Voltage Supply - Internal3 V ~ 3.6 V
Number of Logic Elements/Blocks8
Number of Macrocells128
Number of Gates2500
Number of I/O80
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case100-TQFP
Supplier Device Package100-TQFP (14x14)

EPM3128ATC100-7N Datasheet

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Page 2

® MAX 3000A Programmable Logic Device Family June 2006, ver. 3.5 Data SheetFeatures... ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ISP circuitry compliant with IEEE Std. 1532 ■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ■ Enhanced ISP features: – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in–system programming ■ High–density PLDs ranging from 600 to 10,000 usable gates ■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz ■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels ■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages ■ Hot–socketing support ■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ■ Industrial temperature range Table 1. MAX 3000A Device Features Feature EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Usable gates 600 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Logic array blocks 2 4 8 16 32 Maximum user I/O pins 34 66 98 161 208 tPD (ns) 4.5 4.5 5.0 7.5 7.5 tSU (ns) 2.9 2.8 3.3 5.2 5.6 tCO1 (ns) 3.0 3.1 3.4 4.8 4.7 fCNT (MHz) 227.3 222.2 192.3 126.6 116.3Altera Corporation 1 DS-MAX3000A-3.5

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MAX 3000A Programmable Logic Device Family Data Sheet...and More Features ■ PCI compatible ■ Bus–friendly architecture including programmable slew–rate control ■ Open–drain output option ■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls ■ Programmable power–saving mode for a power reduction of over 50% in each macrocell ■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell ■ Programmable security bit for protection of proprietary designs ■ Enhanced architectural features, including: – 6 or 10 pin– or logic–driven output enable signals – Two global clock signals with optional inversion – Enhanced interconnect resources for improved routability – Programmable output slew–rate control ■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest ■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) General Description MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.2 Altera Corporation

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MAX 3000A Programmable Logic Device Family Data SheetThe MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. See Table 3. Note: (1) When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or boundary–scan testing, four I/O pins become JTAG pins. MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user–configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times. Table 2. MAX 3000A Speed Grades Device Speed Grade –4 –5 –6 –7 –10 EPM3032A v v v EPM3064A v v v EPM3128A v v v EPM3256A v v EPM3512A v v Table 3. MAX 3000A Maximum User I/O Pins Note (1) Device 44–Pin PLCC 44–Pin TQFP 100–Pin TQFP 144–Pin TQFP 208–Pin PQFP 256-Pin FineLine BGA EPM3032A 34 34 EPM3064A 34 34 66 EPM3128A 80 96 98 EPM3256A 116 158 161 EPM3512A 172 208Altera Corporation 3

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MAX 3000A Programmable Logic Device Family Data SheetMAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and high–speed parallel expander product terms to provide up to 32 product terms per macrocell. MAX 3000A devices provide programmable speed/power optimization. Speed–critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non–speed–critical signals are switching. The output drivers of all MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX 3000A devices to be used in mixed–voltage systems. MAX 3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry–standard PC– and UNIX–workstation–based EDA tools. The software runs on Windows–based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. Functional Description The MAX 3000A architecture includes the following elements: ■ Logic array blocks (LABs) ■ Macrocells ■ Expander product terms (shareable and parallel) ■ Programmable interconnect array (PIA) ■ I/O control blocks The MAX 3000A architecture includes four dedicated inputs that can be used as general–purpose inputs or as high–speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 3000A devices.4 Altera Corporation

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MAX 3000A Programmable Logic Device Family Data SheetFigure 1. MAX 3000A Device Block Diagram Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Logic Array Blocks The MAX 3000A device architecture is based on the linking of high–performance LABs. LABs consist of 16–macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: ■ 36 signals from the PIA that are used for general logic inputs ■ Global controls that are used for secondary register functions 6 or 10 6 or 10 INPUT/GCLRn 6 or 10 Output Enables (1) 6 or 10 Output Enables (1) 16 36 36 16 I/O Control Block LAB C LAB D I/O Control Block 6 or 10 16 36 36 16 I/O Control Block LAB A Macrocells 1 to 16 LAB B I/O Control Block 6 or 10 PIA INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 2 to 16 I/O 2 to 16 I/O 2 to 16 I/O 2 to 16 I/O 2 to 16 2 to 16 2 to 16 2 to 16 2 to 162 to 16 2 to 162 to 16 Macrocells 17 to 32 Macrocells 33 to 48 Macrocells 49 to 64Altera Corporation 5

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MAX 3000A Programmable Logic Device Family Data SheetMacrocells MAX 3000A macrocells can be individually configured for either sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, product–term select matrix, and programmable register. Figure 2 shows a MAX 3000A macrocell. Figure 2. MAX 3000A Macrocell Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product–term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ Shareable expanders, which are inverted product terms that are fed back into the logic array ■ Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product–term allocation according to the logic requirements of the design. Product- Term Select Matrix 36 Signals from PIA 16 Expander Product Terms LAB Local Array Parallel Logic Expanders (from other macrocells) Shared Logic Expanders Clear Select Global Clear Global Clocks Clock/ Enable Select 2 PRN CLRN Q ENA Register Bypass To I/O Control Block To PIA Programmable Register VCC D/T6 Altera Corporation

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MAX 3000A Programmable Logic Device Family Data SheetFor registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ Global clock signal mode, which achieves the fastest clock–to–output performance. ■ Global clock signal enabled by an active–high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock–to–output performance of the global clock. ■ Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 3000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the two global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product–term select matrix allocates product terms to control these operations. Although the product–term–driven preset and clear from the register are active high, active–low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active–low dedicated global clear pin (GCLRn). All registers are cleared upon power-up. By default, all registered outputs drive low when the device is powered up. You can set the registered outputs to drive high upon power-up through the Quartus® II software. Quartus II software uses the NOT Gate Push-Back method, which uses an additional macrocell to set the output high. To set this in the Quartus II software, go to the Assignment Editor and set the Power-Up Level assignment for the register to High. Altera Corporation 7

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MAX 3000A Programmable Logic Device Family Data SheetExpander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, highly complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX 3000A architecture also offers both shareable and parallel expander product terms (“expanders”) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. Shareable expanders incur a small delay (tSEXP). Figure 3 shows how shareable expanders can feed multiple macrocells. Figure 3. MAX 3000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 36 Signals from PIA 16 Shared Expanders8 Altera Corporation

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MAX 3000A Programmable Logic Device Family Data SheetParallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The Altera development system compiler can automatically allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 × tPEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower– numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest–numbered macrocell can only lend parallel expanders and the highest–numbered macrocell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell.Altera Corporation 9

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August 13, 2020

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August 5, 2020

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