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EPM7256AEFI256-7N

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EPM7256AEFI256-7N

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Part Number EPM7256AEFI256-7N
Manufacturer Altera
Description IC CPLD 256MC 7.5NS 256FBGA
Datasheet EPM7256AEFI256-7N Datasheet
Package 256-BGA
In Stock 952 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 4 - Dec 9 (Choose Expedited Shipping)
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Part Number # EPM7256AEFI256-7N (Embedded - CPLDs (Complex Programmable Logic Devices)) is manufactured by Altera and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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EPM7256AEFI256-7N Specifications

ManufacturerAltera
CategoryIntegrated Circuits (ICs) - Embedded - CPLDs (Complex Programmable Logic Devices)
Datasheet EPM7256AEFI256-7NDatasheet
Package256-BGA
SeriesMAX? 7000A
Programmable TypeIn System Programmable
Delay Time tpd(1) Max7.5ns
Voltage Supply - Internal3 V ~ 3.6 V
Number of Logic Elements/Blocks16
Number of Macrocells256
Number of Gates5000
Number of I/O164
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case256-BGA
Supplier Device Package256-FBGA (17x17)

EPM7256AEFI256-7N Datasheet

Page 1

Page 2

® Includes MAX 7000AE MAX 7000A Programmable Logic Device September 2003, ver. 4.5 Data SheetAltera Corporation 1 Features... ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 – EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532 ■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 ■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71 ■ Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) – ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) – Pull-up resistor on I/O pins during in-system programming ■ Pin-compatible with the popular 5.0-V MAX 7000S devices ■ High-density PLDs ranging from 600 to 10,000 usable gates ■ Extended temperature range f For information on in-system programmable 5.0-V MAX 7000 or 2.5-V MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.DS-M7000A-4.5

Page 3

MAX 7000A Programmable Logic Device Data Sheet...and More Features ■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz ■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels ■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space- saving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages ■ Supports hot-socketing in MAX 7000AE devices ■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ■ PCI-compatible ■ Bus-friendly architecture, including programmable slew-rate control ■ Open-drain output option ■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls ■ Programmable power-up states for macrocell registers in MAX 7000AE devices ■ Programmable power-saving mode for 50% or greater power reduction in each macrocell ■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell ■ Programmable security bit for protection of proprietary designs ■ 6 to 10 pin- or logic-driven output enable signals ■ Two global clock signals with optional inversion ■ Enhanced interconnect resources for improved routability ■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers ■ Programmable output slew-rate control ■ Programmable ground pins Table 1. MAX 7000A Device Features Feature EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE Usable gates 600 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Logic array blocks 2 4 8 16 32 Maximum user I/O pins 36 68 100 164 212 tPD (ns) 4.5 4.5 5.0 5.5 7.5 tSU (ns) 2.9 2.8 3.3 3.9 5.6 tFSU (ns) 2.5 2.5 2.5 2.5 3.0 tCO1 (ns) 3.0 3.1 3.4 3.5 4.7 fCNT (MHz) 227.3 222.2 192.3 172.4 116.32 Altera Corporation

Page 4

MAX 7000A Programmable Logic Device Data SheetAltera Corporation 3 ■ Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest ■ Programming support with Altera’s Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, ByteBlasterMVTM parallel port download cable, and BitBlasterTM serial download cable, as well as programming hardware from third-party manufacturers and any JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable in-circuit tester General Description MAX 7000A (including MAX 7000AE) devices are high-density, high- performance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM- based MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. Table 2. MAX 7000A Speed Grades Device Speed Grade -4 -5 -6 -7 -10 -12 EPM7032AE v v v EPM7064AE v v v EPM7128A v v v v EPM7128AE v v v EPM7256A v v v v EPM7256AE v v v EPM7512AE v v v

Page 5

MAX 7000A Programmable Logic Device Data SheetThe MAX 7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX 7000A devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA, PQFP, and TQFP packages. See Table 3 and Table 4. Notes to tables: (1) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O pins become JTAG pins. (2) All Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details. (3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details. Table 3. MAX 7000A Maximum User I/O Pins Note (1) Device 44-Pin PLCC 44-Pin TQFP 49-Pin Ultra FineLine BGA (2) 84-Pin PLCC 100-Pin TQFP 100-Pin FineLine BGA (3) EPM7032AE 36 36 EPM7064AE 36 36 41 68 68 EPM7128A 68 84 84 EPM7128AE 68 84 84 EPM7256A 84 EPM7256AE 84 84 EPM7512AE Table 4. MAX 7000A Maximum User I/O Pins Note (1) Device 144-Pin TQFP 169-Pin Ultra FineLine BGA (2) 208-Pin PQFP 256-Pin BGA 256-Pin FineLine BGA (3) EPM7032AE EPM7064AE EPM7128A 100 100 EPM7128AE 100 100 100 EPM7256A 120 164 164 EPM7256AE 120 164 164 EPM7512AE 120 176 212 2124 Altera Corporation

Page 6

MAX 7000A Programmable Logic Device Data SheetAltera Corporation 5 MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX 7000A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product terms, providing up to 32 product terms per macrocell. MAX 7000A devices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used in mixed-voltage systems. MAX 7000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet.

Page 7

MAX 7000A Programmable Logic Device Data SheetFunctional Description The MAX 7000A architecture includes the following elements: ■ Logic array blocks (LABs) ■ Macrocells ■ Expander product terms (shareable and parallel) ■ Programmable interconnect array ■ I/O control blocks The MAX 7000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000A devices.6 Altera Corporation

Page 8

MAX 7000A Programmable Logic Device Data SheetFigure 1. MAX 7000A Device Block Diagram Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables. EPM7512AE devices have 10 output enables. Logic Array Blocks The MAX 7000A device architecture is based on the linking of high-performance LABs. LABs consist of 16-macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: ■ 36 signals from the PIA that are used for general logic inputs ■ Global controls that are used for secondary register functions ■ Direct input paths from I/O pins to the registers that are used for fast setup times 6 6 INPUT/GCLRn 6 or 10 Output Enables (1) 6 or 10 Output Enables (1) 16 36 36 16 I/O Control Block LAB C LAB D I/O Control Block 6 16 36 36 16 I/O Control Block LAB A Macrocells 1 to 16 LAB B I/O Control Block 6 PIA INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 2 to 16 I/O 2 to 16 I/O 2 to 16 I/O 2 to 16 I/O 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 162 to 16 2 to 162 to 16 Macrocells 17 to 32 Macrocells 33 to 48 Macrocells 49 to 64Altera Corporation 7

Page 9

MAX 7000A Programmable Logic Device Data SheetMacrocells MAX 7000A macrocells can be individually configured for either sequential or combinatorial logic operation. The macrocells consist of three functional blocks: the logic array, the product-term select matrix, and the programmable register. Figure 2 shows a MAX 7000A macrocell. Figure 2. MAX 7000A Macrocell Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ Shareable expanders, which are inverted product terms that are fed back into the logic array ■ Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. Product- Term Select Matrix 36 Signals from PIA 16 Expander Product Terms LAB Local Array Parallel Logic Expanders (from other macrocells) Shared Logic Expanders Clear Select Global Clear Global Clocks Clock/ Enable Select 2 PRN CLRN D/T Q ENA Register Bypass To I/O Control Block From I/O pin To PIA Programmable Register Fast Input Select VCC8 Altera Corporation

Page 10

MAX 7000A Programmable Logic Device Data SheetFor registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ Global clock signal. This mode achieves the fastest clock-to-output performance. ■ Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. ■ Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 7000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE device may be set to either a high or low state. This power-up state is specified at design entry. Upon power-up, each register in EPM7128A and EPM7256A devices are set to a low state. All MAX 7000A I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be clocked to an input D flipflop with an extremely fast (as low as 2.5 ns) input setup time.Altera Corporation 9

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