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Part Number FAN5234MTC
Manufacturer Fairchild/ON Semiconductor
Datasheet FAN5234MTC Datasheet
Package 16-TSSOP (0.173", 4.40mm Width)
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Part Number # FAN5234MTC (PMIC - Voltage Regulators - Special Purpose) is manufactured by Fairchild/ON Semiconductor and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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FAN5234MTC Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Special Purpose
Datasheet FAN5234MTCDatasheet
Package16-TSSOP (0.173", 4.40mm Width)
ApplicationsController, Mobile PCs
Voltage - Input2 V ~ 24 V
Number of Outputs1
Voltage - Output0.9 V ~ 5.5 V
Operating Temperature-10°C ~ 85°C
Mounting TypeSurface Mount
Package / Case16-TSSOP (0.173", 4.40mm Width)
Supplier Device Package16-TSSOP

FAN5234MTC Datasheet

Page 1

Page 2 REV. 1.0.10 5/3/04 Features • Wide input voltage range (2 to 24V) for Mobile systems • Excellent dynamic response with Voltage Feed-Forward and Average Current Mode control • Lossless current sensing on low-side MOSFET or precision over-current using sense resistor • VCC Under-voltage Lockout • Power-Good Signal • Light load Hysteretic mode maximizes efficiency • QSOP16, TSSOP16 • 300Khz or 600Khz operation Applications • Mobile PC regulator • Hand-Held PC power General Description The FAN5234 PWM controller provides high efficiency and regulation with an adjustable output from 0.9V to 5.5V that are required to power I/O, chip-sets, memory banks or peripherals in high-performance notebook computers, PDAs and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of loads. The hysteretic mode of operation can be disabled if PWM mode is desired for all load levels. Efficiency is even further enhanced by using MOSFET’s R DS(ON) as a current sense component. Feed-forward ramp modulation, average current mode control, and internal feedback compensation provide fast response to load transients. The FAN5234 monitors these outputs and generates a PGOOD (power good) signal when the soft-start is completed and the output is within ±10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over- voltage conditions go away. Under-voltage protection latches the chip off when the output drops below 75% of its set value after the soft-start sequence is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. Typical Application Figure 1. 1.8V Output Regulator (see Table 2, page 12 for BOM) SW FAN5234 10 C6 L1 Q1B 14 ILIM 1 4 R1 R2 11 VCC +5 D1 +515 13 R3 12 C4 8 R5 PGOOD 2 +5 9 ISNS PGND Q1A 6 VSEN LDRV HDRV BOOT VIN C5 C1 1.8V@3.5A R4 VIN (BATTERY) = 2 to 24V C2 AGND EN 3 SS1 7 C3 16 FPWM VOUT 5 FAN5234 Mobile-Friendly PWM/PFM Controller

Page 3

FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 2 Pin Configurations Pin Definitions Pin Number Pin Name Pin Function Description 1 VIN Input Voltage. Connect to main input power source (battery). Also used to program operating frequency for low input voltage operation. See Table 1. 2 PGOOD Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a ±10% range of the 0.9V reference. 3 EN ENABLE . Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. This is a CMOS inputs whose state is indeterminate if left open. 4 ILIM Current Limit. A resistor from this pin to GND sets the current limit. 5 VOUT Output Voltage. Connect to output voltage. Used for regulation to ensure a smooth transitions during mode changes. When VOUT is expected to exceed VCC, tie this pin to VCC. 6 VSEN Output Voltage Sense. The feedback from the output. Used for regulation as well as PGOOD, under-voltage, and over-voltage protection and monitoring. 7 SS Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5 µ A current source. 8 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. 9 PGND Power Ground. The return for the low-side MOSFET driver. Connect to source of low- side MOSFET. 10 LDRV Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. 11 VCC VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). 12 ISNS Current Sense input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. 13 SW Switching node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. 14 HDRV High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. 15 BOOT BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 2. 16 FPWM Forced PWM mode. When logic HIGH, inhibits the regulator from entering hysteretic mode. VIN PGOOD EN ILIM VOUT VSEN SS AGND FAN5234 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FPWM BOOT HDRV SW ISNS VCC LDRV PGND QSOP-16 or TSSOP-16 θ JA = 112°C/W

Page 4

FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 3 Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Recommended Operating Conditions Parameter Min. Typ. Max. Units VCC Supply Voltage: 6.5 V VIN 27 V BOOT, SW, ISNS, HDRV 33 V BOOT to SW 6.5 V All Other Pins –0.3 VCC+0.3 V Junction Temperature (T J ) –10 150 °C Storage Temperature –65 150 °C Lead Soldering Temperature, 10 seconds 300 °C Parameter Conditions Min. Typ. Max. Units Supply Voltage VCC 4.75 5 5.25 V Supply Voltage VIN 5 24 V Ambient Temperature (T A ) – 10 85 °C

Page 5

PRODUCT SPECIFICATION FAN5234 4 REV. 1.0.10 5/3/04 Electrical Specifications Recommended operating conditions, unless otherwise noted. Parameter Conditions Min. Typ. Max. Units Power Supplies VCC Current LDRV, HDRV Open, VSEN forced above regulation point 850 1300 µ A Shut-down (EN=0) 5 15 µ A VIN Current - Sinking VIN pin = input voltage source 10 20 30 µ A VIN Current - Sourcing VIN pin = GND 7 15 20 µ A VIN Current - Shut-down 1 µ A UVLO Threshold Rising VCC 4.3 4.55 4.75 V Falling 4.1 4.27 4.5 V Hysteresis 0.1 0.5 V Oscillator Frequency VIN > 5V 255 300 345 KHz VIN = 0V 510 600 690 KHz Ramp Amplitude, pk–pk VIN = 16V 2 V Ramp Amplitude, pk–pk VIN < 5V 1.25 V Ramp Offset 0.5 V Ramp / VIN Gain VIN > 3V 125 mV/V Ramp / VIN Gain 1V < VIN < 3V 250 mV/V Reference and Soft Start Internal Reference Voltage 0.891 0.9 0.909 V Soft Start current (I SS ) at start-up 5 µ A Soft Start Complete Threshold 1.5 V PWM Converter Load Regulation I OUT from 0 to 3A, VIN from 2 to 24V -1 +1 % VSEN Bias Current 50 80 120 nA VOUT pin input impedance 40 55 65 K Ω Under-voltage Shutdown as % of set point. 2 µ S noise filter 70 75 80 % I SNS Over-Current threshold R ILIM = 68.5K Ω . See Figure 4 115 144 172 µA Over-voltage threshold as % of set point. 2 µ S noise filter 113 120 % Output Driver HDRV Output Resistance Sourcing 8 15 Ω Sinking 3.2 4 Ω LDRV Output Resistance Sourcing 8 15 Ω Sinking 1.5 2.4 Ω PGOOD (Power Good Output) and Control pins Lower Threshold as % of set point, 2 µ S noise filter 86 92 % Upper Threshold as % of set point, 2 µ S noise filter 110 115 % PGOOD Output Low I PGOOD = 4mA 0.5 V Leakage Current V PULLUP = 5V 1 µ A Soft Start Voltage when PGOOD Enabled 1.5 V EN, FPWM Inputs Input High 2 V Input Low 0.8 V

Page 6

FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 5 Figure 2. IC Block Diagram REF2 PGOOD EN C BOOT Q1 Q2 5V VDD ADAPTIVE GATE CONTROL LOGIC CURRENT PROCESSING HDRV SW LDRV PGND BOOT VDD HYST ISNS VIN C OUT VOUT PWM/HYST PWM S/H ILIM R IL IM R SENSEILIM det. HYST SS SS DUTY CYCLE CLAMP Σ PWM S R Q RAMP MODE OSC I OUT RAMP CLK OVP POR/UVLO Reference and Soft Start FPWM L OUT VREF EA PWM/HYST VSEN FPWM VIN Circuit Description Overview The FAN5234 is a PWM controller intended for low voltage power applications in modern notebook, desktop, and sub-notebook PCs. The output voltage of the controller can be set in the range of 0.9V to 5.5V by an external resistor divider. The synchronous buck converter can operate from either an unregulated DC source (such as a notebook battery) with voltage ranging from 2V to 24V, or from a regulated system rail. In either mode of operation the IC is biased from a +5V source. The PWM modulator uses an average current mode control with input voltage feed-forward for simplified feed- back loop compensation and improved line regulation. The controller includes integrated feedback loop compensation that dramatically reduces the number of external compo- nents. Depending on the load level, the converter can operate either in fixed frequency PWM mode or in a hysteretic mode. Switch-over from PWM to hysteretic mode improves the converters' efficiency at light loads and prolongs battery run time. In hysteretic mode, a comparator is synchronized to the main clock that allows seamless transition between the oper- ational modes and reduced channel-to-channel interaction. The hysteretic mode of operation can be inhibited indepen- dently using the FPWM pin if variable frequency operation is not desired. Oscillator Table 1. Converter Operating modes When VIN is from the battery, the oscillator's ramp ampli- tude is proportional to VIN, providing voltage feed-forward control for improved loop response. When in either of the Fixed modes, oscillator's ramp amplitude is fixed. The oper- ating frequency is then determined according to the connec- tion on the VIN pin (Table 1). Initialization and Soft Start Assuming EN is high, FAN5234 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal Power-On Reset function disables the chip. Mode F SW (Khz) Converter Power VIN Pin Battery 300 2 to 24V Battery (>5V) Fixed 300 300 < 5.5V Fixed 100K Ω to GND Fixed 600 600 < 5.5V Fixed GND

Page 7

PRODUCT SPECIFICATION FAN5234 6 REV. 1.0.10 5/3/04 The voltage at the positive input of the error amplifier is lim- ited by the voltage at the SS pin which is charged with a 5mA current source. Once C SS has charged to VREF (0.9V) the output voltage will be in regulation. The time it takes SS to reach 0.9V is: where T 0.9 is in seconds if C SS is in µ F. When SS reaches 1.5V, the Power Good outputs are enabled and hysteretic mode is allowed. The converter is forced into PWM mode during soft start. Operation Mode Control The mode-control circuit changes the converter’s mode of operation from PWM to Hysteretic and visa versa, based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed-frequency PWM mode as shown in Figure 3. This mode of operation achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the ‘reverse’ direction, the SW node becomes positive, and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switch- ing frequency. To prevent accidental mode change or "mode chatter" the transition from PWM to Hysteretic mode occurs when the SW node is positive for eight consecutive clock cycles (see Figure 3). The polarity of the SW node is sampled at the end of the lower MOSFET's conduction time. At the transi- tion between PWM and hysteretic mode both the upper and lower MOSFETs are turned off. The SW node will ‘ring’ based on the output inductor and the parasitic capacitance on the SW node and settle out at the value of the output voltage. The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression. Hysteretic Mode Conversely, the transition from Hysteretic mode to PWM mode occurs when the SW node is negative for 8 consecutive cycles. A sudden increase in the output current will also cause a change from hysteretic to PWM mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load causes the output voltage (as presented at VSEN) to drop below the hysteretic regulation level (20mV below VREF), the mode is changed to PWM on the next clock cycle. In hysteretic mode, the PWM comparator and the error amplifier that provide control in PWM mode are inhibited and the hysteretic comparator is activated. In hysteretic mode the low side MOSFET is operated as a synchronous rectifier, where the voltage across (V DS(ON) ) it is monitored, and it is switched off when V DS(ON) goes positive (current flowing back from the load) allowing the diode to block reverse conduction. T0.9 0.9 CSS× 5 ----------------------= (1) ILOAD DIS( ) VIN VOUT–( )VOUT 2FSWLOUTVIN --------------------------------------------------= (2) Figure 3. Transitioning between PWM and Hysteretic Mode PWM ModeHysteretic Mode Hysteretic ModePWM Mode 1 2 3 4 5 6 7 8 VCORE I L 0 VCORE I L 0 1 2 3 4 5 6 7 8

Page 8

FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 7 Figure 4. Current Limit / Summing Circuits LDRV PGND ISNSin + in – 2.5VILIM det. R SENSE SS 1.5M C SS VSEN V to I Reference and Soft Start 17pf ISNS S/H TO PWM COMP 4.14K 300K ISNS 0.17pf I2 = ILIM*11.2 ILIM 0.9V R ILIM ILIM The hysteretic comparator causes HDRV turn-on when the output voltage (at VSEN) falls below the lower threshold (10mV below VREF) and terminates the PFM signal when VSEN rises over the higher threshold (5mV above VREF). The switching frequency is primarily a function of: 1. Spread between the two hysteretic thresholds 2. ILOAD 3. Output Inductor and Capacitor ESR A transition back to PWM (Continuous Conduction Mode or CCM) mode occurs when the inductor current rises suffi- ciently to stay positive for 8 consecutive cycles. This occurs when: where ∆VHYSTERESIS = 15mV and ESR is the equivalent series resistance of COUT. Because of the different control mechanisms, the value of the load current where transition into PWM operation takes place is typically higher compared to the load level at which transition into hysteretic mode occurs. Hysteretic mode can be disabled by setting the FPWM pin HIGH. Current Processing Section The following discussion refers to Figure 4. The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on. That current is held, and summed with the output of the error amplifier. This effec- tively creates a current mode control loop. The resistor con- nected to ISNS pin (RSENSE) sets the gain in the current feedback loop. For stable operation, the voltage induced by the current feedback at the PWM comparator input should be set to 30% of the ramp amplitude at maximum load currrent and line voltage. The following expression estimates the rec- ommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET’s RDS(ON): RSENSE must, however, be kept higher than: Setting the Current Limit A ratio of ISNS is also compared to the current established when a 0.9 V internal reference drives the ILIM pin: Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4%/°C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease propotional to increasing MOSFET die temperature. A factor of 1.6 in the current limit setpoint should compensate for all MOSFET RDS(ON) variations, assuming the MOSFET’s heat sinking will keep its operating die temperature below 125°C. ILOAD CCM( ) ∆VHYSTERESIS 2 ESR --------------------------------------= (3) RSENSE ILOAD MAX( ) RDS ON( )× 4.1K× 30% 0.125× VIN MAX( )× ----------------------------------------------------------------------------- 100–= (4a) RSENSE ILOAD MAX( ) RDS ON( )× 150µA ----------------------------------------------------------- 100–= (4b) (5)RILIM 11.2 ILIMIT --------------- 100 RSENSE+( ) RDS ON( ) ---------------------------------------×=

Page 9

PRODUCT SPECIFICATION FAN5234 8 REV. 1.0.10 5/3/04 Figure 5. Improving current sensing accuracy More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET as shown in Figure 5. This approach causes higher losses, but yields greater accu- racy in both VDROOP and ILIMIT. R1 is a low value (e.g. 10mΩ) resistor. Current limit (ILIMIT) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.2 is sufficient. In addition, since ILIMIT is a peak current cut-off value, we will need to multiply ILOAD(MAX) by the inductor ripple current (we’ll use 25%). For example, in Figure 1 the target for ILIMIT would be: ILIMIT > 1.2 × 1.25 × 1.6 × 6A ≈ 14A (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit pushing a duty cycle to almost 100% for significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient, over-current condition, or even to a failure espe- cially at high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting the maximum duty cycle to This circuit is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. Gate Driver section The Adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 Volt. This allows a wide variety of upper and lower MOS- FETs to be used without a concern for simultaneous conduc- tion, or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adap- tive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circit and shoot-through may occur. Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency deter- mined by load where RO is load resistance, CO is load capacitance. For this type of modulator, Type 2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an inter- nally compensated error amplifier. Figure 6 shows a Type 2 amplifier and its response along with the responses of a current mode modulator and of the converter. The Type 2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. Figure 6. Compensation LDRV PGND ISNS RSENSE R 1 Q2 DCMAX VOUT VIN -------------- 2.4 VIN ---------+= FPO 1 2πROCO ---------------------= (7) R1 R2 EA Out C1 C2 REF VIN C onverter 0 14 18 modulator F P0 F Z F P error amp FZ 1 2πR2C1 ------------------- 6kHz= = (8a) FP 1 2πR2C2 ------------------- 600kHz= = (8b)

Page 10

FAN5234 PRODUCT SPECIFICATION REV. 1.0.10 5/3/04 9 This region is also associated with phase ‘bump’ or reduced phase shift. The amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90 degrees. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp. The zero frequency, the amplifier high frequency gain and the modulator gain are chosen to satisfy most typical appli- cations. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz...50kHz range gives some additional phase ‘boost’. Fortunately, there is an oppo- site trend in mobile applications to keep the output capacitor as small as possible. Protection The converter output is monitored and protected against extreme overload, short circuit, over-voltage and under- voltage conditions. A sustained overload on an output sets the PGOOD pin low and latches-off the whole chip. Operation can be restored by cycling the VCC voltage or by toggling the EN pin. If VOUT drops below the under-voltage threshold, the chip shuts down immediately. Over-Current sensing If the circuit's current limit signal (“ILIM det” as shown in Figure 4) is high at the beginning of a clock cycle, a pulse-skipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If at any time from the 9th to the 16th clock cycle, the "ILIM det" is again reached, the over-current protection latch is set, disabling the chip. If "ILIM det" does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. Figure 7. Over-Current protection waveforms Over-Voltage / Under-Voltage Protection Should the VSEN voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure, or for other reasons, the overvoltage protection comparator will force LDRV high. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, will eventually blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a ‘soft’ crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. Similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point. Should this condition occur, the regulator will shut down. Over-Temperature Protection The chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of about 150˚C is reached. Normal operation is restored at die tem- perature below 125˚C with internal Power On Reset asserted, resulting in a full soft-start cycle. Design and Component Selection Guidelines As an initial step, define operating input voltage range, output voltage, minimum and maximum load currents for the controller. For the examples in the following discussion, we will be selecting components for: VIN from 5V to 20V VOUT = 1.8V @ ILOAD(MAX) = 3.5A 1 2 3 CH1 5.0V CH3 2.0AΩ CH2 100mV M 10.0µs IL PGOOD 8 CLK VOUT

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December 5, 2020

Components all tested within limits of specifications. Components came packaged in an easy to identify resealable bag and will work well for my projects.

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