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GAL22V10D-15LPNI

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GAL22V10D-15LPNI

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Part Number GAL22V10D-15LPNI
Manufacturer Lattice Semiconductor Corporation
Description IC CPLD 10MC 15NS 24DIP
Datasheet GAL22V10D-15LPNI Datasheet
Package 24-DIP (0.300", 7.62mm)
In Stock 42,964 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 27 - Oct 2 (Choose Expedited Shipping)
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Part Number # GAL22V10D-15LPNI (Embedded - CPLDs (Complex Programmable Logic Devices)) is manufactured by Lattice Semiconductor Corporation and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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GAL22V10D-15LPNI Specifications

ManufacturerLattice Semiconductor Corporation
CategoryIntegrated Circuits (ICs) - Embedded - CPLDs (Complex Programmable Logic Devices)
Datasheet GAL22V10D-15LPNIDatasheet
Package24-DIP (0.300", 7.62mm)
SeriesGAL?22V10
Programmable TypeEE PLD
Delay Time tpd(1) Max15.0ns
Voltage Supply - Internal4.5 V ~ 5.5 V
Number of Logic Elements/Blocks-
Number of Macrocells10
Number of Gates-
Number of I/O-
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeThrough Hole
Package / Case24-DIP (0.300", 7.62mm)
Supplier Device Package24-PDIP

GAL22V10D-15LPNI Datasheet

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5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347 Internet: http://www.latticesemi.com GAL®22V10 Device Datasheet September 2010 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GAL22V10D GAL22V10D-7LP Discontinued PCN#09-10 GAL22V10D-7LPN GAL22V10D-10LP PCN#13-10 GAL22V10D-10LPN GAL22V10D-15LP GAL22V10D-15LPN GAL22V10D-25LP GAL22V10D-25LPN GAL22V10D-7LPI PCN#09-10 GAL22V10D-7LPNI GAL22V10D-10LPI PCN#13-10 GAL22V10D-10LPNI GAL22V10D-15LPI GAL22V10D-15LPNI GAL22V10D-20LPI GAL22V10D-20LPNI GAL22V10D-25LPI GAL22V10D-25LPNI GAL22V10D-10QP GAL22V10D-10QPN GAL22V10D-15QP GAL22V10D-15QPN GAL22V10D-25QP GAL22V10D-25QPN GAL22V10D-10LS PCN#06-07 GAL22V10D-15LS GAL22V10D-25LS GAL22V10D-4LJ PCN#09-10 GAL22V10D-4LJN GAL22V10D-5LJ PCN#13-10 GAL22V10D-5LJN

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5555 N.E. Moore Ct.  Hillsboro, Oregon 97124-6421  Phone (503) 268-8000  FAX (503) 268-8347 Internet: http://www.latticesemi.com Product Line Ordering Part Number Product Status Reference PCN GAL22V10D (Cont’d) GAL22V10D-7LJ Discontinued PCN#13-10 GAL22V10D-7LJN GAL22V10D-10LJ GAL22V10D-10LJN GAL22V10D-15LJ GAL22V10D-15LJN GAL22V10D-25LJ GAL22V10D-25LJN GAL22V10D-7LJI PCN#09-10 GAL22V10D-7LJNI GAL22V10D-10LJI GAL22V10D-10LJNI GAL22V10D-15LJI PCN#13-10 GAL22V10D-15LJNI GAL22V10D-20LJI GAL22V10D-20LJNI GAL22V10D-25LJI GAL22V10D-25LJNI GAL22V10D-10QJ GAL22V10D-10QJN GAL22V10D-15QJ GAL22V10D-15QJN GAL22V10D-25QJ GAL22V10D-25QJN

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Specifications GAL22V10 1 2 28 N C I/ C L K II I I I I I I NC NC N C G N D II I I/ O /Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q V c c I/ O /Q I/ O /Q I/ O /Q 4 26 25 19 18 21 23 161412 11 9 7 5 Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • ACTIVE PULL-UPS ON ALL PINS • COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V10 Devices • 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR — 90mA Typical Icc on Low Power Device — 45mA Typical Icc on Quarter Power Device • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability • APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade • ELECTRONIC SIGNATURE FOR IDENTIFICATION • LEAD-FREE PACKAGE OPTIONS ESCRIPTION Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance avail- able of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL22V10 is fully function/fuse map/parametric com- patible with standard bipolar and CMOS 22V10 devices. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lat- tice Semiconductor delivers 100% field programmability and func- tionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. GAL22V10 High Performance E2CMOS PLD Generic Array Logic™ Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 2006 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com GAL22V10 Top View PLCC 1 12 13 24I/CLK I I I I I I I I I I GND Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I 6 18 GAL 22V10 DIP 22v10_12 Functional Block Diagram Pin Configuration SOIC GAL22V10 Top View Lead- Free Packa ge Optio ns Availa ble! 1 1 2 1 3 2 4 I I I I I I I I I G N D I/ O /Q I/ O /Q I/ O /Q I/ O /Q I/ O /Q I/ O /Q I/ O /Q I/ O /Q I/ O /Q I 6 1 8 I/ C L K I V c c I/ O /Q P R O G R A M M A B L E A N D -A R R A Y (1 3 2 X 4 4 ) I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I/CLK I I I I I I I I I I RESET PRESET 8 10 12 14 16 16 14 12 10 8 OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC AL L D EV IC ES DI SC ON TIN UE D

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Specifications GAL22V10 2 Conventional Packaging Commercial Grade Specifications Industrial Grade Specifications GAL22V10 Ordering Information )sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP 5.7 5 5.4 061 01V22LAG D IPL7- PIDcitsalPniP-42 5.4 5.4 061 01V22LAG D IJL7- CCLPdaeL-82 01 7 7 061 01V22LAG D IPL01- PIDcitsalPniP-42 061 01V22LAG D IJL01- CCLPdaeL-82 51 01 8 031 G IPL51-D01V22LA PIDcitsalPniP-42 031 IJL51-D01V22LAG CCLPdaeL-82 02 41 01 031 IPL02-D01V22LAG PIDcitsalPniP-42 031 IJL02-D01V22LAG CCLPdaeL-82 52 51 51 031 IPL52-D01V22LAG PIDcitsalPniP-42 031 IJL52-D01V22LAG CCLPdaeL-82 )sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredOr geakcaP 4 5.2 5.3 041 JL4-D01V22LAG CCLPdaeL-82 5 3 4 041 JL5-D01V22LAG CCLPdaeL-82 5.7 5.4 5.4 041 PL7-D01V22LAG PIDcitsalPniP-42 5.4 5.4 041 JL7-D01V22LAG CCLPdaeL-82 01 7 7 55 PQ01-D01V22LAG PIDcitsalPniP-42 55 JQ01-D01V22LAG CCLPdaeL-82 90 90 130 90 LP01-D01V22LAG PIDcitsalPniP-42 031 JL01-D01V22LAG CCLPdaeL-82 03 LS101-D01V22LAG CIOSniP-42 51 01 8 55 PQ51-D01V22LAG PIDcitsalPniP-42 55 JQ51-D01V22LAG CCLPdaeL-82 LP51-D01V22LAG PIDcitsalPniP-42 LJ51-D01V22LAG CCLPdaeL-82 LS151-D01V22LAG CIOSniP-42 52 51 51 55 PQ52-D01V22LAG PIDcitsalPniP-42 55 JQ52-D01V22LAG CCLPdaeL-82 09 PL52-D01V22LAG piDcitsalPniP-42 09 JL52-D01V22LAG CCLPdaeL-82 09 S1L52-D01V22LAG CIOSniP-42 1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. AL L EV IC E DI SC ON TIN UE D

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Specifications GAL22V10 3 Part Number Description Lead-Free Packaging Commercial Grade Specifications )sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP 4 5.2 5.3 041 NJL4-D01V22LAG CCLPdaeL-82eerF-daeL 5 3 4 041 NJL5-D01V22LAG CCLPdaeL-82eerF-daeL 5.7 5.4 5.4 041 NPL7-D01V22LAG PIDcitsalPniP-42eerF-daeL 5.4 5.4 041 NJL7-D01V22LAG CCLPdaeL-82eerF-daeL 01 7 7 55 NPQ01-D01V22LAG PIDcitsalPniP-42eerF-daeL 55 NJQ01-D01V22LAG CCLPdaeL-82eerF-daeL 031 NPL01-D01V22LAG PIDcitsalPniP-42eerF-daeL 031 NJL01-D01V22LAG CCLPdaeL-82eerF-daeL 51 01 8 55 NPQ51-D01V22LAG PIDcitsalPniP-42eerF-daeL 55 NJQ51-D01V22LAG CCLPdaeL-82eerF-daeL 09 NPL51-D01V22LAG PIDcitsalPniP-42eerF-daeL 09 NJL51-D01V22LAG CCLPdaeL-82eerF-daeL 52 51 51 55 NPQ52-D01V22LAG PIDcitsalPniP-42eerF-daeL 55 NJQ52-D01V22LAG CCLPdaeL-82eerF-daeL 09 NPL52-D01V22LAG piDcitsalPniP-42eerF-daeL 09 NJL52-D01V22LAG CCLPdaeL-82eerF-daeL Industrial Grade Specifications )sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP 5.7 5 5.4 061 INPL7-D01V22LAG PIDcitsalPniP-42eerF-daeL 5.4 5.4 061 INJL7-D01V22LAG CCLPdaeL-82eerF-daeL 01 7 7 061 INPL01-D01V22LAG PIDcitsalPniP-42eerF-daeL 061 INJL01-D01V22LAG CCLPdaeL-82eerF-daeL 51 01 8 031 INPL51-D01V22LAG PIDcitsalPniP-42eerF-daeL 031 INJL51-D01V22LAG CCLPdaeL-82eerF-daeL 02 41 01 031 INPL02-D01V22LAG PIDcitsalPniP-42eerF-daeL 031 INJL02-D01V22LAG CCLPdaeL-82eerF-daeL 52 51 51 031 INPL52-D01V22LAG piDcitsalPniP-42eerF-daeL 031 INJL52-D01V22LAG CCLPdaeL-82eerF-daeL Blank = Commercial I = Industrial Grade PackagePowerL = Low Power Q = Quarter Power Speed (ns) XXXXXXXX XX X XX X Device Name _ P = Plastic DIP PN = Lead-Free Plastic DIP J = PLCC JN = Lead-Free PLCC S = SOIC GAL22V10D AL L EV IC ES DI SC ON TIN UE D

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Specifications GAL22V10 4 GAL22V10 OUTPUT LOGIC MACROCELL (OLMC) Each of the Macrocells of the GAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an in- dividual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Out- put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. The GAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 14 and 23, DIP pinout), two have ten product terms (pins 15 and 22), two have twelve product terms (pins 16 and 21), two have fourteen product terms (pins 17 and 20), and two OLMCs have sixteen product terms (pins 18 and 19). In addition to the product terms available for logic, each OLMC has an addi- tional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL22V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two prod- uct terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. A R S P D Q QC L K 4 T O 1 M U X 2 T O 1 M U X Output Logic Macrocell (OLMC) Output Logic Macrocell ConfigurationsAL L D EV IC ES DI SC ON TIN UE D

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Specifications GAL22V10 5 ACTIVE HIGHACTIVE LOW ACTIVE HIGHACTIVE LOW S 0 = 1 S 1 = 1 S 0 = 0 S 1 = 1 S 0 = 0 S 1 = 0 S 0 = 1 S 1 = 0 A R S P D Q QC L K A R S P D Q QC L K Registered Mode Combinatorial Mode AL L D EV IC ES DI SC ON TIN UE D

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Specifications GAL22V10 6 DIP (PLCC) Package Pinouts 1 (2) 22 (26)OLMC S0 5810 S1 5811 0440 . . . . 0880 2 (3) ASYNCHRONOUS RESET (TO ALL REGISTERS) 0 4 8 12 16 20 24 28 32 36 40 SYNCHRONOUS PRESET (TO ALL REGISTERS) 10 (12) 0000 5764 0044 . . . 0396 23 (27)S0 5808 S1 5809 21 (25)OLMC S0 5812 S1 5813 0924 . . . . . 1452 3 (4) 4 (5) 5 (6) 20 (24)OLMC S0 5814 S1 5815 1496 . . . . . . 2112 19 (23) OLMC S0 5816 S1 5817 2156 . . . . . . . 2860 18 (21) OLMC S0 5818 S1 5819 2904 . . . . . . . 3608 17 (20)OLMC S0 5820 S1 5821 3652 . . . . . . 4268 OLMC S0 5822 S1 5823 4312 . . . . . 4840 8 (10) 16 (19) 15 (18) OLMC S0 5824 S1 5825 4884 . . . . 5324 9 (11) 5368 . . . 5720 14 (17) OLMC S0 5826 S1 5827 7 (9) 6 (7) 11 (13) 13 (16) 8 10 14 16 12 12 16 14 10 8 OLMC Electronic Signature 5828, 5829 ... ... 5890, 5891 L S B M S B Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3 GAL22V10 Logic Diagram / JEDEC Fuse Map AL L D EV IC ES DI SC ON TIN UE D

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Specifications GAL22V10 7 Supply voltage V CC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to V CC +1.0V Off-state output voltage applied........... -2.5 to V CC +1.0V Storage Temperature.................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Commercial Devices: Ambient Temperature (T A ) ............................. 0 to +75°C Supply voltage (V CC ) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (T A ) ............................ -40 to 85°C Supply voltage (V CC ) with Respect to Ground ..................... +4.50 to +5.50V Specifications GAL2 V10D COMMERCIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L-4/-5/-7 — 90 140 mA Supply Current ftoggle = 15MHz Outputs Open L-10 — 90 130 mA L-15/-25 — 75 90 mA Q-10/-15/-25 — 45 55 mA VIL Input Low Voltage Vss – 0.5 — 0.8 V VIH Input High Voltage 2.0 — Vcc+1 V IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 μA VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V IOL Low Level Output Current — — 16 mA IOH High Level Output Current — — –3.2 mA IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V T A = 25°C –30 — –130 mA Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS INDUSTRIAL ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA Supply Current ftoggle = 15MHz Outputs Open L-15/-20/-25 — 75 130 mA 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 °C Absolute Maximum Ratings1 Recommended Operating Conditions DC Electrical Characteristics AL L D EV IC ES DI SC ON TIN UE D

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August 20, 2020

DELIVERY AND COMMUNICATION EXTRA SELLER TOP 5 STARS on my list

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August 19, 2020

I recently became very interested in electronics and I have used several of them. They work great.

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August 16, 2020

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August 13, 2020

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July 31, 2020

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July 27, 2020

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July 14, 2020

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July 11, 2020

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July 10, 2020

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July 4, 2020

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