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HI1-0509A-5

hot HI1-0509A-5

HI1-0509A-5

For Reference Only

Part Number HI1-0509A-5
Manufacturer Renesas Electronics America
Description IC MULTIPLEXER DUAL 4X1 16CDIP
Datasheet HI1-0509A-5 Datasheet
Package 16-CDIP (0.300", 7.62mm)
In Stock 257 piece(s)
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Lead Time Can Ship Immediately
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HI1-0509A-5

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HI1-0509A-5 Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Interface - Analog Switches, Multiplexers, Demultiplexers
Datasheet HI1-0509A-5 Datasheet
Package16-CDIP (0.300", 7.62mm)
Series-
Switch CircuitSP4T
Multiplexer/Demultiplexer Circuit4:1
Number of Circuits2
On-State Resistance (Max)1.8 kOhm
Voltage - Supply, Dual (V±)±15V
Switch Time (Ton, Toff) (Max)300ns, 300ns (Typ)
Channel Capacitance (CS(off), CD(off))10pF, 12pF
Current - Leakage (IS(off)) (Max)30pA (Typ)
Operating Temperature0°C ~ 75°C (TA)
Package / Case16-CDIP (0.300", 7.62mm)
Supplier Device Package16-CERDIP

HI1-0509A-5 Datasheet

Page 1

Page 2

FN3143 Rev.6.00 October 30, 2007 HI-506A, HI-507A, HI-508A, HI-509A 16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection DATASHEETThe HI-506A, HI-507A, HI-508A and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1k of resistance under this condition. These features make the HI-506A, HI-507A, HI-508A and HI-509A ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-506A is a single 16-channel multiplexer, the HI-507A is an 8-channel differential multiplexer, the HI-508A is a single 8-channel multiplexer and the HI-509A is a differential 4-channel multiplexer. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Note AN520. Features • Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70VP-P • No Channel Interaction During Overvoltage • Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V • Fail Safe with Power Loss (No Latch-Up) • Break-Before-Make Switching • Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V • Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns • Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW • Pb-Free Available (RoHS Compliant) Applications • Data Acquisition Systems • Industrial Controls • TelemetryFN3143 Rev.6.00 Page 1 of 20 October 30, 2007

Page 3

HI-506A, HI-507A, HI-508A, HI-509AOrdering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HI1-0506A-2 HI1-506A-2 -55 to +125 28 Ld CERDIP F28.6 HI1-0506A-5 HI1-506A-5 0 to +75 28 Ld CERDIP F28.6 HI1-0506A-8 HI1-506A-8 -55 to +125 + 160 Hour Burn-In 28 Ld CERDIP F28.6 HI3-0506A-5 HI3-506A-5 0 to +75 28 Ld PDIP E28.6 HI3-0506A-5Z (Note 1) HI3-506A-5Z 0 to +75 28 Ld PDIP (Note 2) (Pb-free) E28.6 HI3-0507A-5 HI3-507A-5 0 to +75 28 Ld PDIP E28.6 HI3-0507A-5Z (Note 1) HI3-507A-5Z 0 to +75 28 Ld PDIP (Note 2) (Pb-free) E28.6 HI1-0508A-8 HI1-508A-8 -55 to +125 + 160 Hour Burn-In 16 Ld CERDIP F16.3 HI3-0508A-5 HI3-508A-5 0 to +75 16 Ld PDIP E16.3 HI3-0508A-5Z (Note 1) HI3-508A-5Z 0 to +75 16 Ld PDIP (Note 2) (Pb-free) E16.3 HI1-0509A-2 HI1-509A-2 -55 to +125 16 Ld CERDIP F16.3 HI1-0509A-5 HI1-509A-5 0 to +75 16 Ld CERDIP F16.3 HI1-0509A-8 HI1-509A-8 -55 to +125 + 160 Hour Burn-In 16 Ld CERDIP F16.3 HI3-0509A-5 HI3-509A-5 0 to +75 16 Ld PDIP E16.3 HI3-0509A-5Z (Note 1) HI3-509A-5Z 0 to +75 16 Ld PDIP (Note 2) (Pb-free) E16.3 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.FN3143 Rev.6.00 Page 2 of 20 October 30, 2007

Page 4

HI-506A, HI-507A, HI-508A, HI-509APinouts HI-506A (CERDIP, PDIP) TOP VIEW HI-507A (PDIP) TOP VIEW HI-508A (CERDIP, PDIP) TOP VIEW HI-509A (CERDIP, PDIP) TOP VIEW +VSUPPLY NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND VREF ADDRESS A3 OUT IN 8 IN 7 IN 6 IN 5 IN 3 IN 1 ENABLE ADDRESS A0 ADDRESS A1 ADDRESS A2 -VSUPPLY IN 4 IN 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +VSUPPLY OUT B NC IN 8B IN 7B IN 6B IN 5B IN 4B IN 3B IN 2B IN 1B GND VREF NC OUT A IN 8A IN 7A IN 6A IN 5A IN 3A IN 1A ENABLE ADDRESS A0 ADDRESS A1 ADDRESS A2 -VSUPPLY IN 4A IN 2A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 A0 ENABLE -VSUPPLY IN 1 IN 2 IN 3 OUT IN 4 A1 GND +VSUPPLY IN 5 IN 6 IN 7 IN 8 A2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 A0 ENABLE -VSUPPLY IN 1A IN 2A IN 3A OUT A IN 4A A1 +VSUPPLY IN 1B IN 2B IN 3B IN 4B OUT B GNDFN3143 Rev.6.00 Page 3 of 20 October 30, 2007

Page 5

HI-506A, HI-507A, HI-508A, HI-509ATruth Tables HI-506A A3 A2 A1 A0 EN “ON” CHANNEL X X X X L None L L L L H 1 L L L H H 2 L L H L H 3 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 HI-507A A2 A1 A0 EN “ON” CHANNEL PAIR X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 HI-508A A2 A1 A0 EN “ON” CHANNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 HI-509A A1 A0 EN “ON” CHANNEL PAIR X X L None L L H 1 L H H 2 H L H 3 H H H 4FN3143 Rev.6.00 Page 4 of 20 October 30, 2007

Page 6

HI-506A, HI-507A, HI-508A, HI-509AFunctional Diagrams HI-506A HI-507A HI-508A HI-509A DECODER/ DRIVER † † † † OUT IN 1 IN 2 IN 16 PROTECTION A0 A1 A2 A3 † EN † DIGITAL INPUT LEVEL SHIFT 5V REF VREF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 1k 1k 1k DECODER/ DRIVER † † † OUT IN 1A IN 8A IN 1B PROTECTION A0 A1 A2 † EN † DIGITAL INPUT LEVEL SHIFT 5V REF VREF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 1k 1k 1k IN 8B 1k A OUT B DECODER/ DRIVER † † † OUT IN 1 IN 2 IN 8 PROTECTION A0 A1 A2 † EN † DIGITAL INPUT LEVEL SHIFT 5V REF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 1k 1k 1k DECODER/ DRIVER † † OUT IN 1A IN 4A IN 1B PROTECTION A0 A1 † EN † DIGITAL INPUT LEVEL SHIFT 5V REF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 1k 1k 1k IN 4B 1k A OUT B FN3143 Rev.6.00 Page 5 of 20 October 30, 2007

Page 7

HI-506A, HI-507A, HI-508A, HI-509ASchematic Diagrams ADDRESS INPUT BUFFER AND LEVEL SHIFTER ADDRESS DECODER LEVEL SHIFTER P N P N N P N P VREF ADD IN N P N P P N P N N P N P LEVEL SHIFTED ADDRESS TO TTL REFERENCE CIRCUIT V+ R10 R9 Q1 Q4 D3 GND OVERVOLTAGE PROTECTION D2 R1 200 V-  D1 V+ R2 R3 GND V+ V- DECODER4 R5 R7 R8R6 P N A0 OR A0 TO N-CHANNEL DEVICE OF THE SWITCH A1 OR A1 A2 OR A2 A3 OR A3 ENABLE P P P P P P V+ V- N N N N N N TO P-CHANNEL DEVICE OF THE SWITCH DELETE A3 OR A3 INPUT FOR HI-507A, HI-508A, HI-509A DELETE A2 OR A2 INPUT FOR HI-509AFN3143 Rev.6.00 Page 6 of 20 October 30, 2007

Page 8

HI-506A, HI-507A, HI-508A, HI-509AMULTIPLEX SWITCH Schematic Diagrams (Continued) FROM DECODE N N V+ OUTIN FROM DECODE OVERVOLTAGE PROTECTION P D6R11 1k V- D7 D4 D5 Q6 N P Q5FN3143 Rev.6.00 Page 7 of 20 October 30, 2007

Page 9

HI-506A, HI-507A, HI-508A, HI-509AAbsolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V or 20mA, Whichever Occurs First Analog Signal (VIN, VOUT) . . . . . . . . . . . . . . (V-) -20V to (V+) +20V Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, IN or OUT, Pulsed 1ms, 10% Duty Cycle (Max) . . 40mA Operating Conditions Temperature Ranges HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . .-55°C to +125°C HI-506A/507A/508A/509A-5. . . . . . . . . . . . . . . . . . . 0°C to +75°C Thermal Resistance (Typical, Note 3) JA (°C/W) JC (°C/W) 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 16 Ld CERDIP Package. . . . . . . . . . . . 75 22 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature CERDIP Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. PARAMETER TEST CONDITIONS TEMP (°C) -2, -8 -5 UNITS MIN (Note 12) TYP MAX (Note 12) MIN (Note 12) TYP MAX (Note 12) DYNAMIC CHARACTERISTICS Access Time, tA Note 4 25 - 0.5 - - 0.5 - s Full - - 1.0 - - 1.0 s Break-Before-Make Delay, tOPEN Note 4 25 25 80 - 25 80 - ns Enable Delay (ON), tON(EN) Note 4 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns Enable Delay (OFF), tOFF(EN) Note 4 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns Settling Time, tS HI-506A and HI-507A To 0.1% 25 - 1.2 - - 1.2 - s To 0.01% 25 - 3.5 - - 3.5 - s HI-508A and HI-509A To 0.1% 25 - 1.2 - - 1.2 - s To 0.01% 25 - 3.5 - - 3.5 - s Off Isolation Note 9 25 - 68 - - 68 - dB Channel Input Capacitance, CS(OFF) 25 - 10 - - 10 - pF Channel Output Capacitance, CD(OFF) HI-506A 25 - 52 - - 52 - pF HI-507A 25 - 30 - - 30 - pF HI-508A 25 - 25 - - 25 - pF HI-509A 25 - 12 - - 12 - pF Digital Input Capacitance, CA 25 - 10 - - 10 - pF Input to Output Capacitance, CDS(OFF) 25 - 0.1 - - 0.1 - pF DIGITAL INPUT CHARACTERISTICS Input Low Threshold, TTL Drive, VAL Note 4 Full - - 0.8 - - 0.8 V Input High Threshold, VAH (Note 11) Note 4 Full 4.0 - - 4.0 - - VFN3143 Rev.6.00 Page 8 of 20 October 30, 2007

Page 10

HI-506A, HI-507A, HI-508A, HI-509AInput Leakage Current (High or Low), IA Notes 4, 8 Full - - 1.0 - - 1.0 A MOS Drive, VAL, HI-506A/HI-507A VREF = +10V 25 - - 0.8 - - 0.8 V MOS Drive, VAH, HI-506A/HI-507A VREF = +10V 25 6.0 - - 6.0 - - V ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN Note 4 Full -15 - +15 -15 - +15 V On Resistance, rON Notes 4, 5 25 - 1.2 1.5 - 1.5 1.8 k Full - 1.5 1.8 - 1.8 2.0 k Off Input Leakage Current, IS(OFF) Notes 4, 6 25 - 0.03 - - 0.03 - nA Full - - 50 - - 50 nA Off Output Leakage Current, ID(OFF) Notes 4, 6 25 - 0.1 - - 0.1 - nA HI-506A Full - - 300 - - 300 nA HI-507A Full - - 200 - - 200 nA HI-508A Full - - 200 - - 200 nA HI-509A Full - - 100 - - 100 nA ID(OFF) With Input Overvoltage Applied Note 7 25 - 4.0 - - 4.0 - nA Full - - 2.0 - - - A On Channel Leakage Current, ID(ON) Notes 4, 6 25 - 0.1 - - 0.1 - nA HI-506A Full - - 300 - - 300 nA HI-507A Full - - 200 - - 200 nA HI-508A Full - - 200 - - 200 nA HI-509A Full - - 100 - - 100 nA Differential Off Output Leakage Current, IDIFF, (HI-507A, HI-509A Only) Full - - 50 - - 50 nA POWER SUPPLY CHARACTERISTICS Current, I+ Notes 4, 10 Full - 0.5 2.0 - 0.5 2.0 mA Current, I- Notes 4, 10 Full - 0.02 1.0 - 0.02 1.0 mA Power Dissipation, PD Full - 7.5 - - 7.5 - mW NOTES: 4. 100% tested for Dash 8. Leakage currents not tested at -55°C. 5. VOUT = 10V, IOUT = +100A. 6. 10nA is the practical lower limit for high speed measurement in the production test environment. 7. Analog Overvoltage = 33V. 8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25°C. 9. VEN = 0.8V, RL = 1k, CL = 15pF, VS = 7VRMS, f = 100kHz. 10. VEN, VA = 0V or 4V. 11. To drive from DTL/TTL Circuits, 1k pull-up resistors to +5V supply are recommended. 12. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. (Continued) PARAMETER TEST CONDITIONS TEMP (°C) -2, -8 -5 UNITS MIN (Note 12) TYP MAX (Note 12) MIN (Note 12) TYP MAX (Note 12)FN3143 Rev.6.00 Page 9 of 20 October 30, 2007

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