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HIP4080AIBZ

hot HIP4080AIBZ

HIP4080AIBZ

For Reference Only

Part Number HIP4080AIBZ
Manufacturer Intersil
Description IC DRIVER FULL-BRIDGE 20-SOIC
Datasheet HIP4080AIBZ Datasheet
Package 20-SOIC (0.295", 7.50mm Width)
In Stock 360 piece(s)
Unit Price $ 5.41 *
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HIP4080AIBZ

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HIP4080AIBZ Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - PMIC - Gate Drivers
Datasheet HIP4080AIBZ Datasheet
Package20-SOIC (0.295", 7.50mm Width)
Series-
Driven ConfigurationHalf-Bridge
Channel TypeSynchronous
Number of Drivers4
Gate TypeN-Channel MOSFET
Voltage - Supply9.5 V ~ 15 V
Logic Voltage - VIL, VIH1V, 2.5V
Current - Peak Output (Source, Sink)2.6A, 2.4A
Input TypeNon-Inverting
High Side Voltage - Max (Bootstrap)95V
Rise / Fall Time (Typ)10ns, 10ns
Operating Temperature-40°C ~ 125°C (TJ)
Mounting TypeSurface Mount
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC

HIP4080AIBZ Datasheet

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Page 2

FN3658 Rev.7.00 July 2004 HIP4080A 80V/2.5A Peak, High Frequency Full Bridge FET Driver DATASHEETThe HIP4080A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4080A includes an input comparator, used to facilitate the “hysteresis” and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the HIP4080A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. HIP4080A can also drive medium voltage brush motors, and two HIP4080As can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. The similar HIP4081A IC allows independent control of all 4 FETs in a Full Bridge configuration. The Application Note for the HIP4080A is AN9404. Features • Drives N-Channel FET Full Bridge Including High Side Chop Capability • Bootstrap Supply Max Voltage to 95VDC • Drives 1000pF Load at 1MHz in Free Air at +50°C with Rise and Fall Times of Typically 10ns • User-Programmable Dead Time • Charge-Pump and Bootstrap Maintain Upper Bias Supplies • DIS (Disable) Pin Pulls Gates Low • Input Logic Thresholds Compatible with 5V to 15V Logic Levels • Very Low Power Consumption • Undervoltage Protection • Pb-Free Available as an Option Applications • Medium/Large Voice Coil Motors • Full Bridge Power Supplies • Switching Power Amplifiers • High Performance Motor Controls • Noise Cancellation Systems • Battery Powered Vehicles • Peripherals • U.P.S. Pinout HIP4080A (PDIP, SOIC) TOP VIEW Ordering Information PART NUMBER TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # HIP4080AIPZ (Note 1) -40 to +85 20 Ld PDIP (Pb-Free) E20.3 HIP4080AIP -40 to +85 20 Ld PDIP E20.3 HIP4080AIB -40 to +85 20 Ld SOIC M20.3 HIP4080AIBZ (Note 1) -40 to +85 20 Ld SOIC (Pb-Free) M20.3 NOTES: 1. Intersil Pb-Free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-Free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 2. Add “T” suffix for Tape and Reel packing option. HIP4080AIP not available in Tape and Reel. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1BHB HEN DIS VSS OUT IN+ HDEL IN- LDEL AHB BHO BLO BLS VDD BHS VCC ALS ALO AHS AHOFN3658 Rev.7.00 Page 1 of 17 July 2004

Page 3

HIP4080AApplication Block Diagram Functional Block Diagram (1/2 HIP4080A) 80V GND HIP4080A GND 12V LOAD BHO BHS BLO ALO AHS AHO IN- IN+ DIS HEN CHARGE PUMP VDD HEN DIS OUT IN+ IN_ HDEL LDEL VSS TURN-ON DELAY + - TURN-ON DELAY DRIVER DRIVER AHB AHO AHS VCC ALO ALS CBF TO VDD (PIN 16) CBS DBS HIGH VOLTAGE BUS  80VDC +12VDC LEVEL SHIFT AND LATCH 14 10 11 12 15 13 16 2 3 5 6 7 8 9 4 BIAS SUPPLY UNDER- VOLTAGEFN3658 Rev.7.00 Page 2 of 17 July 2004

Page 4

HIP4080ATypical Application (Hysteresis Mode Switching) 6V 80V 12V 12V DIS IN GND 6V GND + - 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 BHB HEN DIS VSS OUT IN+ HDEL IN- LDEL AHB BHO BLO BLS VDD BHS VCC ALS ALO AHS AHO LOAD H IP 4 08 0 A /H IP 40 8 0 FN3658 Rev.7.00 Page 3 of 17 July 2004

Page 5

HIP4080AAbsolute Maximum Ratings Thermal Information Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25°C to 125°C) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55°C to 125°C) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns All Voltages relative to VSS, unless otherwise specified. Operating Conditions Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . .VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500A to -50A Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C Thermal Resistance (Typical, Note 3) JA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Power Dissipation at +85°C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125°C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C (For SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25°C, Unless Otherwise Specified PARAMETERS SYMBOL TEST CONDITIONS TJ = +25°C TJ = - 40°C TO +125°C UNITSMIN TYP MAX MIN MAX SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current IDD IN- = 2.5V, Other Inputs = 0V 8 11 14 7 14 mA VDD Operating Current IDDO Outputs switching f = 500kHz, No Load 9 12 15 8 15 mA VCC Quiescent Current ICC IN- = 2.5V, Other Inputs = 0V, IALO = IBLO = 0 - 25 80 - 100 A VCC Operating Current ICCO f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA AHB, BHB Quiescent Current - Qpump Output Current IAHB, IBHB IN- = 2.5V, Other Inputs = 0V, IAHO = IBHO = 0, VDD = VCC =VAHB = VBHB = 10V -50 -25 -11 -60 -10 A AHB, BHB Operating Current IAHBO, IBHBO f = 500kHz, No Load 0.62 1.2 1.5 0.5 1.9 mA AHS, BHS, AHB, BHB Leakage Current IHLK VBHS = VAHS = 80V, VAHB = VBHB = 93V - 0.02 1.0 - 10 A AHB-AHS, BHB-BHS Qpump Output Voltage VAHB - VAHS VBHB - VBHS IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage VOS Over Common Mode Voltage Range -10 0 +10 -15 +15 mV Input Bias Current IIB 0 0.5 2 0 4 A Input Offset Current IOS -1 0 +1 -2 +2 A Input Common Mode Voltage Range CMVR 1 - VDD -1.5 1 VDD -1.5 V FN3658 Rev.7.00 Page 4 of 17 July 2004

Page 6

HIP4080AVoltage Gain AVOL 10 25 - 10 - V/mV OUT High Level Output Voltage VOH IN+ > IN-, IOH = -250A VDD -0.4 - - VDD - 0.5 - V OUT Low Level Output Voltage VOL IN+ < IN-, IOL = +250A - - 0.4 - 0.5 V Low Level Output Current IOL VOUT = 6V 6.5 14 19 6 20 mA High Level Output Current IOH VOUT = 6V -17 -10 -3 -20 -2.5 mA INPUT PINS: DIS Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V Input Voltage Hysteresis - 35 - - - mV Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 A High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 A INPUT PINS: HEN Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V Input Voltage Hysteresis - 35 - - - mV Low Level Input Current IIL VIN = 0V, Full Operating Conditions -260 -200 -150 -270 -130 A High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 A TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL,V IHDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V High Level Output Voltage VCC - VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V Peak Pullup Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A Peak Pulldown Current IO- VOUT = 12V 1.7 2.4 3.3 1.3 3.6 A Under Voltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V Under Voltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V Under Voltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25°C, Unless Otherwise Specified (Continued) PARAMETERS SYMBOL TEST CONDITIONS TJ = +25°C TJ = - 40°C TO +125°C UNITSMIN TYP MAX MIN MAXFN3658 Rev.7.00 Page 5 of 17 July 2004

Page 7

HIP4080ASwitching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF, and TA = +25°C, Unless Otherwise Specified PARAMETERS SYMBOL TEST CONDITIONS TJ = +25°C TJ = - 40°C TO +125°C UNITSMIN TYP MAX MIN MAX Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) TLPHL - 40 70 - 90 ns Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) THPHL - 50 80 - 110 ns Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) TLPLH - 40 70 - 90 ns Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) THPLH - 70 110 - 140 ns Rise Time TR - 10 25 - 35 ns Fall Time TF - 10 25 - 35 ns Turn-on Input Pulse Width TPWIN-ON 50 - - 50 - ns Turn-off Input Pulse Width TPWIN-OFF 40 - - 40 - ns Disable Turn-off Propagation Delay (DIS - Lower Outputs) TDISLOW - 45 75 - 95 ns Disable Turn-off Propagation Delay (DIS - Upper Outputs) TDISHIGH - 55 85 - 105 ns Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) TDLPLH - 45 70 - 90 ns Refresh Pulse Width (ALO and BLO) TREF-PW 240 380 500 200 600 ns Disable to Upper Enable (DIS - AHO and BHO) TUEN - 480 630 - 750 ns HEN-AHO, BHO Turn-off, Propagation Delay THEN-PHL RHDEL = RLDEL = 10K - 40 70 - 90 ns HEN-AHO, BHO Turn-on, Propagation Delay THEN-PLH RHDEL = RLDEL = 10K - 60 90 - 110 ns TRUTH TABLE INPUT OUTPUT IN+ > IN- HEN U/V DIS ALO AHO BLO BHO X X X 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 1 0 X X 1 X 0 0 0 0FN3658 Rev.7.00 Page 6 of 17 July 2004

Page 8

HIP4080APin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 4 VSS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. 16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.FN3658 Rev.7.00 Page 7 of 17 July 2004

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HIP4080ATiming Diagrams FIGURE 1. BISTATE MODE FIGURE 2. HIGH SIDE CHOP MODE FIGURE 3. DISABLE FUNCTION 0 HEN ALO AHO BLO TLPHL THPLH TR (10% - 90%) TF (90% - 10%) TDT U/V = DIS THPHL TLPLH TDT 1 IN+ > IN- BHO 0 HEN ALO AHO BLO U/V = DIS THEN-PLHTHEN-PHL IN+ > IN- BHO HEN AHO BLO U/V or DIS TREF-PW TDLPLH IN+ > IN- BHO TDIS TUEN ALOFN3658 Rev.7.00 Page 8 of 17 July 2004

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HIP4080ATypical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25°C, Unless Otherwise Specified FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE FIGURE 5. IDDO NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF) FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERATURE AT VCM = 5V 8 10 12 14 2.0 4.0 6.0 8.0 10.0 12.0 14.0 I D D S U P P LY C U R R E N T ( m A ) VDD SUPPLY VOLTAGE (V) 13 12.5 12.0 11.5 11.0 10.5 10 200 400 600 800 1000 I D D S U P P LY C U R R E N T ( m A ) SWITCHING FREQUENCY (kHz) 0 100 200 300 400 500 600 700 800 900 1000 0.0 5.0 10.0 15.0 20.0 F L O A T IN G S U P P LY B IA S C U R R E N T ( m A ) SWITCHING FREQUENCY (kHz) 0 100 200 300 400 500 600 700 800 900 1000 0.0 1.0 2.0 3.0 4.0 5.0 I C C S U P P LY C U R R E N T ( m A ) SWITCHING FREQUENCY (kHz) +75°C +25°C +125°C -40°C 0°C 0.5 1 1.5 2 2.5 200 600 800 10000 400 F L O A T IN G S U P P LY B IA S C U R R E N T ( m A ) SWITCHING FREQUENCY (kHz) -40 -20 0 20 40 60 80 100 120 0.5 1.0 C O M P A R A T O R I N P U T C U R R E N T ( A ) JUNCTION TEMPERATURE (°C)FN3658 Rev.7.00 Page 9 of 17 July 2004

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