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Part Number HIP6004ECBZ-T
Manufacturer Intersil
Datasheet HIP6004ECBZ-T Datasheet
Package 20-SOIC (0.295", 7.50mm Width)
In Stock 14,294 piece(s)
Unit Price $ 2.7160 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 21 - Sep 26 (Choose Expedited Shipping)
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Part Number # HIP6004ECBZ-T (PMIC - Voltage Regulators - Special Purpose) is manufactured by Intersil and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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HIP6004ECBZ-T Specifications

CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Special Purpose
Datasheet HIP6004ECBZ-TDatasheet
Package20-SOIC (0.295", 7.50mm Width)
ApplicationsController, Intel VRM8.5
Voltage - Input5V, 12V
Number of Outputs1
Voltage - Output1.05 V ~ 1.825 V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package-

HIP6004ECBZ-T Datasheet

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FN4997 Rev 3.00 November 10, 2015 HIP6004E Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor DATASHEETThe HIP6004E provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N-Channel MOSFETs in a synchronous-rectified buck topology. The HIP6004E integrates all of the control, output adjustment, monitoring and protection functions into a single package. The output voltage of the converter is easily adjusted and precisely regulated. The HIP6004E includes a 5-input digital- to-analog converter (DAC) that adjusts the output voltage from 1.05VDC to 1.825VDC in 25mV increments steps. The precision reference and voltage-mode regulator hold the selected output voltage to within 1% over temperature and line voltage variations. The HIP6004E provides simple, single feedback loop, voltage-mode control with fast transient response. It includes a 200kHz free-running triangle-wave oscillator that is adjustable from below 50kHz to over 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The HIP6004E monitors the output voltage with a window comparator that tracks the DAC output and issues a Power Good signal when the output is within 10%. The HIP6004E protects against over-current and overvoltage conditions by inhibiting PWM operation. Additional built-in overvoltage protection triggers an external SCR to crowbar the input supply. The HIP6004E monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. Pinout HIP6004E TOP VIEW Features • Drives two N-Channel MOSFETs • Operates from +5V or +12V Input • Simple single-loop control design - Voltage-mode PWM control • Fast transient response - High-bandwidth error amplifier - Full 0% to 100% Duty Ratio • Excellent output voltage regulation - 1% Over Line Voltage and Temperature • 5-Bit digital-to-analog output Voltage Selection - 25mV binary steps . . . . . . . . . . . 1.05VDC to 1.825VDC • Power good output voltage monitor • Overvoltage and overcurrent fault monitors - Does not require extra current sensing element, Uses MOSFET’s rDS(ON) • Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to over 1MHz • Pb-free available Applications • VRM8.5 modules for Pentium III and Other Microprocessors • High-Power DC-DC Regulators • Low-Voltage Distributed Power Supplies Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1VSEN OCSET SS VID25mV VID0 VID1 VID3 VID2 COMP FB RT VCC LGATE PGND OVP BOOT UGATE PHASE PGOOD GNDFN4997 Rev 3.00 Page 1 of 14 November 10, 2015

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HIP6004ETypical Application Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # HIP6004ECBZ (See Note) 0 to 70 20 Ld SOIC (Pb-free) M20.3 HIP6004ECVZ (See Note) No longer available or supported, recommended replacement HIP6004ECBZ 0 to 70 20 Ld TSSOP (Pb-free) M20.173 *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. +12V +VOUT PGND HIP6004E VSEN RT FB COMP VID25mV VID0 VID1 VID2 SS PGOOD D/A GND OSC LGATE UGATE OCSET PHASE BOOT VCC VIN = +5V OR +12V OVP MONITOR AND PROTECTION + - + -VID3FN4997 Rev 3.00 Page 2 of 14 November 10, 2015

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HIP6004EAbsolute Maximum Ratings Thermal Information Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V Boot voltage, VBOOT - VPHASE. . . . . . . . . . . . . . . . . . . . . . . . .+15V Input, output or I/O voltage . . . . . . . . . . . .GND -0.3V to VCC +0.3V ESD classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Operating Conditions Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient temperature range . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Thermal resistance (Typical, Note 1) JA (oC/W) SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum storage temperature range . . . . . . . . . . . -65oC to 150oC Maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300oC (lead tips only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended operating conditions, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Nominal supply ICC UGATE and LGATE open - 5 - mA POWER-ON RESET Rising VCC threshold VOCSET = 4.5V - - 10.4 V Falling VCC threshold VOCSET = 4.5V 8.2 - - V Rising VOCSET threshold - 1.26 - V OSCILLATOR Free running frequency RT = open 185 200 215 kHz Total variation 6k < RT to GND < 200k -15 - +15 % Ramp amplitude VOSC RT = open - 1.9 - VP-P REFERENCE AND DAC DAC (VID0-VID4) input low voltage - - 0.8 V DAC (VID0-VID4) input high voltage 2.0 - - V DACOUT voltage accuracy -1.0 - +1.0 % ERROR AMPLIFIER DC gain - 88 - dB Gain-bandwidth product GBWP - 15 - MHz Slew rate SR COMP = 10pF - 6 - V/s GATE DRIVERS Upper gate source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V 350 500 - mA Upper gate sink RUGATE ILGATE = 0.3A - 5.5 10  Lower gate source ILGATE VCC = 12V, VLGATE = 6V 300 450 - mA Lower gate sink RLGATE ILGATE = 0.3A - 3.5 6.5  PROTECTION Overvoltage trip (VSEN/DACOUT) - 115 120 % OCSET current source IOCSET VOCSET = 4.5VDC 170 200 230 A OVP sourcing current IOVP VSEN = 5.5V, VOVP = 0V 60 - - mA Soft start current ISS - 10 - A POWER GOOD Upper threshold (VSEN/DACOUT) VSEN rising 106 - 111 % Lower threshold (VSEN/DACOUT) VSEN falling 89 - 94 % Hysteresis (VSEN/DACOUT) Upper and lower threshold - 2 - % PGOOD voltage low VPGOOD IPGOOD = -5mA - 0.3 - VFN4997 Rev 3.00 Page 4 of 14 November 10, 2015

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HIP6004EFunctional Pin Descriptions VSEN (Pin 1) This pin is connected to the converter’s output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. OCSET (Pin 2) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200A current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation: An over-current trip cycles the soft-start function. SS (Pin 3) Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A current source, sets the soft-start interval of the converter. VID25mV-VID3 (Pins 4-8) VID25mV - VID3 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the converter output voltage. It also sets the PGOOD and OVP thresholds. Table 1 specifies DACOUT for the all combinations of DAC inputs. COMP (Pin 9) and FB (Pin 10) COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. GND (Pin 11) Signal ground for the IC. All voltage levels are measured with respect to this pin. PGOOD (Pin 12) PGOOD is an open collector output used to indicate the status of the converter output voltage. This pin is pulled low when the converter output is not within 10%of the DACOUT reference voltage. PHASE (Pin 13) Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for overcurrent protection. This pin also provides the return path for the upper gate drive. UGATE (Pin 14) Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. BOOT (Pin 15) This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. PGND (Pin 16) This is the power ground connection. Tie the lower MOSFET source to this pin. Typical Performance Curves FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY 10 100 1000 SWITCHING FREQUENCY (kHz) R E S IS TA N C E ( k  ) 10 100 1000 RT PULLUP TO +12V RT PULLDOWN TO VSS 100 200 300 400 500 600 700 800 900 1000 I C C ( m A ) SWITCHING FREQUENCY (kHz) CGATE = 3300pF CGATE = 1000pF CGATE = 10pF CUPPER = CLOWER = CGATE 80 70 60 50 40 30 20 10 0 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1VSEN OCSET SS VID25mV VID0 VID1 VID3 VID2 COMP FB RT VCC LGATE PGND OVP BOOT UGATE PHASE PGOOD GND IPEAK IOCSET x ROCSET rDS ON  ----------------------------------------------------=FN4997 Rev 3.00 Page 5 of 14 November 10, 2015

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HIP6004ELGATE (Pin 17) Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. VCC (Pin 18) Provide a 12V bias supply for the chip to this pin. OVP (Pin 19) The OVP pin can be used to drive an external SCR in the event of an overvoltage condition. Output rising 15% more than the DAC-set voltage triggers a high output on this pin and disables PWM gate drive circuitry. RT (Pin 20) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation: RT pin has a constant voltage of 1.26V typically. Functional Description Initialization The HIP6004E automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft-start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation. Soft Start The POR function initiates the soft-start sequence. An internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 3 shows the soft-start interval with CSS = 0.1F. Initially the clamp on the error amplifier (COMP pin) controls the converter’s output voltage. At t1 in Figure 3, the SS voltage reaches the valley of the oscillator’s triangle wave. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 3. At t3 the SS voltage exceeds the DACOUT voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The PGOOD signal toggles ‘high’ when the output voltage (VSEN pin) is within 10% of DACOUT. The 2% hysteresis built into the power good comparators prevents PGOOD oscillation due to nominal output voltage ripple. Overcurrent Protection The overcurrent function protects the converter from a shorted output by using the upper MOSFET’s on-resistance, rDS(ON) to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level. An internal 200A current sink develops a voltage across ROCSET that is referenced to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET, the overcurrent function initiates a soft-start sequence. The soft-start function discharges CSS with a 10A current sink and inhibits PWM Fs 200kHz 5 x 10 6 RT k  --------------------+ (RT to GND) Fs 200kHz 4 x 10 7 RT k  --------------------– (RT to 12V) 0V 0V 0V TIME (5ms/DIV.) SOFT-START (1V/DIV.) OUTPUT (1V/DIV.) VOLTAGE t2 t3 PGOOD (2V/DIV.) t1 FIGURE 3. SOFT START INTERVAL O U T P U T I N D U C T O R S O F T -S TA R T 0A 0V TIME (20ms/DIV.) 5A 10A 15A 2V 4V FIGURE 4. OVER-CURRENT OPERATIONFN4997 Rev 3.00 Page 6 of 14 November 10, 2015

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HIP6004Eoperation. The soft-start function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft-start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 4 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an overcurrent trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 4 is 2.5W. The overcurrent function will trip at a peak inductor current (IPEAK) determined by: where IOCSET is the internal OCSET current source (200A typical). The OC trip point varies mainly due to the MOSFET’s rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for , where I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled “Output Inductor Selection”. A small, ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Output Voltage Program The output voltage of a HIP6004E converter is programmed to discreet levels between 1.05VDC and 1.825VDC. The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a TTL-compatible 5-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the 32 different combinations of connections on the VID pins. The output voltage should not be adjusted while the converter is delivering power. Remove input power before changing the output voltage. Adjusting the output voltage during operation could toggle the PGOOD signal and exercise the overvoltage protection. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short-printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. IPEAK IOCSET x ROCSET rDS ON  ----------------------------------------------------= IPEAK IOUT MAX  I  2+ TABLE 1. OUTPUT VOLTAGE PROGRAM PIN NAME NOMINAL OUTPUT VOLTAGE DACOUT PIN NAME NOMINAL OUTPUT VOLTAGE DACOUT VID25 mV VID3 VID2 VID1 VID0 VID25 mV VID3 VID2 VID1 VID0 0 0 1 0 0 1.050 0 1 1 0 0 1.450 1 0 1 0 0 1.075 1 1 1 0 0 1.475 0 0 0 1 1 1.100 0 1 0 1 1 1.500 1 0 0 1 1 1.125 1 1 0 1 1 1.525 0 0 0 1 0 1.150 0 1 0 1 0 1.550 1 0 0 1 0 1.175 1 1 0 1 0 1.575 0 0 0 0 1 1.200 0 1 0 0 1 1.600 1 0 0 0 1 1.225 1 1 0 0 1 1.625 0 0 0 0 0 1.250 0 1 0 0 0 1.650 1 0 0 0 0 1.275 1 1 0 0 0 1.675 0 1 1 1 1 1.300 0 0 1 1 1 1.700 1 1 1 1 1 1.325 1 0 1 1 1 1.725 0 1 1 1 0 1.350 0 0 1 1 0 1.750 1 1 1 1 0 1.375 1 0 1 1 0 1.775 0 1 1 0 1 1.400 0 0 1 0 1 1.800 1 1 1 0 1 1.425 1 0 1 0 1 1.825 NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors or leave the pins floating. Internal pull-ups will force the floating VID pins to HIGH.FN4997 Rev 3.00 Page 7 of 14 November 10, 2015

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HIP6004EFigure 5 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 5 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the HIP6004E within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the HIP6004E must be sized to handle up to 1A peak current. Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS pin and locate the capacitor, CSS close to the SS pin because the internal current source is only 10A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC. Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the HIP6004E) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC). 3. Place 2ND Zero at Filter’s Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier’s Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary. PGND LO COLGATE UGATE PHASE Q1 Q2 D2 VIN VOUT RETURN HIP6004E CIN L O A D FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES +12V HIP6004E SS GND VCC BOOT D1 LO CO VOUT L O A D Q1 Q2 PHASE +VIN CBOOT CVCCCSS FIGURE 7. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN VOUT REFERENCE LO CO ESR VIN VOSC ERROR AMP PWM DRIVER (PARASITIC) ZFB + - DACOUT R1 R3R2 C3 C2 C1 COMP VOUT FB ZFB HIP6004E ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN OSC FLC 1 2 x LO x CO ------------------------------------------= FESR 1 2 x ESR x CO -------------------------------------------=FN4997 Rev 3.00 Page 8 of 14 November 10, 2015

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HIP6004ECompensation Break Frequency Equations Figure 8 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low ESR capacitors intended for switching- regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large- case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6004E will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: FZ1 1 2 x R2 x C1 -----------------------------------= FZ2 1 2 x R1 R3+  x C3 ------------------------------------------------------= FP1 1 2 x R2 x C1 x C2 C1 C2+ ---------------------       --------------------------------------------------------= FP2 1 2 x R3 x C3 -----------------------------------= 100 80 60 40 20 0 -20 -40 -60 FP1FZ2 10M1M100K10K1K10010 OPEN LOOP ERROR AMP GAIN FZ1 FP2 20LOG FLC FESR COMPENSATION G A IN ( d B ) FREQUENCY (Hz) GAIN 20LOG (VIN/VOSC) MODULATOR GAIN (R2/R1) FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN CLOSED LOOP GAIN I = VIN - VOUT Fs x L VOUT VIN VOUT = I x ESRx tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUTFN4997 Rev 3.00 Page 9 of 14 November 10, 2015

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August 16, 2020

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August 14, 2020

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July 16, 2020

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