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IRU3011CW

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IRU3011CW

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Part Number IRU3011CW
Manufacturer Infineon Technologies
Description IC CTRL SYNC BUCK 5BIT 20-SOIC
Datasheet IRU3011CW Datasheet
Package 20-SOIC (0.295", 7.50mm Width)
In Stock 3,700 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 24 - Sep 29 (Choose Expedited Shipping)
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Part Number # IRU3011CW (PMIC - Voltage Regulators - Special Purpose) is manufactured by Infineon Technologies and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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IRU3011CW Specifications

ManufacturerInfineon Technologies
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Special Purpose
Datasheet IRU3011CWDatasheet
Package20-SOIC (0.295", 7.50mm Width)
Series-
ApplicationsController, Intel Pentium? III
Voltage - Input5V, 12V
Number of Outputs1
Voltage - Output1.3 V ~ 3.5 V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC

IRU3011CW Datasheet

Page 1

Page 2

IRU3011 1Rev. 1.608/20/02 www.irf.com TYPICAL APPLICATION DESCRIPTION The IRU3011 controller IC is specifically designed to meet Intel specification for latest Pentium III microproces- sor applications as well as the next generation P6 fam- ily processors. These products feature a patented topol- ogy that in combination with a few external components as shown in the typical application circuit,will provide in excess of 20A of output current for an on-board DC/DC converter while automatically providing the right output voltage via the 5-bit internal DAC. These devices also features, loss less current sensing by using the RDS(ON) of the high side Power MOSFET as the sensing resis- tor, a Power Good window comparator that switches its open collector output low when the output is outside of a ±10% window and an Over-Voltage Protection output. Other features of the device are: Under-voltage lockout for both 5V and 12V supplies, an external programmable soft-start function as well as programming the oscillator frequency by using an external capacitor. Dual Layout compatible with HIP6004A Designed to meet Intel specification of VRM8.4 for Pentium III On-Board DAC programs the output voltage from 1.3V to 3.5V. The IRU3011 remains on for VID code of (11111). Loss-less Short Circuit Protection Synchronous operation allows maximum efficiency Patented architecture allows fixed frequency operation as well as 100% duty cycle during dynamic load Over-Voltage Protection Output Soft-Start High current totem pole driver for direct driving of the external power MOSFET Power Good Function PACKAGE ORDER INFORMATION FEATURES 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC APPLICATIONS Pentium III & Pentium II processor DC to DC converter application Low Cost Pentium with AGP Note: Pentium II and Pentium III are trade marks of Intel Corp. TA (8C) DEVICE PACKAGE VID VOLTAGE RANGE 0 To 70 IRU3011CW 20-Pin Plastic SOIC WB (W) 1.3V to 3.5V Data Sheet No. PD94143 Figure 1 - Typical application of the IRU3011. VOUT (1.3V - 3.5V) 5V 12V VID0 Power Good Q2 VID1 VID2 VID3 VID4 L1 C5 R1 C3 C6 Q1 R2 R3 C8 R4 C10 C14 C1 C7 C2 R6 C12 R8 C13 C11 R7 R9 R5 C9 D1 C4 L2 HDrv LDrv NC/Gnd SS CS+ Gnd NC/Sen D3 D2D4 D1 D0 IRU3011 VFB V5/Comp CS-V12 NC/ Boot OVP PGdCt/Rt OVP

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2 Rev. 1.608/20/02 IRU3011 www.irf.com ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. ABSOLUTE MAXIMUM RATINGS V5 Supply Voltage .................................................... 7V V12 Supply Voltage .................................................. 20V Storage Temperature Range ...................................... -65°C To 150°C Operating Junction Temperature Range ...................... 0°C To 125°C PACKAGE INFORMATION 20-PIN WIDE BODY PLASTIC SOIC (W) VID Section DAC Output Voltage (Note 1) DAC Output Line Regulation DAC Output Temp Variation VID Input LO VID Input HI VID Input Internal Pull-Up Resistor to V5 Power Good Section Under-Voltage lower trip point Under-Voltage upper trip point UV Hysterises Over-Voltage upper trip point Over-Voltage lower trip point OV Hysteresis Power Good Output LO Power Good Output HI Soft-Start Section Soft-Start Current θJA =858C/W Ct OVP V12 LDrv Gnd NC HDrv CS- PGd NC NC CS+ SS D0 D1 D2 D3 D4 V5 VFB 4 3 2 1 7 6 5 18 19 20 TOP VIEW 11 13 12 14 10 15 9 16 8 17 PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS VOUT Ramping Down VOUT Ramping Up VOUT Ramping Up VOUT Ramping Down RL=3mA RL=5K Pull-Up to 5V CS+=0V, CS-=5V 0.99Vs 2 0.89Vs 0.015Vs 1.09Vs 0.015Vs 4.8 Vs 27 0.90Vs 0.92Vs 0.02Vs 1.10Vs 1.08Vs 0.02Vs 10 1.01Vs 0.1 0.5 0.4 0.91Vs 0.025Vs 1.11Vs 0.025Vs 0.4 V % % V V KΩ V V V V V V V V µA

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IRU3011 3Rev. 1.608/20/02 www.irf.com UVLO Section UVLO Threshold-12V UVLO Hysteresis-12V UVLO Threshold-5V UVLO Hysteresis-5V Error Comparator Section Input Bias Current Input Offset Voltage Delay to Output Current Limit Section CS Threshold Set Current CS Comp Offset Voltage Hiccup Duty Cycle Supply Current Operating Supply Current Output Drivers Section Rise Time Fall Time Dead Band Time Oscillator Section Osc Frequency Osc Valley Osc Peak Over-Voltage Section OVP Drive Current PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Table 1 - Set point voltage vs. VID codes. Note 1: Vs refers to the set point voltage given in Table 1. D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vs 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vs 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 Supply Ramping Up Supply Ramping Up VDIFF=10mV Css=0.1µF CL=3000pF: V5 V12 CL=3000pF CL=3000pF CL=3000pF Ct=150pF 9.2 0.3 4.1 0.2 -2 160 -5 100 190 10 0.4 4.3 0.3 200 20 14 70 70 200 220 V5 10.8 0.5 4.5 0.4 2 +2 100 240 +5 2 100 130 300 250 0.2 V V V V µA mV ns µA mV % mA ns ns ns KHz V V mA

Page 5

4 Rev. 1.608/20/02 IRU3011 www.irf.com PIN DESCRIPTIONS No connection. This pin is connected to the Drain of the power MOSFET of the Core supply and it provides the positive sensing for the internal current sensing circuitry. An external resis- tor programs the CS threshold depending on the RDS of the power MOSFET. An external capacitor is placed in parallel with the programming resistor to provide high frequency noise filtering. This pin provides the soft-start for the switching regulator. An internal current source charges an external capacitor that is connected from this pin to the ground which ramps up the outputs of the switching regulator, preventing the outputs from overshooting as well as limiting the input current. The second function of the Soft-Start cap is to provide long off time for the synchronous MOSFET or the Catch diode (HICCUP) during current limiting. LSB input to the DAC that programs the output voltage. This pin can be pulled up exter- nally by a 10K resistor to either 3.3V or 5V supply. Input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10KΩ resistor to either 3.3V or 5V supply. Input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply. MSB input to the DAC that programs the output voltage. This pin can be pulled-up exter- nally by a 10K resistor to either 3.3V or 5V supply. This pin selects a range of output voltages for the DAC. 5V supply voltage. This pin is connected directly to the output of the Core supply to provide feedback to the Error comparator. No connection. This pin is an open collector output that switches LO when the output of the converter is not within ±10% (typ) of the nominal output voltage. When PGd pin switches LO the saturation voltage is less than 0.4V at 3mA. This pin is connected to the Source of the power MOSFET for the Core supply and it provides the negative sensing for the internal current sensing circuitry. Output driver for the high side power MOSFET. No connection. This pin serves as the ground pin and must be connected directly to the ground plane. A high frequency capacitor (0.1 to 1µF) must be connected from V5 and V12 pins to this pin for noise free operation. Output driver for the synchronous power MOSFET. This pin is connected to the 12 V supply and serves as the power Vcc pin for the output drivers. A high frequency capacitor (0.1 to 1µF) must be connected directly from this pin to ground pin in order to supply the peak current to the power MOSFET during the transitions. Over-voltage comparator output. This pin programs the oscillator frequency in the range of 50KHz to 500KHz with an external capacitor connected from this pin to the ground. PIN# PIN SYMBOL PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC CS+ SS D0 D1 D2 D3 D4 V5 VFB NC PGd CS- HDrv NC Gnd LDrv V12 OVP Ct

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IRU3011 5Rev. 1.608/20/02 www.irf.com BLOCK DIAGRAM Figure 2 - Simplified block diagram of the IRU3011. PWM Control V12 V12 Osc Slope Comp + 5Bit DAC, Ctrl Logic Enable Soft Start & Fault Logic 200uA 0.9Vset 1.1Vset Vset Enable UVLO Vset Enable D4 V5 V12 SS PGd CS- Ct CS+ LDrv HDrv VFB D3 D2 D1 D0 Over Current Enable Gnd 1.18Vset OVP 18 9 4 5 6 7 8 19 16 10 14 17 13 2 20 3 12

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6 Rev. 1.608/20/02 IRU3011 www.irf.com TYPICAL APPLICATION Synchronous Operation (Dual Layout with HIP6004B) Part # R5 R7 R8 R9 C4 C7 C9 C11 C12 C13 D1 HIP6004B O V V V V O O V V V V IRU3011 S O O V O V V O O O O Figure 3 - Typical application of IRU3011 in an on board DC-DC converter providing the Core supply for microprocessor. Table 2 - Components that need to be modified to make the dual layout work for IRU3011and HIP6004B. S - Short O - Open V - See IR or Harris parts list for the value Vcore5V 12V VID0 Power Good Q2 VID1 VID2 VID3 VID4 L1 C 5 R 1 C 3 C 6 Q1 R 2 R 3 C 8 R 4 C10 C14 C 1 C 7 C 2 R 6 C12 R 8 C13 C11 R 7 R 9 R 5 C 9 D 1 C 4 Vcc3 R13 L2 R10 R11 C15 R12 HDrv LDrv NC/Gnd SS CS+ G n d NC/Sen D 3 D 2D 4 D 1 D 0 IRU3011 V FB V5/Comp CS-V12 NC/ B o o t O V P P G dCt/Rt

Page 8

IRU3011 7Rev. 1.608/20/02 www.irf.com Ref Desig Description Qty Part # Manuf Q1 MOSFET 1 IRL3103s, TO-263 package IR Q2 MOSFET 1 IRL3103D1S, TO-263 package IR L1 Inductor 1 L=1µH, 5052 core with 4 turns of Micro Metal 1.0mm wire L2 Inductor 1 L=2.7µH, 5052B core with 7 turns of Micro Metal 1.2mm wire C1 Capacitor, Electrolytic 1 10MV470GX, 470µF, 10V Sanyo C2, 9 Capacitor, Ceramic 2 1µF, 0603 C3 Capacitor, Electrolytic 2 10MV1200GX, 1200µF, 10V Sanyo C5 Capacitor, Ceramic 1 220pF, 0603 C6 Capacitor, Ceramic 1 1µF, 0805 C7 Capacitor, Ceramic 1 150pF, 0603 C8 Capacitor, Ceramic 1 1000pF, 0603 C10 Capacitor, Electrolytic 6 6MV1500GX, 1500µF, 6.3V Sanyo C14 Capacitor, Ceramic 1 0.1µF, 0603 C15 Capacitor, Ceramic 1 4.7µF, 1206 R1 Resistor 1 3.3KΩ, 5%, 0603 R2, 3, 4 Resistor 3 4.7Ω, 5%, 1206 R5 Resistor 1 0Ω, 0603 R6 Resistor 1 10KΩ, 5%, 0603 R9 Resistor 1 100Ω, 1%, 0603 R10 Resistor 1 220Ω, 1%, 0603 R11 Resistor 1 330Ω, 1%, 0603 R12 Resistor 1 22KΩ, 1%, 0603 R13 Resistor 1 10Ω, 5%, 0603 IRU3011 and HIP6004B Dual Layout Parts List Note 1: R10, R11, C15, R9, and R12 set the Vcore 2% higher for level shift to reduce CPU transient voltage.

Page 9

8 Rev. 1.608/20/02 IRU3011 www.irf.com APPLICATION INFORMATION An example of how to calculate the components for the application circuit is given below. Assuming, two sets of output conditions that this regu- lator must meet, the regulator design will be done such that it meets the worst case requirement of each condition. Output Capacitor Selection The first step is to select the output capacitor. This is done primarily by selecting the maximum ESR value that meets the transient voltage budget of the total ∆Vo specification. Assuming that the regulators DC initial accuracy plus the output ripple is 2% of the output volt- age, then the maximum ESR of the output capacitor is calculated as: The Sanyo MVGX series is a good choice to achieve both the price and performance goals. The 6MV1500GX, 1500µF, 6.3V has an ESR of less than 36mΩ typical. Selecting 6 of these capacitors in parallel has an ESR of ≈ 6mΩ which achieves our low ESR goal. Other type of electrolytic capacitors from other manu- facturers to consider are the Panasonic FA series or the Nichicon PL series. Reducing the Output Capacitors Using Voltage Level Shifting Technique The trace resistance or an external resistor from the output of the switching regulator to the Slot 1 can be used to the circuit advantage and possibly reduce the number of output capacitors, by level shifting the DC regulation point when transitioning from light load to full load and vice versa. To accomplish this, the output of the regulator is typically set about half the DC drop that results from light load to full load. For example, if the total resistance from the output capacitors to the Slot 1 and back to the Gnd pin of the device is 5mΩ and if the total ∆I, the change from light load to full load is 14A, then the output voltage measured at the top of the resistor divider which is also connected to the output capacitors in this case, must be set at half of the 70mV or 35mV higher than the DAC voltage setting. This intentional voltage level shifting during the load tran- sient eases the requirement for the output capacitor ESR at the cost of load regulation. One can show that the new ESR requirement eases up by half the total trace resistance. For example, if the ESR requirement of the output capacitors without voltage level shifting must be 7mΩ then after level shifting the new ESR will only need to be 8.5mΩ if the trace resistance is 5mΩ (7 + 5/2=9.5). However, one must be careful that the combined “volt- age level shifting” and the transient response is still within the maximum tolerance of the Intel specification. To in- sure this, the maximum trace resistance must be less than: Where : Rs = Total maximum trace resistance allowed Vspec = Intel total voltage spec Vo = Output voltage ∆Vo = Output ripple voltage ∆I = load current step For example, assuming: Vspec = ±140mV = ±0.1V for 2V output Vo = 2V ∆Vo = assume 10mV = 0.01V ∆I = 14.2A Then the Rs is calculated to be: However, if a resistor of this value is used, the maximum power dissipated in the trace (or if an external resistor is being used) must also be considered. For example if Rs=12.6mΩ, the power dissipated is: This is a lot of power to be dissipated in a system. So, if the Rs=5mΩ, then the power dissipated is about 1W which is much more acceptable. If level shifting is not implemented, then the maximum output capacitor ESR was shown previously to be 7mΩ which translated to ≈ 6 of the 1500µF, 6MV1500GX type Sanyo capacitors. With Rs=5mΩ, the maximum ESR becomes 9.5mΩ which is equivalent to ≈ 4 caps. Another important consideration is that if a trace is being used to implement the resistor, the power dissipated by the trace increases the case temperature of the output capacitors which could seri- ously effect the life time of the output capacitors. ESR ≤ = 7mΩ10014.2 a) Vo=2.8V, Io=14.2A, ∆Vo=185mV, ∆Io=14.2A b) Vo=2V, Io=14.2A, ∆Vo=140mV, ∆Io=14.2A Rs ≤ 2×(Vspec - 0.02×Vo - ∆Vo) / ∆I Rs ≤ 2×(0.140 - 0.02×2 - 0.01) / 14.2 = 12.6mΩ Io2×Rs = 14.22×12.6 = 2.54W

Page 10

IRU3011 9Rev. 1.608/20/02 www.irf.com T ≡ Switching Period D ≡ Duty Cycle Vsw ≡ High-side MOSFET ON Voltage RDS ≡ MOSFET On-Resistance Vsync ≡ Synchronous MOSFET ON Voltage ∆Ir ≡ Inductor Ripple Current ∆Vo ≡ Output Ripple Voltage T = 1/Fsw Vsw = Vsync = Io×RDS D ≈ (Vo + Vsync) / (V IN - Vsw + Vsync) TON = D×T TOFF = T - TON ∆Ir = (Vo + Vsync)×TOFF / L ∆Vo = ∆Ir×ESR L = 0.006×9000×(4.75 - 2.8) / (2×14.2) = 3.7µH L = ESR×C×(VIN(MIN) - Vo(MAX)) / (2×∆I) T = 1 / 200000 = 5µs Vsw = Vsync = 14.2×0.019 = 0.27V D ≅ (2.8 + 0.27) / (5 - 0.27 + 0.27) = 0.61 TON = 0.61×5 = 3.1µs TOFF = 5 - 3.1 = 1.9µs ∆Ir = (2.8 + 0.27)×1.9 / 3 = 1.94A ∆Vo = 1.94×0.006 = 0.011V = 11mV Ts = TJ - PD×(θJC + θcs) Ts = 125 - 3.82×(1.8 + 0.05) = 1188C ∆T = Ts - TA = 118 - 35 = 838C Temperature Rise Above Ambient θSA = ∆T / PD = 83 / 3.82 = 228C/W Output Inductor Selection The output inductance must be selected such that un- der low line and the maximum output voltage condition, the inductor current slope times the output capacitor ESR is ramping up faster than the capacitor voltage is drooping during a load current step. However, if the in- ductor is too small, the output ripple current and ripple voltage become too large. One solution to bring the ripple current down is to increase the switching frequency, however, that will be at the cost of reduced efficiency and higher system cost. The following set of formulas are derived to achieve the optimum performance without many design iterations. The maximum output inductance is calculated using the following equation: Where: VIN(MIN) = Minimum input voltage For Vo=2.8V and ∆I=14.2A Assuming that the programmed switching frequency is set at 200KHz, an inductor is designed using the Micrometals’ powder iron core material. The summary of the design is outlined below: The selected core material is Powder Iron, the selected core is T50-52D from Micro Metal wounded with 8 turns of #16 AWG wire, resulting in 3µH inductance with ≈ 3mΩ of DC resistance. Assuming L=3µH and Fsw=200KHz(switching fre- quency), the inductor ripple current and the output ripple voltage is calculated using the following set of equations: In our example for Vo=2.8V and 14.2A load, assuming IRL3103 MOSFET for both switches with maximum on resistance 0f 19mΩ, we have: Power Component Selection Assuming IRL3103 MOSFETs as power components, we will calculate the maximum power dissipation as fol- lows: For high-side switch the maximum power dissipation happens at maximum Vo and maximum duty cycle. RDS(MAX) = Maximum RDS(ON) of the MOSFET at 1258C For synch MOSFET, maximum power dissipation hap- pens at minimum Vo and minimum duty cycle. Heat Sink Selection Selection of the heat sink is based on the maximum allowable junction temperature of the MOSFETS. Since we previously selected the maximum RDS(ON) at 1258C, then we must keep the junction below this temperature. Selecting TO-220 package gives θJC=1.88C/W (From the venders’ data sheet) and assuming that the selected heat sink is black anodized, the heat-sink-to-case ther- mal resistance is θcs=0.058C/W, the maximum heat sink temperature is then calculated as: With the maximum heat sink temperature calculated in the previous step, the heat-sink-to-air thermal resistance (θSA) is calculated as follows: Assuming TA = 358C: DMIN ≅ (2 + 0.27) / (5.25 - 0.27 + 0.27) = 0.43 PDS = (1 - DMIN)×Io2×RDS(MAX) PDS = (1 - 0.43)×14.22×0.029 = 3.33W DMAX ≅ (2.8 + 0.27) / (4.75 - 0.27 + 0.27) = 0.65 PDH = DMAX×Io2×RDS(MAX) PDH = 0.65×14.22×0.029 = 3.8W

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