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IS43DR16640B-25DBL

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IS43DR16640B-25DBL

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Part Number IS43DR16640B-25DBL
Manufacturer ISSI, Integrated Silicon Solution Inc
Description IC SDRAM 1GBIT 400MHZ 84BGA
Datasheet IS43DR16640B-25DBL Datasheet
Package 84-TFBGA
In Stock 4,200 piece(s)
Unit Price $ 5.0800 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # IS43DR16640B-25DBL (Memory) is manufactured by ISSI, Integrated Silicon Solution Inc and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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IS43DR16640B-25DBL Specifications

ManufacturerISSI, Integrated Silicon Solution Inc
CategoryIntegrated Circuits (ICs) - Memory
Datasheet IS43DR16640B-25DBLDatasheet
Package84-TFBGA
Series-
Memory TypeVolatile
Memory FormatDRAM
TechnologySDRAM - DDR2
Memory Size1Gb (64M x 16)
Memory InterfaceParallel
Clock Frequency400MHz
Write Cycle Time - Word, Page15ns
Access Time400ps
Voltage - Supply1.7 V ~ 1.9 V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case84-TFBGA
Supplier Device Package84-WBGA (8x12.5)

IS43DR16640B-25DBL Datasheet

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IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 1 3/25/2015 1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential or Interleave  Programmable Burst Length: 4 and 8  Automatic and Controlled Precharge Command  Power Down Mode  Auto Refresh and Self Refresh  Refresh Interval: 7.8 s (8192 cycles/64 ms)  ODT (On-Die Termination)  Weak Strength Data-Output Driver Option  Bidirectional differential Data Strobe (Single- ended data-strobe is an optional feature)  On-Chip DLL aligns DQ and DQs transitions with CK transitions  DQS# can be disabled for single-ended data strobe  Read Data Strobe supported (x8 only)  Differential clock inputs CK and CK#  VDD and VDDQ = 1.8V ± 0.1V  PASR (Partial Array Self Refresh)  SSTL_18 interface  tRAS lockout supported  Operating temperature: Commercial (TA = 0°C to 70°C ; TC = 0°C to 85°C) Industrial (TA = -40°C to 85°C; TC = -40°C to 95°C) Automotive, A1 (TA = -40°C to 85°C; TC = -40°C to 95°C) Automotive, A2 (TA = -40°C to 105°C; TC = -40°C to 105°C) OPTIONS  Configuration:  128Mx8 (16M x 8 x 8 banks)  64Mx16 (8M x 16 x 8 banks)  Package:  60-ball TW-BGA for x8  84-ball TW-BGA for x16  Self-Refresh:  Standard  Low Power (L) ADDRESS TABLE Parameter 128Mx8 64Mx16 Row Addressing A0-A13 A0-A12 Column Addressing A0-A9 A0-A9 Bank Addressing BA0-BA2 BA0-BA2 Precharge Addressing A10 A10 Clock Cycle Timing -3D -25E -25D Units Speed Grade DDR2-667D DDR2-800E DDR2-800D CL-tRCD-tRP 5-5-5 6-6-6 5-5-5 tCK tCK (CL=3) 5 5 5 ns tCK (CL=4) 3.75 3.75 3.75 ns tCK (CL=5) 3 3 2.5 ns tCK (CL=6) 3 2.5 2.5 ns tCK (CL=7) 3 2.5 2.5 ns Frequency (max) 333 400 400 MHz MARCH 2015 Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Page 3

IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 2 3/25/2015 Package Ball-out and Description DDR2 SDRAM (128Mx8) TW-BGA Ball-out (Top-View) (8.00mm x 10.50mm) Description Input clocks Clock enable Chip Select Command control pins Address Bank Address I/O Data Strobe Redundant Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect VDDL VSSDL NC VSS VDDQ VSSQ VREF ODT BA[2:0] DQ[7:0] DQS, DQS# RDQS, RDQS# DM VDD Symbol CK, CK# CKE CS# RAS#,CAS#,WE# A[13:0] Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS# are identical in function and timing to strobe pair DQS & DQS# and input masking function is disabled. 3. The function of DM or RDQS/RDQS# are enabled by EMRS command. 4. VDDL and VSSDL are power and ground for the DLL.

Page 4

IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 3 3/25/2015 DDR2 SDRAM (64Mx16) TW-BGA Ball-out (Top-View) (8.00mm x 12.50mm Body, 0.8mm pitch) Description Input clocks Clock enable Chip Select Command control inputs Address Bank Address I/O Upper Byte Data Strobe Lower Byte Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect VDDL VSSDL NC ODT VDD VSS VDDQ VSSQ LDQS, LDQS# UDM, LDM RAS#,CAS#,WE# A[12:0] BA[2:0] VREF Symbol CK, CK# CKE CS# DQ[15:0] UDQS, UDQS# Note: VDDL and VSSDL are power and ground for the DLL. 1 2 3 4 5 6 7 8 9 A B C D E F G H J K L M N P R

Page 5

IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 4 3/25/2015 Functional Description Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for Power-up and Initialization. 1. Either one of the following sequence is required for Power-up: A. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT 1 at a LOW state (all other inputs may be undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD(Min); and during the VDD voltage ramp, |VDD-VDDQ| ≥ 0.3 V. Once the ramping of the supply voltages is complete (when VDDQ crosses VDDQ(Min)), the supply voltage specifications provided in the table Recommended DC Operating Conditions (SSTL_1.8), prevail.  VDD, VDDL and VDDQ are driven from a single power converter output, AND  VTT is limited to 0.95V max, AND  VREF tracks VDDQ/2, VREF must be within ± 300mV with respect to VDDQ/2 during supply ramp time.  VDDQ ≥ VREF must be met at all times B. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT 1 at a LOW state (all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch- up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications provided in the table Recommended DC Operating Conditions (SSTL-1.8), prevail.  Apply VDD/VDDL before or at the same time as VDDQ.  VDD/VDDL voltage ramp time must be no greater 200 ms from when VDD ramps from 300 mV to VDD(Min) .  Apply VDDQ before or at the same time as VTT.  The VDDQ voltage ramp time from when VDD(Min) is achieved on VDD to the VDDQ(Min) is achieved on VDDQ must be no greater than 500 ms. 2. Start clock and maintain stable condition. 3. For the minimum of 200 µs after stable power (VDD, VDDL, VDDQ, VREF, and VTT values are in the range of the minimum and maximum values specified in the table Recommended DC Operating Conditions (SSTL-1.8)) and stable clock (CK, CK#), then apply NOP or Deselect and assert a logic HIGH to CKE. 4. Wait minimum of 400 ns then issue a precharge all command. During the 400 ns period, a NOP or Deselect command must be issued to the DRAM. 5. Issue an EMRS command to EMR(2). 6. Issue an EMRS command to EMR(3). 7. Issue EMRS to enable DLL. 8. Issue a Mode Register Set command for DLL reset. 9. Issue a precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL.) 12. Wait at least 200 clock cycles after step 8 and then execute OCD Calibration. EMRS Default command (A9=A8=A7=HIGH) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1). 13. The DDR2 SDRAM is now ready for normal operation. Note: 1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.

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IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 5 3/25/2015 Initialization Sequence after Power-Up Diagram tCH tCL tIS CK CK# ODT ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~Command NOP PRE ALL EMRS MRS REF Any Com PRE ALL REF MRS EMRS EMRS 400ns tRP tMRD DLL Enable DLL Reset Minimum 200 Cycles OCD Default OCD Cal. Mode Exit ~ ~ ~ ~ tIS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ tMRD tRP tRFC tRFC Follow OCD Flowchart tMRD tOIT Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, CAS# latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) or Extended Mode Registers EMR[1] and EMR[2] can be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR, EMR[1], or EMR[2] variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued. The x16 option does not have A13, so all references to this address can be ignored for this option. MRS, EMRS and Reset DLL do not affect memory array contents, which mean re-initialization including those can be executed at any time after power-up without affecting memory array contents. DDR2 Mode Register (MR) Setting The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS# latency, burst length, burst sequence, DLL reset, tWR and active power down exit time to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2 while controlling the state of address pins A0 - A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 - A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3; CAS latency is defined by A4 - A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time tWR is defined by A9 - A11. Refer to the table for specific codes.

Page 7

IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 6 3/25/2015 Mode Register (MR) Diagram A12 0 BA2 0 1 BA1 0 BA0 0 A11 A10 A9 A13(1) 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A8 0 A7 1 0 1 A6 A5 A4 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A3 0 1 A2 A1 A0 BL 0 1 0 4 0 1 1 8 Address Field Mode Register A2 Burst Length A6 CAS Latency A7 TM A11 WR Interleave A3 BT 5 6 7 A1 Burst Type Sequential A0 CAS Latency Reserved A5 Reserved Reserved A4 3 4 A10 6 Yes Reserved A8 DLL DLL Reset ModeNo Normal 7 A9 8 Reserved A12 PD1 2 3 4 5 WR(cycles)(2) Slow exit(use tXARDS) Active power down exit time Fast exit (use tXARD) Notes: 1. A13 is reserved for future use and must be set to 0 when programming the MR. 2. WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL. DDR2 Extended Mode Register 1 (EMR[1]) Setting The extended mode register 1 stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. Extended mode register 1 is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1, and BA2, and HIGH on BA0, and controlling pins A0 – A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling reduced strength data-output driver. A3 - A5 determines the additive latency, A2 and A6 are used for ODT value selection, A7 - A9 are used for OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.

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IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 7 3/25/2015 DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Extended Mode Register 1(EMR[1]) Diagram A12 0 BA2 0 1 BA1 0 BA0 1 A11(2) A13(1) 0 0 RDQS/DM RDQS# DQS DQS# 1 0 0 DM Hi-Z DQS DQS# A10 0 1 DM Hi-Z DQS Hi-Z 0 1 0 RDQS RDQS# DQS DQS# 1 1 1 RDQS Hi-Z DQS Hi-Z A9 A8 A7 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 A5 A4 A3 0 0 0 A6 A2 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 A1 A0 0 0 1 1 RDQS Enable A11 (RDQS) A10 (DQS#) Qoff Output buffer enabled Ouput buffer disabled Strobe Function Matrix Disable A11 RDQS Enable Disable A12 Qoff Enable DQS# A10 DQS# OCD Calibration Program A9 OCD Calibration mode exit; maintain setting Reserved A8 Reserved Reserved 75 ohms A7 OCD Calibration default (3) A6 Rtt Additive Latency 0 Rtt(NOMINAL) A5 Additive Latency 1 ODT Disabled 2 A4 Rtt Reserved A1 D.I.C Output Drive Impedance Control 4 A3 Normal Strength (100%) Enable Reduced strength (60%) 3 150 ohms 50 ohms Disable A2 OCD Program 5 6 Address Field Mode Register DLL enable A0 DLL Notes: 1. A13 is reserved for future use and must be set to 0 when programming the EMR[1]. 2. If RDQS is enabled, the DM function is disabled. RDQS is active for reads and don’t care for writes. The x16 option does not support RDQS. This must be set to 0 when programming the EMR[1] for the x16 option. 3. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. DDR2 Extended Mode Register 2 (EMR[2]) Setting The extended mode register 2 controls refresh related features. The default value of the extended mode register 2 is not defined. Therefore, the extended mode register must be programmed during initialization for proper operation. The extended mode register 2 is written by asserting LOW on CS, RAS, CAS, WE, BA0, BA2, and HIGH on BA1, while controlling pins A0-A13. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into extended mode register 2. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register 2. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state.

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IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 8 3/25/2015 Extended Mode Register 2 (EMR[2]) Diagram Address Field Mode Register BA2 0 BA1 1 BA0 0 A13 (1) 0 A7 0 1 A2 A1 A0 BA[2:0] 0 0 0 All combinations 0 0 1 000, 001, 010, 011 0 1 0 000, 001 0 1 1 000 1 0 0 010, 011, 100, 101, 110, 111 1 0 1 100, 101, 110, 111 1 1 0 110, 111 1 1 1 111 A2 PASR (3) Quarter Array 1/8 array A1 3/4 array Half array A0 Quarter array 1/8 array A4 (1) 0 Partial Array Self Refresh for 8 Banks A3 (1) 0 Full Array Half Array A6 (1) 0 A5 (1) 0 A8 (1) 0 High Temperature Self-Refresh Rate Enable A7 SRFt Disable Enable (2) A10 (1) 0 A9 (1) 0 A12 (1) 0 A11 (1) 0 Notes: 1. A3-A6, and A8-A13 are reserved for future use and must be set to 0 when programming the EMR[2]. 2. Only Industrial and Automotive grade devices support the high temperature Self-Refresh Mode. The controller can set the EMR (2) [A7] bit to enable this self- refresh rate if Tc > 85°C while in self-refresh operation. TOPER may not be violated. 3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. DDR2 Extended Mode Register 3 (EMR[3]) Setting No function is defined in extended mode register 3. The default value of the extended mode register 3 is not defined. Therefore, the extended mode register 3 must be programmed during initialization for proper operation. DDR2 Extended Mode Register 3 (EMR[3]) Diagram BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0* 1 1 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Address Field Mode Register Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3].

Page 10

IS43/46DR81280B(L), IS43/46DR16640B(L) Rev. G 9 3/25/2015 Truth Tables Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. Command Truth Table Previous Cycle Current Cycle (Extended) Mode Register H H L L L L BA 1, 2 Refresh (REF) H H L L L H X X X X 1 Self Refresh Entry H L L L L H X X X X 1, 8 H X X X L H H H Single Bank Precharge H H L L H L BA X L X 1, 2 Precharge All Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA 1, 2 Write H H L H L L BA X L Column 1, 2, 3, 10 Write with Auto Precharge H H L H L L BA X H Column 1, 2, 3, 10 Read H H L H L H BA X L Column 1, 2, 3, 10 Read with Auto Precharge H H L H L H BA X H Column 1, 2, 3, 10 No Operation (NOP) H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 H X X X L H H H H X X X L H H H Function CKE CS# RAS# CAS# WE# BA2-BA0 An(9)-A11 A10 A9-A0 Notes Opcode Sel Refresh Exit L H X X X X 1, 7, 8 Row Address Power Down Entry H L X X X X 1,4 Power Down Exit L H X X X X 1, 4 Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. 2. Bank addresses BA0, BA1, and BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 6. “X” means “H or L (but a defined logic level)” 7. Self refresh exit is asynchronous. 8. VREF must be maintained during Self Refresh operation. 9. An refers to the MSBs of addresseses. An=A13 for x8, and An=A12 for x16.

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