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ISL54405IVZ-T

hot ISL54405IVZ-T

ISL54405IVZ-T

For Reference Only

Part Number ISL54405IVZ-T
Manufacturer Intersil
Description IC MUX STEREO 2:1 CD/MP3 16TSSOP
Datasheet ISL54405IVZ-T Datasheet
Package 16-TSSOP (0.173", 4.40mm Width)
In Stock 5170 piece(s)
Unit Price $ 1.188 *
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ISL54405IVZ-T Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - Interface - Analog Switches - Special Purpose
Datasheet ISL54405IVZ-T Datasheet
Package16-TSSOP (0.173", 4.40mm Width)
Series-
ApplicationsAudio
Multiplexer/Demultiplexer Circuit2:1
Switch CircuitSPDT
Number of Channels2
On-State Resistance (Max)1.9 Ohm
Voltage - Supply, Single (V+)3.3V, 5V
-3db Bandwidth230MHz
FeaturesBreak-Before-Make, Depop
Operating Temperature-40°C ~ 85°C (TA)
Package / Case16-TSSOP (0.173", 4.40mm Width)
Supplier Device Package16-TSSOP

ISL54405IVZ-T Datasheet

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FN6699 Rev 2.00 May 6, 2014 ISL54405 CD/MP3 Quality Stereo 2:1 Multiplexer with Click and Pop Elimination DATASHEETThe Intersil ISL54405 is a single supply, bidirectional, dual single-pole/double-throw (SPDT) ultra low distortion, high OFF-Isolation analog switch that can pass analog signals that are positive and negative with respect to ground. It is primarily targeted at consumer and professional audio switching applications such as computer sound cards and home theater products. The inputs can accommodate ground referenced signals up to 2VRMS while operating from a single 3.3V or 5V DC supply. The digital logic inputs are 1.8V logic-compatible when using a single 3.3V or 5V supply. It can be used in both AC or DC coupled ground referenced applications. The ISL54405 features a soft-switch feature and click/pop circuitry at each signal pin that eliminates clicks and pops associated with power-up/down conditions of the preceding amplifier outputs. With -106dB THD+N performance with a 2VRMS signal into 20k load, superior signal muting, high PSRR and very flat frequency response, the ISL54405 meets the exacting requirements of consumer and professional audio engineers. The ISL54405 is available in 16 Ld TSSOP, 16 Ld 3mmx3mm TQFN, and 16 Ld 2.6mmx1.8mm µTQFN packages. It’s specified for operation over the -40°C to +85°C temperature range. Related Literature • TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • AN557 “Recommended Test Procedures for Analog Switches” Features • Clickless audio switching • 2 switches • Switch type SPDT or 2 to 1 MUX • 2VRMS signal switching from 3.3V or 5V supply • -106dB THD+N into 20k load at 2VRMS • -108dB THD+N into 32 load at 3.9mW • Signal to noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >124dBV • ±0.01dB insertion loss at 1kHz, 20k load • ±0.007dB gain variation 20Hz to 20kHz • 125dB signal muting into 20k load • 90dB PSRR 20Hz to 20kHz • Single supply operation . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V or 5V • Available in 16 Ld TSSOP, 16 Ld TQFN, and 16 Ld µTQFN • Pb-Free (RoHS compliant) Applications • Computer sound cards • Home theater audio products • SACD/DVD audio • DVD player audio output switching • Headsets for MP3/cellphone switching • Hi-Fi audio switching application FIGURE 1. ISL54405 BLOCK DIAGRAM LOGIC ISL54405 SEL MUTE L R L1 L2 R1 R2 CAP_SS VDD5V_Supply For 5V operation connect the 5V_Supply pin to 5V and float the VDD pin. For 3.3V operation connect the VDD pin to 3.3V and float GND AC/DC the 5V_Supply pin. DIR_SEL CONTROL AND CLICK/POP FN6699 Rev 2.00 Page 1 of 20 May 6, 2014

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ISL54405Pin Configurations (Note 1) ISL54405 (16 LD µTQFN) TOP VIEW ISL54405 (16 LD TQFN) TOP VIEW ISL54405 (16 LD TSSOP) TOP VIEW NOTE: 1. See Figure 1 on page 1. 1 3 4 15 MUTE L R SEL A C /D C 5V _S u p p ly V D D C A P _ S S 16 14 13 2 12 10 9 11 65 7 8 L1 L2 R1 R2 G N D D IR _S E L G N D G N D 1 3 4 15 MUTE L R SEL A C /D C 5 V _ S u p p ly V D D C A P _ S S 16 14 13 2 12 10 9 11 65 7 8 L1 L2 R1 R2 G N D D IR _S E L G N D G N D 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 5V_Supply AC/DC MUTE L R SEL DIR_SEL GND VDD L1 L2 R1 R2 GND GND CAP_SSFN6699 Rev 2.00 Page 2 of 20 May 6, 2014

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ISL54405 Truth Table INPUTS OUTPUTS AC/DC DIR MUTE SEL L1, R1 L2, R2 COM (L, R) C/P SHUNTS L1, R1 C/P SHUNTS L2, R2 C/P SHUNTS 0 X 0 0 ON OFF OFF OFF OFF 0 X 0 1 OFF ON OFF OFF OFF 0 X 1 X OFF OFF OFF OFF OFF 1 0 0 0 ON OFF OFF OFF ON 1 0 0 1 OFF ON OFF ON OFF 1 0 1 X OFF OFF OFF ON ON 1 1 0 0 ON OFF OFF OFF OFF 1 1 0 1 OFF ON OFF OFF OFF 1 1 1 X OFF OFF ON OFF OFF NOTE: MUTE, AC/DC, DIR: Logic “0” 0.5V, Logic “1” 1.4V or float with a 3.3V supply or 5V supply. SEL: Logic “0” 0.5V, Logic “1” 1.4V with a 3.3V supply or 5V supply. X = Don’t Care Pin Descriptions PIN # TSSOP PIN # µTQFN, TQFN PIN NAME DESCRIPTION 16 14 VDD System power supply pin (+3V to +3.6V) (float pin for 5V applications) 1 15 5V_Supply 5V supply pin (+4.5V to +5.5V) (float pin for 3.3V applications) 7, 9, 10 5, 7, 8 GND Ground connection 15 13 CAP_SS Soft-start capacitor pin 3 1 MUTE Signal mute control pin 6 4 SEL Input select control pin 2 16 AC/DC AC/DC select control pin 8 6 DIR_SEL Direction select control pin 5 3 R Analog switch common pin 4 2 L Analog switch common pin 11, 13 9, 11 R2, L2 Analog switch normally open pin 12, 14 10, 12 R1, L1 Analog switch normally closed pin Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL54405IVZ (Notes 3, 4) 54405 IVZ -40 to +85 16 Ld TSSOP M16.173 ISL54405IRTZ (Notes 3, 4) 05TZ -40 to +85 16 Ld 3x3 TQFN L16.3x3A ISL54405IRUZ-T (Notes 2, 5) GAD -40 to+ 85 16 Ld µTQFN L16.2.6x1.8A NOTES: 2. Please refer to TB347 for details on reel specifications. 3. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.FN6699 Rev 2.00 Page 3 of 20 May 6, 2014

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ISL54405Absolute Maximum Ratings Thermal Information VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V 5V_Supply to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Input Voltages SEL, MUTE, AC/DC, DIR_SEL (Note 6) . . . . . . . . . . -0.3 to ((VDD) + 0.3V) L1, L2, R1, R2 (Note 6) . . . . . . . . . . . . . . . . . . . . . . -3.1 to ((VDD) + 0.3V) Output Voltages R, L (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3.1 to ((VDD) + 0.3V) Continuous Current L1, L2, R1, R2 or L, R . . . . . . . . . . . . . . . . . . ±300mA Peak Current L1, L2, R1, R2 or L, R (Pulsed 1ms, 10% Duty Cycle, Max). . . . . . . . . . . . . . . . . . . . . . ±500mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 16 Ld TSSOP Package (Note 7) . . . . . . . . . 110 41 16 Ld TQFN Package (Notes 8, 9) . . . . . . . 75 11 16 Ld µTQFN Package (Note 8) . . . . . . . . . 93 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Signals on L1, L2, R1 R2, MUTE, SEL, AC/DC, DIR_SEL, R, and L exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 9. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications 3.3V Supply: VDD = +3.0V to +3.6V, GND = 0V, VDIR_SEL = VAC/DC = GND, V5V_SUPPLY = Float, VSIGNAL = 2VRMS, RLOAD = 20kΩ , f = 1kHz, VSELH = VMUTEH = 1.4V, VSELL = VMUTEL = 0.5V, CAP_SS = 0.1µF, (Note 10), Unless otherwise specified. PARAMETER TEST CONDITIONS SUPPLY (V) TEMP (°C) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG 3.3, 5 Full - 2 - VRMS ON-Resistance, rON VDD = 3.3V, IR or IL = 80mA, VLx or VRx = -2.828V to +2.828V (See Figure 5) 3.3 25 - 1.9 -  Full - 2.6 -  rON Matching Between Channels, rON VDD = 3.3V, IR or IL = 80mA, VLx or VRx = Voltage at max rON over -2.828V to +2.828V (Note 15) 3.3 25 - 0.023 -  Full - 0.045 -  rON Flatness, rFLAT(ON) VDD = 3.3V, IR or IL = 80mA, VLx or VRx = -2.828V, 0V, +2.828V (Note 13) 3.3 25 - 0.003 0.01  Full - 0.009 -  L, R, Lx, Rx Pull-down Resistance VDD = 3.6V, VLx or VRx = -2.83V, 2.83V, VL or VR = -2.83V, 2.83V, VAC/DC = 0V, VMUTE = 3.6V, measure current, calculate resistance. 3.6 25 225 300 375 k Full - 345 - k DYNAMIC CHARACTERISTICS THD+N VSIGNAL = 2VRMS, f = 1kHz, A-weighted filter, RLOAD = 20k 3.3, 5 25 - -106 - dB VSIGNAL = 1.9VRMS, f = 1kHz, A-weighted filter, RLOAD = 20k 25 - -113 - dB VSIGNAL = 1.8VRMS, f = 1kHz, A-weighted filter, RLOAD = 20k 25 - -116 - dB VSIGNAL = 0.707VRMS, f = 1kHz, A-weighted filter, RLOAD = 32 25 - -100 - dB SNR f = 20Hz to 20kHz, A-weighted filter, inputs grounded, RLOAD = 20k or 32 3.3, 5 25 - >124 - dBV Insertion Loss, GON f = 1kHz, RLOAD = 20k 3.3 25 - ±0.01 - dBFN6699 Rev 2.00 Page 4 of 20 May 6, 2014

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ISL54405Gain vs Frequency, Gf f = 20Hz to 20kHz, RLOAD = 20k, reference to GON at 1kHz 3.3 25 - ±0.007 - dB Stereo Channel Imbalance L1 and R1, L2 and R2 f = 20Hz to 20kHz, RLOAD = 20k 3.3 25 - ±0.003 - dB OFF-Isolation (Muting) f = 20Hz to 22kHz, L = R = 2VRMS, RLOAD = 20k, MUTE = AC/DC = 3.3V, DIR_SEL = GND, SEL = “X” 3.3, 5 25 - 120 - dB f = 20Hz to 22kHz, L1, R1, L2, R2 = 2VRMS, RLOAD = 20kMUTE = AC/DC = DIR_SEL = 3.3V, SEL = “X” 25 - 120 - dB f = 20Hz to 22kHz, VL or VR = 0.7VRMS, RLOAD = 32 25 - 125 - dB Crosstalk (Channel-to- Channel) RL = 20k, f = 20Hz to 20kHz, VSIGNAL = 2VRMS, signal source impedance = 20, Note 16 3.3 25 - 120 - dB RL = 32, f = 20Hz to 20kHz, VSIGNAL = 0.7VRMS, signal source impedance = 20, Note 16 25 - 120 - dB PSRR f = 1kHz, VSIGNAL= 100mVRMS, inputs grounded 3.3, 5 25 - 110 - dB f = 20kHz, VSIGNAL= 100mVRMS, inputs grounded 25 - 90 - dB Bandwidth, -3dB RLOAD = 50 3.3 25 - 230 - MHz ON to Mute Time, TTRANS-OM CAP_SS = 0.1µF 3.3 25 - 50 - ns Mute to ON Time, TTRANS-MO CAP_SS = 0.1µF (Selectable via soft-start capacitor value) 3.3 25 - 58 - ms Turn-ON Time, tON VDD = 3.3V, VLx or VRx = 1.5V, VMUTE = 0V, RL = 20k (See Figure 2) 3.3 25 - 45 - µs Turn-OFF Time, tOFF VDD = 3.3V, VLx or VRx = 1.5V, VMUTE = 0V, RL = 20k (See Figure 2) 3.3 25 - 50 - ns Break-Before-Make Time Delay, tD VDD = 3.6V, VLx or VRx = 1.5V, VMUTE = 0V, RL = 20k (See Figure 3) 3.6 25 - 45 - µs OFF-Isolation RL = 50, f = 1MHz, VL or VR = 1VRMS (See Figure 4) 3.3 25 - 100 - dB Crosstalk (Channel-to- Channel) RL = 50, f = 1MHz, VL or VR = 1VRMS (See Figure 6) 3.3 25 - 70 - dB Lx, Rx OFF Capacitance, COFF f = 1MHz, VLx or VRx = VL or VR = 0V (See Figure 7) 3.3 25 - 10 - pF L, R ON Capacitance, CCOM(ON) f = 1MHz, VLx or VRx = VCOM = 0V (See Figure 7) 3.3 25 - 27 - pF POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD 5V_Supply = Float 3.3 Full 3 - 3.6 V Power Supply Range, 5V_Supply VDD = Float 5 Full 4.5 - 5.5 V Positive Supply Current, I+ VDD = +3.6V, VMUTE = 0V, VSEL = 0V or VDD 3.6 25 - 54 65 µA Full - 59 - µA VDD = +3.6V, VMUTE = VDD, VSEL = 0V or VDD 3.6 25 - 14 18 µA 3.6 Full - 15 - µA VDD = +3.6V, VMUTE = 0V, VSEL = 1.8V 3.6 25 - 55 65 µA 3.6 Full - 58 - µA DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VSELL, VMUTEL 3.3, 5 Full - - 0.5 V Electrical Specifications 3.3V Supply: VDD = +3.0V to +3.6V, GND = 0V, VDIR_SEL = VAC/DC = GND, V5V_SUPPLY = Float, VSIGNAL = 2VRMS, RLOAD = 20kΩ , f = 1kHz, VSELH = VMUTEH = 1.4V, VSELL = VMUTEL = 0.5V, CAP_SS = 0.1µF, (Note 10), Unless otherwise specified. PARAMETER TEST CONDITIONS SUPPLY (V) TEMP (°C) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITSFN6699 Rev 2.00 Page 5 of 20 May 6, 2014

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ISL54405Input Voltage High, VSELH, VMUTEH 3.3, 5 Full 1.4 - - V Input Current, ISELH, ISELL VDD = 3.6V, VMUTE = 0V, VSEL = 0V or VDD 3.6 Full -0.5 0.01 0.5 µA Input Current, IAC/DCL, IDIR_SELL VDD = 3.6V, VAC/DC, VDIR_SEL = 0V, VMUTE = Float, VSEL = VDD 3.6 Full -1.3 -0.7 0.3 µA Input Current, IAC/DCH, IDIR_SELH VDD = 3.6V, VAC/DC, VDIR_SEL = VDD, VMUTE = 0V, VSEL = 0V 3.6 Full -0.5 0.01 0.5 µA Input Current, IMUTEL VDD = 3.6V, VSEL = VDD, VMUTE = 0V 3.6 Full -1.3 -0.7 0.3 µA Input Current, IMUTEH VDD = 3.6V, VSEL = 0V, VMUTE = VDD 3.6 Full -0.5 0.01 0.5 µA NOTES: 10. VIN = input voltage to perform proper function. 11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Flatness is defined as the difference between maximum and minimum value of ON-resistance at the specified analog signal voltage points. 14. Limits established by characterization and are not production tested. 15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value. 16. Crosstalk is inversely proportional to source impedance. Test Circuits and Waveforms Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 2A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT FIGURE 2. SWITCHING TIMES Electrical Specifications 3.3V Supply: VDD = +3.0V to +3.6V, GND = 0V, VDIR_SEL = VAC/DC = GND, V5V_SUPPLY = Float, VSIGNAL = 2VRMS, RLOAD = 20kΩ , f = 1kHz, VSELH = VMUTEH = 1.4V, VSELL = VMUTEL = 0.5V, CAP_SS = 0.1µF, (Note 10), Unless otherwise specified. PARAMETER TEST CONDITIONS SUPPLY (V) TEMP (°C) MIN (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS 50% tr < 20ns tf < 20ns tOFF 90% VDD 0V VLx OR VRx 0V tON LOGIC INPUT SWITCH INPUT SWITCH OUTPUT 90% VOUT VOUT V(Lx or Rx) RL RL rON+ -----------------------= SWITCH INPUT LOGIC INPUT VOUT RL CL L or R Lx OR Rx SEL GND VDD C MUTEFN6699 Rev 2.00 Page 6 of 20 May 6, 2014

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ISL54405FIGURE 3A. MEASUREMENT POINTS Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 4. OFF-ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT Test Circuits and Waveforms (Continued) 90% VDD 0V tD LOGIC INPUT SWITCH OUTPUT 0VVOUT LOGIC INPUT SEL R OR L RL CL VOUT Lx Rx VDD GND VNX C MUTE ANALYZER RL SIGNAL GENERATOR VDD C 0V OR VDD Lx or Rx L, R SEL GND Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. MUTE VDD C 0V OR VDD Lx or Rx L, R SEL GND VNX V1 rON = V1/80mA 80mA Repeat test for all switches. MUTE 0V OR VDD ANALYZER VDD C Lx OR Rx SIGNAL GENERATOR RL GND SEL L, R NC L, R Lx or Rx Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. MUTE VDD C GND Lx or Rx L, R SEL IMPEDANCE ANALYZER 0V OR VDD Repeat test for all switches. MUTEFN6699 Rev 2.00 Page 7 of 20 May 6, 2014

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ISL54405Sound Card AC Coupled Application Block Diagrams Detailed Description The ISL54405 is a single supply, bidirectional, dual single pole/double throw (SPDT) ultra low distortion, high OFF-Isolation analog switch. It was designed to operate from either a 3.3V or 5V single supply. When operated with a 3.3V or 5V single supply, the switches can accommodate ±2.83VPEAK (2VRMS) ground reference analog signals. The switch rON flatness across this range is extremely small resulting in excellent THD+N performance (0.0006% with 20k load and 0.0014% with 32 load at 707mVRMS). The T-Type configuration of the switch cells prevents signals from getting through to the output when a switch is in the OFF-state providing for superior mute performance (>120dB) in audio applications. The ISL54405 has special circuitry to eliminate click and pops in the speakers during power-up and power-down of the audio CODEC drivers, during removal and insertion of headphones, and while switching between sources and loads. The ISL54405 was designed primarily for consumer and professional audio switching applications such as computer sound cards and home theater products. The “Sound Card AC Coupled Application Block Diagrams” show two typical sound card applications. In the upper block diagram the ISL54405 is being used to route a single stereo source to either the front or back panel line outs of the computer sound card. In the lower block diagram the ISL54405 is being used to multiplex two stereo sources to a single line out of the computer sound card. CODEC µ-CONTROLLER 0.1µF SOFT-START L R L1 LINE OUT OR HEADPHONE JACK FRONT PANEL LINE OUT OR HEADPHONE JACK BACK PANELL2 R1 R2 3.3VFLOAT CAPACITOR LOGIC AUDIO LOGIC ISL54405 SEL MUTE L R L1 L2 R1 R2 CAP_SS VDD5V_Supply GND AC/DC DIR_SEL CONTROL CODEC µ-CONTROLLER 0.1µF SOFT-START L R L1 LINE OUT OR HEADPHONE JACK FRONT PANEL L2 R1 R2 3.3VFLOAT CAPACITOR LOGIC AUDIO ISL54405 SEL MUTE L R L1 L2 R1 R2 CAP_SS VDD5V_Supply GND AC/DC DIR_SEL CODEC AUDIO AND CLICK/POP LOGIC CONTROL AND CLICK/POPFN6699 Rev 2.00 Page 8 of 20 May 6, 2014

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ISL54405SPDT Switch Cell Architecture and Performance Characteristics The normally open (L2, R2) and normally closed (L1, R1) of the SPDT switches are T-Type switches that have a typical rON of 1.9and an off-isolation of >120dB. The low on-resistance (1.9and rON flatness (0.003) provide very low insertion loss and minimal distortion to applications that require hi-fidelity signal reproduction. The SPDT switch cells have internal charge pumps that allow for signals to swing below ground. They were specifically designed to pass audio signals that are ground referenced and have a swing of ± 2.828VPEAK while driving either 10k/20k (receiver) or 32 (headphone) loads. Each switch cell incorporates special circuitry to gradually decrease the switch resistance when transitioning from the OFF-state (high impedance) to the ON-state (1.9). The gradual decrease in the switch resistance provides for a slow ramp of the voltage at the load side of the switch which helps to eliminate clicks and pops in the speaker by suppressing the transient during switching events. The output voltage ramp time is determined by the capacitor value of the soft-start capacitor connected at the CAP_SS pin. With a 0.1µF ceramic chip capacitor the ramp time is approximately 4.6V/s. The slow ramping of the signal at the output can be disabled by floating the CAP_SS pin. In addition to the slow ramp feature (soft-start feature) of the in line switches, the part has special click and pop (C/P) shunt circuitry at each of the signal pins (L, R, L1, L2, R1, and R2). A pin’s C/P shunt circuitry is activated or deactivated depending on the logic levels applied at the AC/DC and DIR_SEL control pins. This shunt circuitry serves two functions: 1. In an AC coupled application they are activated and directed to the source side of the switch to suppress or eliminate click/pop noise in the speaker load when powering up or down of the audio CODEC drivers. 2. For superior muting the C/P shunt circuitry is activated and directed to the load side of the switch which gives >120dB of OFF-Isolation when driving a 10k/20k receiver load with an audio signal in the range of 20Hz to 22kHz. If the AC/DC pin is driven LOW, all C/P shunt circuitry at all the signal pins (L, R, L1, R1, L2, and R2) are deactivated and not operable. If the AC/DC pin is driven HIGH, then the logic at the DIR_SEL pin will determine whether the L and R (COM) C/P shunt circuitry is activated or the L1, L2, R1, and R2 (NOx, NCx) C/P shunt circuitry is activated. When the DIR_SEL is driven LOW, the L1, R1, L2, R2 C/P shunt circuitry will be activated while the L and R C/P shunt circuitry will be deactivated. When the DIR_SEL is driven HIGH, the L and R C/P shunt circuitry will be activated while the L1, R1, L2, R2 C/P shunt circuitry will be deactivated. Note: Shunt circuitry that is activated will be turned ON when a switch cell is turned OFF and will be OFF when a switch cell is turned ON. Supply Voltage, Signal Amplitude, and Grounding The power supply connected at VDD or the 5V_Supply pin provides power to the ISL54405 part. The ISL54405 is a single supply device that was designed to be operated with a 3.3V ±10% DC supply connected at the VDD pin or a 5V ±10% DC supply connected at the 5V_Supply pin. It was specifically designed to accept ground referenced 2VRMS (± 2.828VPEAK) audio signals at its signal pins while driving either 10k/20k receiver loads or 32 headphone loads. When using the part in a 3.3V application the 5V_Supply pin should be left floating. A 0.1µF decoupling capacitor should be connected from the VDD pin to ground to minimize power supply noise and transients. This capacitor should be located as close to the pin as possible. The part also has a 5V supply pin (5V_Supply) to allow it to be used in 5V ±10% applications. Special circuitry within the device converts the 5V, connected at the 5V_Supply pin, too 3.3V to properly power the internal circuitry of the device. When using the part in a 5V application the VDD pin should be left floating. A 0.1µF decoupling capacitor should be connected from the 5V_Supply pin to ground to minimize power supply noise. This capacitor should be located as close to the pin as possible. Grounding of the ISL54405 should follow a star configuration (see Figure 8). All grounds of the IC should be directly connected to the power supply ground return without cascading to other grounds. This configuration isolates shunt currents of the Click and Pop transients from the IC ground and optimizes device performance. Mute Operation When the MUTE logic pin is driven HIGH the part will go into the mute state. In the mute state all switches of the SPDTs are open while the T-Shunt switches are closed. In addition any activated click and pop shunt circuitry at the signal pins is turned on. See “Logic Control” on page 10 for more details. MUTE TO ON When the MUTE pin is driven LOW, the ISL54405 will transition to the ON-state in the following sequence: ISL54405 L R MUTE GND1 VDD SEL +3.3V 0.1µF GND2 GND3 L1 R1 LOGIC CONTROL FIGURE 8. STAR GROUNDING CONFIGURATION AC/DC DIR_SEL L2 R2FN6699 Rev 2.00 Page 9 of 20 May 6, 2014

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