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ISL6261CRZ

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ISL6261CRZ

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Part Number ISL6261CRZ
Manufacturer Renesas Electronics America
Description IC CTRLR BUCK 1PHASE 40VFQFN
Datasheet ISL6261CRZ Datasheet
Package 40-VFQFN Exposed Pad
In Stock 331 piece(s)
Unit Price $ 3.4694 *
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 27 - Nov 1 (Choose Expedited Shipping)
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Part Number # ISL6261CRZ (PMIC - Voltage Regulators - Special Purpose) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ISL6261CRZ Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Special Purpose
Datasheet ISL6261CRZDatasheet
Package40-VFQFN Exposed Pad
SeriesRobust Ripple Regulator™ (R3)
ApplicationsConverter, Intel IMVP-6
Voltage - Input5 V ~ 21 V
Number of Outputs1
Voltage - Output0.3 V ~ 1.5 V
Operating Temperature-10°C ~ 100°C
Mounting TypeSurface Mount
Package / Case40-VFQFN Exposed Pad
Supplier Device Package40-QFN (6x6)

ISL6261CRZ Datasheet

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1 ® ISL6261FN9251.1Data Sheet September 27, 2006Single-Phase Core Regulator for IMVP-6® Mobile CPUs The ISL6261 is a single-phase buck regulator implementing lntel® IMVP-6® protocol, with embedded gate drivers. The heart of the ISL6261 is the patented R3 Technology™, Intersil’s Robust Ripple Regulator modulator. Compared with the traditional multi-phase buck regulator, the R3 Technology™ has faster transient response. This is due to the R3 modulator commanding variable switching frequency during a load transient. lntel® Mobile Voltage Positioning (IMVP) is a smart voltage regulation technology effectively reducing power dissipation in lntel® Pentium processors. To boost battery life, the ISL6261 supports DPRSLRVR (deeper sleep) function and maximizes the efficiency via automatically changing operation modes. At heavy load in the active mode, the regulator commands the continuous conduction mode (CCM) operation. When the CPU enters deeper sleep mode, the ISL6261 enables diode emulation to maximize the efficiency at light load. Asserting the FDE pin of the ISL6261 in deeper sleep mode will further decrease the switching frequency at light load and increase the regulator efficiency. A 7-bit digital-to-analog converter (DAC) allows dynamic adjustment of the core output voltage from 0.300V to 1.500V. The ISL6261 has 0.5% system voltage accuracy over temperature. A unity-gain differential amplifier provides remote voltage sensing at the CPU die. This allows the voltage on the CPU die to be accurately measured and regulated per lntel® IMVP-6 specification. Current sensing can be implemented through either lossless inductor DCR sensing or precise resistor sensing. If DCR sensing is used, an NTC thermistor network will thermally compensates the gain and the time constant variations caused by the inductor DCR change. Features • Precision single-phase CORE voltage regulator - 0.5% system accuracy over temperature - Enhanced load line accuracy • Internal gate driver with 2A driving capability • Microprocessor voltage identification input - 7-Bit VID input - 0.300V to 1.500V in 12.5mV steps - Support VID change on-the-fly • Multiple current sensing schemes supported - Lossless inductor DCR current sensing - Precision resistive current sensing • Thermal monitor • User programmable switching frequency • Differential remote voltage sensing at CPU die • Overvoltage, undervoltage, and overcurrent protection • Pb-free plus anneal available (RoHS compliant) Ordering Information PART NUMBER (NOTE) PART MARKING TEMP RANGE (°C) PACKAGE (Pb-FREE) PKG. DWG. # ISL6261CRZ ISL6261CRZ -10 to +100 40 Ld 6x6 QFN L40.6x6 ISL6261CRZ-T ISL6261CRZ -10 to +100 40 Ld 6x6 QFN, T&R L40.6x6 ISL6261CR7Z ISL6261CR7Z -10 to +100 48 Ld 7x7 QFN L48.7x7 ISL6261CR7Z-T ISL6261CR7Z -10 to +100 48 Ld 7x7 QFN, T&R L48.7x7 ISL6261IRZ ISL6261IRZ -40 to +100 40 Ld 6x6 QFN L40.6x6 ISL6261IRZ-T ISL6261IRZ -40 to +100 40 Ld 6x6 QFN, T&R L40.6x6 ISL6261IR7Z ISL6261IR7Z -40 to +100 48 Ld 7x7 QFN L48.7x7 ISL6261IR7Z-T ISL6261IR7Z -40 to +100 48 Ld 7x7 QFN, T&R L48.7x7 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.

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ISL6261Pinouts ISL6261 (40 LD QFN) ISL6261 (48 LD QFN) 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 P G O O D 3 V 3 C L K _ E N D P R S T P # D P R S L P V R V R _O N V ID 6 V ID 5 V ID 4 V ID 3 VID2 VID1 VID0 VCCP LGATE VSSP PHASE UGATE BOOT NC FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB V D IF F V S E N R T N D R O O P D F B V O V S U M V IN V S S V D D GND PAD (BOTTOM) 3 V 3 C L K _ E N # D P R S T P # D P R S L P V R 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 V R _ O N V ID 6 V ID 5 V ID 4 V ID 3 V ID 2 V ID 1 V ID 0 V D IF F V S E N R T N D R O O P D F B V O V S U M V IN V S S V D D N C N C NC NC NC NC NC VCCP LGATE VSSP PHASE UGATE BOOT NC PGOOD FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB NC GND PAD (BOTTOM)2 FN9251.1 September 27, 2006

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ISL6261Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns) Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ) UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT . . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 6x6 QFN Package (Notes 1, 2) . . . . . . 33 5.5 7x7 QFN Package (Notes 1, 2) . . . . . . 30 5.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to +100°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS INPUT POWER SUPPLY +5V Supply Current IVDD VR_ON = 3.3V - 3.1 3.6 mA VR_ON = 0V - - 1 µA +3.3V Supply Current I3V3 No load on CLK_EN# pin - - 1 µA Battery Supply Current at VIN pin IVIN VR_ON = 0, VIN = 25V - - 1 µA POR (Power-On Reset) Threshold PORr VDD Rising - 4.35 4.5 V PORf VDD Falling 3.85 4.1 - V SYSTEM AND REFERENCES System Accuracy %Error (Vcc_core) No load, close loop, active mode, TA = 0°C to +100°C, VID = 0.75-1.5V -0.5 - 0.5 % VID = 0.5-0.7375V -8 - 8 mV VID = 0.3-0.4875V -15 - 15 mV RBIAS Voltage RRBIAS RRBIAS = 147kΩ 1.45 1.47 1.49 V Boot Voltage VBOOT 1.188 1.2 1.212 V Maximum Output Voltage VCC_CORE (max) VID = [0000000] - 1.5 - V Minimum Output Voltage VCC_CORE (min) VID = [1100000] - 0.3 - V VID Off State VID = [1111111] - 0.0 - V CHANNEL FREQUENCY Nominal Channel Frequency fSW RFSET = 7kΩ, Vcomp = 2V - 333 - kHz Adjustment Range 200 - 500 kHz AMPLIFIERS Droop Amplifier Offset -0.3 0.3 mV Error Amp DC Gain (Note 3) AV0 - 90 - dB3 FN9251.1 September 27, 2006

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ISL6261Error Amp Gain-Bandwidth Product (Note 3) GBW CL = 20pF - 18 - MHz Error Amp Slew Rate (Note 3) SR CL = 20pF - 5.0 - V/µs FB Input Current IIN(FB) - 10 150 nA SOFT-START CURRENT Soft-start Current ISS -46 -41 -36 µA Soft Geyserville Current IGV |SOFT - REF|>100mV ±175 ±200 ±225 µA Soft Deeper Sleep Entry Current IC4 DPRSLPVR = 3.3V -46 -41 -36 µA Soft Deeper Sleep Exit Current IC4EA DPRSLPVR = 3.3V 36 41 46 µA Soft Deeper Sleep Exit Current IC4EB DPRSLPVR = 0V 175 200 225 µA GATE DRIVER DRIVING CAPABILITY (Note 4) UGATE Source Resistance RSRC(UGATE) 500mA Source Current - 1 1.5 Ω UGATE Source Current ISRC(UGATE) VUGATE_PHASE = 2.5V - 2 - A UGATE Sink Resistance RSNK(UGATE) 500mA Sink Current - 1 1.5 Ω UGATE Sink Current ISNK(UGATE) VUGATE_PHASE = 2.5V - 2 - A LGATE Source Resistance RSRC(LGATE) 500mA Source Current - 1 1.5 Ω LGATE Source Current ISRC(LGATE) VLGATE = 2.5V - 2 - A LGATE Sink Resistance RSNK(LGATE) 500mA Sink Current - 0.5 0.9 Ω LGATE Sink Current ISNK(LGATE) VLGATE = 2.5V - 4 - A UGATE to PHASE Resistance RP(UGATE) - 1.1 - kΩ GATE DRIVER SWITCHING TIMING (Refer to Timing Diagram) UGATE Turn-on Propagation Delay tPDHU PVCC = 5V, Output Unloaded 20 30 44 ns LGATE Turn-on Propagation Delay tPDHL PVCC = 5V, Output Unloaded 7 15 30 ns BOOTSTRAP DIODE Forward Voltage VDDP = 5V, Forward Bias Current = 2mA 0.43 0.58 0.67 V Leakage VR = 16V - - 1 μA POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage VOL IPGOOD = 4mA - 0.11 0.4 V PGOOD Leakage Current IOH PGOOD = 3.3V -1 - 1 µA PGOOD Delay tpgd CLK_EN# Low to PGOOD High 5.5 6.8 8.1 ms Overvoltage Threshold OVH VO rising above setpoint >1ms 160 200 240 mV Severe Overvoltage Threshold OVHS VO rising above setpoint >0.5µs 1.675 1.7 1.725 V OCSET Reference Current I(Rbias) = 10µA 9.8 10 10.2 µA OC Threshold Offset DROOP rising above OCSET >120µs -3.5 3.5 mV Undervoltage Threshold (VDIFF-SOFT) UVf VO below set point for >1ms -360 -300 -240 mV LOGIC THRESHOLDS VR_ON, DPRSLPVR and PGD_IN Input Low VIL(3.3V) - - 1 V VR_ON, DPRSLPVR and PGD_IN Input High VIH(3.3V) 2.3 - - V Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS4 FN9251.1 September 27, 2006

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ISL6261Gate Driver Timing Diagram Leakage Current on VR_ON and PGD_IN IIL Logic input is low -1 0 - μA IIH Logic input is high - 0 1 μA Leakage Current on DPRSLPVR IIL_DPRSLP DPRSLPVR logic input is low -1 0 - μA IIH_DPRSLP DPRSLPVR logic input is high - 0.45 1 μA DAC(VID0-VID6), PSI# and DPRSTP# Input Low VIL(1.0V) - - 0.3 V DAC(VID0-VID6), PSI# and DPRSTP# Input High VIH(1.0V) 0.7 - - V Leakage Current of DAC(VID0- VID6) and DPRSTP# IIL DPRSLPVR logic input is low -1 0 - μA IIH DPRSLPVR logic input is high - 0.45 1 μA THERMAL MONITOR NTC Source Current NTC = 1.3V 53 60 67 µA Over-temperature Threshold V(NTC) falling 1.17 1.2 1.25 V VR_TT# Low Output Resistance RTT I = 20mA - 5 9 CLK_EN# OUTPUT LEVELS CLK_EN# High Output Voltage VOH 3V3 = 3.3V, I = -4mA 2.9 3.1 - V CLK_EN# Low Output Voltage VOL ICLK_EN# = 4mA - 0.18 0.4 V NOTES: 3. Guaranteed by characterization. 4. Guaranteed by design. Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM UGATE LGATE 1V 1V tPDHL tRL tFU tRU tPDHU tFL5 FN9251.1 September 27, 2006

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ISL6261Functional Pin Description FDE Forced diode emulation enable signal. Logic high of FDE with logic low of DPRSTP# forces the ISL6261 to operate in diode emulation mode with an increased VW-COMP voltage window. PGD_IN Digital Input. Suggest connecting to MCH_PWRGD, which indicates that VCC_MCH voltage is within regulation. RBIAS A 147K resistor to VSS sets internal current reference. VR_TT# Thermal overload output indicator with open-drain output. Over-temperature pull-down resistance is 10. NTC Thermistor input to VR_TT# circuit and a 60µA current source is connected internally to this pin. SOFT A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage. The SOFT pin is the non-inverting input of the error amplifier. OCSET Overcurrent set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A 10µA current source is connected internally to this pin. VW A resistor from this pin to COMP programs the switching frequency (eg. 6.81K = 300kHz). COMP The output of the error amplifier. FB The inverting input of the error amplifier. VDIFF The output of the differential amplifier. VSEN Remote core voltage sense input. RTN Remote core voltage sense return. DROOP The output of the droop amplifier. DROOP-VO voltage is the droop voltage. DFB The inverting input of the droop amplifier. VO An input to the IC that reports the local output voltage. 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 P G O O D 3 V 3 C L K _ E N D P R S T P # D P R S L P V R V R _ O N V ID 6 V ID 5 V ID 4 V ID 3 VID2 VID1 VID0 VCCP LGATE VSSP PHASE UGATE BOOT NC FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB V D IF F V S E N R T N D R O O P D F B V O V S U M V IN V S S V D D GND PAD (BOTTOM)6 FN9251.1 September 27, 2006

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ISL6261VSUM This pin is connected to one terminal of the capacitor in the current sensing R-C network. VIN Power stage input voltage. It is used for input voltage feed forward to improve the input line transient performance. VSS Signal ground. Connect to controller local ground. VDD 5V control power supply. BOOT Upper gate driver supply voltage. An internal bootstrap diode is connected to the VCCP pin. UGATE The upper-side MOSFET gate signal. PHASE The phase node. This pin should connect to the source of upper MOSFET. VSSP The return path of the lower gate driver. LGATE The lower-side MOSFET gate signal. VCCP 5V power supply for the gate driver. NC Not connected. Ground this pin in the practical layout. VID0, VID1, VID2, VID3, VID4, VID5, VID6 VID input with VID0 as the least significant bit (LSB) and VID6 as the most significant bit (MSB). VR_ON VR enable pin. A logic high signal on this pin enables the regulator. DPRSLPVR Deeper sleep enable signal. A logic high indicates that the microprocessor is in Deeper Sleep Mode and also indicates a slow Vo slew rate with 41μA discharging or charging the SOFT cap. DPRSTP# Deeper sleep slow wake up signal. A logic low signal on this pin indicates that the microprocessor is in Deeper Sleep Mode. CLK_EN# Digital output for system PLL clock. Goes active 20µs after PGD_IN is active and Vcore is within 10% of boot voltage. 3V3 3.3V supply voltage for CLK_EN#. PGOOD Power good open-drain output. Needs to be pulled up externally by a 680 resistor to VCCP or 1.9k to 3.3V.7 FN9251.1 September 27, 2006

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ISL6261Function Block Diagram FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261 D R O O P O C S E T V S U M D F B D R O O P 1 1 V O O C S O F T V O V S E N V O R T N V D IF F E /A S O F T F B 1 0 u A V W C O M P M O D U L A T O R O C V IN V S O F T V W D R IV E R L O G IC F L T F A U L T A N D P G O O D L O G IC P G O O D M O N IT O R A N D L O G IC M O D E C O N T R O L V R _ O N F D E D P R S L P V R D P R S T P # V ID 0 V ID 1 V ID 2 V ID 3 V ID 4 V ID 5 V ID 6 D A C P G D _ IN C L K _ E N # P G O O D 3 V 3 R B IA S F L T P G O O D G N D L G A T E V S S P P H A S E U G A T E B O O T V C C P V C C P V R _ T T # N T C 1 .2 2 V 6 0 u A V IN V IN V D D V C C P V C C P V S S 8 FN9251.1 September 27, 2006

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ISL6261Simplified Application Circuit for DCR Current Sensing FIGURE 2. ISL6261-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING VSUM VO OCSET DFB DROOP VSSP LGATE PHASE BOOT UGATE VIN VCCPVDD3V3 VW COMP FB VDIFF RBIAS NTC VR_TT# SOFT VIDs DPRSTP# DPRSLPVR FDE PGD_IN CLK_EN# VR_ON PGOOD VR_TT# VID<0:6> DPRSTP# DPRSLPVR MCH_PWRGD CLK_ENABLE# VR_ON IMVP6_PWRGD ISL6261 Lo Co Vo VinV+5V+3.3 VSS R4 R5 R6 R7 R1 R2 R3 R8 R10 R11 R12 C1 C2 C3 C4 C5 C7 C6 C8 C10 VSENVCC-SENSE RTNVSS-SENSE C9 R9 NTC Network9 FN9251.1 September 27, 2006

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Maxw*****Haynes

August 11, 2020

Very supportive of my small orders, but very glad easy to work with. Hard to see how it could be any more efficient!

Terr***** Samra

August 9, 2020

Perfect, functional, arrived a weeks earlier, excellent Seller. Recommended

Elai*****raves

August 6, 2020

I am always amazed at the cost of automotive or marine costs when a rectifier is needed while these will do the exact same thing if you are a bit technically minded to wire them up.

Lac*****Hill

August 2, 2020

As I said before, your crew rock's keep up the fantastic work as we need you out there.

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