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ISL6539CA-T

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ISL6539CA-T

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Part Number ISL6539CA-T
Manufacturer Renesas Electronics America
Description IC CTRLR DDR DRAM, SDRAM 28QSOP
Datasheet ISL6539CA-T Datasheet
Package 28-SSOP (0.154", 3.90mm Width)
In Stock 3,860 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 28 - Nov 2 (Choose Expedited Shipping)
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Part Number # ISL6539CA-T (PMIC - Voltage Regulators - Special Purpose) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ISL6539CA-T Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Special Purpose
Datasheet ISL6539CA-TDatasheet
Package28-SSOP (0.154", 3.90mm Width)
Series-
ApplicationsController, DDR DRAM, SDRAM
Voltage - Input3.3 V ~ 18 V
Number of Outputs2
Voltage - Output0.9 V ~ 5.5 V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case28-SSOP (0.154", 3.90mm Width)
Supplier Device Package28-SSOP/QSOP

ISL6539CA-T Datasheet

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FN9144 Rev 6.00 Apr 29, 2010 ISL6539 Wide Input Range Dual PWM Controller with DDR Option DATASHEETThe ISL6539 dual PWM controller delivers high efficiency and tight regulation from two voltage regulating synchronous buck DC/DC converters. It was designed especially for DDR DRAM, SDRAM, graphic chipset applications, and system regulators in high performance applications. Voltage-feed-forward ramp modulation, current mode control, and internal feedback compensation provide fast response to input voltage and output load transients. Input current ripple is minimized by channel-to-channel PWM phase shift of 0°, 90° or 180° (determined by input voltage and status of the DDR pin). The ISL6539 can control two independent output voltages adjustable from 0.9V to 5.5V or, by activating the DDR pin, transform into a complete DDR memory power supply solution. In DDR mode, CH2 output voltage VTT tracks CH1 output voltage VDDQ. CH2 output can both source and sink current, an essential power supply feature for DDR memory. The reference voltage VREF required by DDR memory is generated as well. In dual power supply applications the ISL6539 monitors the output voltage of both CH1 and CH2. An independent PGOOD (power good) signal is asserted for each channel after the soft-start sequence has completed, and the output voltage is within PGOOD window. In DDR mode CH1 generates the only PGOOD signal. Built-in overvoltage protection prevents the output from going above 115% of the set point by holding the lower MOSFET on and the upper MOSFET off. When the output voltage decays below the overvoltage threshold, normal operation automatically resumes. Once the soft-start sequence has completed, undervoltage protection latches the offending channel off if the output drops below 75% of its set point value for the dual switcher. Adjustable overcurrent protection (OCP) monitors the voltage drop across the rDS(ON) of the lower MOSFET. If more precise current-sensing is required, an external current sense resistor may be used. Features • Provides Regulated Output Voltage in the Range of 0.9V to 5.5V • Complete DDR Memory Power Solution with VTT Tracks VDDQ/2 and VDDQ/2 Buffered Reference Output • Supports both DDR-I and DDR2 Memory • Lossless rDS(ON) Current-Sense Sensing • Excellent Dynamic Response with Voltage Feed-Forward and Current Mode Control Accommodating Wide Range LC Filter Selections • Dual Mode Operation - Operates Directly from a 5.0V to 15V Input or 3.3V/5V System Rail • Undervoltage Lock-out on VCC Pin • Power-good, Overcurrent, Overvoltage, Undervoltage protection for both Channels • Synchronized 300kHz PWM Operation in PWM Mode • Pb-Free (RoHS Compliant) Applications • Single and Dual Channel DDR Memory Power Systems • Graphics Cards - GPU and Memory Supplies • Supplies for Servers, Motherboards, FPGAs • ASIC Power Supplies • Embedded Processor and I/O Supplies • DSP SuppliesFN9144 Rev 6.00 Page 1 of 20 Apr 29, 2010

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ISL6539Pinout ISL6539 (28 LD QSOP) TOP VIEW Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL6539IAZ* (Note) ISL 6539IAZ -40 to +85 28 Ld QSOP (Pb-free) M28.15 ISL6539CAZ* (Note) ISL 6539CAZ -40 to +85 28 Ld QSOP (Pb-free) M28.15 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. EN1 GND DDR VSEN1 VIN PG1 GND ISEN1 LGATE1 PGND1 BOOT1 UGATE1 PHASE1 ISEN2 LGATE2 PGND2 BOOT2 UGATE2 PHASE2 EN2 VSEN2 GND OCSET2OCSET1 SOFT1 SOFT2 PG2/REF VCC28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14FN9144 Rev 6.00 Page 2 of 20 Apr 29, 2010

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ISL6539Generic Application Circuits VOUT1 VOUT2 L1Q1 Q2 OCSET1 DDR FIGURE 1. ISL6539 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY PWM1 PWM2 L2 Q3 Q4 C2 OCSET2 VCC EN2 EN1 + C1 + 5V VIN 5.0V TO 15V 3.3V OR FIGURE 2. ISL6539 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY VDDQ VTT L1 Q1 Q2 OCSET1 DDR PWM1 PWM2 L2 Q3 Q4 OCSET2 VCC EN2 EN1 5V VREF PG2/VREF C1 + C2 + VIN 5.0V TO 15V 3.3V ORFN9144 Rev 6.00 Page 3 of 20 Apr 29, 2010

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ISL6539Absolute Maximum Ratings Bias Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18.0V PHASE, UGATE . . . . . . . . . . . . . . . . . .GND - 5V (Note 1) to +24.0V BOOT, ISEN . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +24.0V BOOT with Respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V All Other Pins . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V Thermal Information Thermal Resistance (Typical, Note 2) JA (°C/W) QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V 5% Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . .+3.3V or 5.0V to +18.0V Ambient Temperature Range, Commercial . . . . . . . . . 0°C to +70°C Junction Temperature Range, Commercial . . . . . . . . 0°C to +125°C Ambient Temperature Range, Industrial . . . . . . . . . . -40°C to +85°C Junction Temperature Range, Industrial . . . . . . . . . -40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. 250ns transient. See “Confining the Negative Phase Node Voltage Swing with Schottky Diode” on page 17. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY Bias Current ICC LGATEx, UGATEx Open, VSENx forced above regulation point, DDR = 0, VIN >5V - 1.8 3.0 mA Shut-Down Current ICCSN - - 1 µA VCC UVLO Rising VCC Threshold VCCU 4.30 4.45 4.50 V Falling VCC Threshold VCCD 4.00 4.14 4.34 V VIN Input Voltage Pin Current (Sink) IVIN - - 35 µA Shut-Down Current IVINS - - 1 µA OSCILLATOR Oscillator Frequency fOSC ISL6539C 255 300 345 kHz ISL6539I 245 300 345 kHz Ramp Amplitude, Peak-to-Peak VR1 VIN pin voltage = 16V (Note 3) - 2 - V Ramp Amplitude, Peak-to-Peak VR2 VIN pin voltage = 5V (Note 3) - 0.625 - V Ramp Offset VROFF (Note 3) - 1 - V Ramp/VIN Gain GRB1 VIN pin voltage > 4.2V (Note 3) - 125 - mV/V Ramp/VIN Gain GRB2 VIN pin voltage  4.1V (Note 3) - 250 - mV/V REFERENCE AND SOFT-START Internal Reference Voltage VREF - 0.9 - V Reference Voltage Accuracy -1.0 - +1.0 % Soft-Start Current During Start-Up ISOFT - 4.5 - µA Soft-Start Complete Threshold VST (Note 3) - 1.5 - VFN9144 Rev 6.00 Page 4 of 20 Apr 29, 2010

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ISL6539Functional Pin Description GND (Pin 1, 9, 20) Signal ground for the IC. All three ground pins must be connected to ground for proper IC operation. Connect to the ground plane through a path as low in inductance as possible. LGATE1, LGATE2 (Pin 2, 27) Connect these pins to the gates of the corresponding lower MOSFETs. These pins provide the PWM-controlled gate drive for the lower MOSFETs. PGND1, PGND2 (Pin 3, 26) These pins provide the return connection for lower gate drivers, and are connected to sources of the lower MOSFETs of their respective converters. These pins must be connected to the ground plane through a path as low in inductance as possible. PHASE1, PHASE2 (Pin 4, 25) The PHASE1 and PHASE2 points are the junction points of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect these pins to the respective converter’s upper MOSFET source. UGATE1, UGATE2 (Pin 5, 24) Connect these pins to the gates of the corresponding upper MOSFETs. These pins provide the PWM-controlled gate drive for the upper MOSFETs. BOOT1, BOOT2 (Pin 6, 23) These pins power the upper MOSFET drivers of the PWM converter. Connect these pins to the junction of the bootstrap PWM CONVERTERS Load Regulation 0.0mA < IVOUT1 <5.0A; 5.0V < VIN <15.0V -2.0 - +2.0 % VSEN Pin Bias Current IVSEN (Note 3) - 80 - nA Minimum Duty Cycle DMIN - 4 - % Maximum Duty Cycle DMAX - 87 - % Undervoltage Shut-Down Level VUVL Fraction of the set point; ~2µs noise filter 70 75 80 % Overvoltage Protection VOVP1 Fraction of the set point; ~2µs noise filter 110 115 - % GATE DRIVERS Upper Drive Pull-Up Resistance R2UGPUP VCC = 5V - 4 8  Upper Drive Pull-Down Resistance R2UGPDN VCC = 5V - 2.3 4  Lower Drive Pull-Up Resistance R2LGPUP VCC = 5V - 4 8  Lower Drive Pull-Down Resistance R2LGPDN VCC = 5V - 1.1 3  POWER GOOD AND CONTROL FUNCTIONS Power Good Lower Threshold VPG- Fraction of the set point; ~3µs noise filter 84 89 92 % Power Good Higher Threshold VPG+ Fraction of the set point; ~3µs noise filter. 110 115 120 % PGOODx Leakage Current IPGLKG VPULLUP = 5.5V - - 1 µA PGOODx Voltage Low VPGOOD IPGOOD = -4mA - 0.5 1 V ISEN Sourcing Current (Note 3) - - 260 µA OCSET Sourcing Current Range 2 - 20 µA EN - Low (Off) - - 0.8 V EN - High (On) 2.0 - - V DDR - Low (Off) - - 0.8 V DDR - High (On) 3 - - V DDR REF Output Voltage VDDREF DDR = 1, IREF = 0...10mA 0.99* VOC2 VOC2 1.01* VOC2 V DDR REF Output Current IDDREF DDR = 1 (Note 3) - 10 12 mA NOTES: 3. Limits should be considered typical and are not production tested. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITSFN9144 Rev 6.00 Page 5 of 20 Apr 29, 2010

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ISL6539capacitor with the cathode of the bootstrap diode. The anode of the bootstrap diode is connected to the VCC voltage. ISEN1, ISEN2 (Pin 7, 22) These pins are used to monitor the voltage drop across the lower MOSFET for current feedback and overcurrent protection. For precise current detection these inputs can be connected to the optional current sense resistors placed in series with the source of the lower MOSFETs. EN1, EN2 (Pin 8, 21) These pins enable operation of the respective converter when high. When both pins are low, the chip is disabled and only low leakage current is taken from VCC and VIN. EN1 and EN2 can be used independently to enable either Channel 1 or Channel 2, respectively. VSEN1, VSEN2 (Pin 10, 19) These pins are connected to the resistive dividers that set the desired output voltage. The PGOOD, UVP, and OVP circuits use this signal to report output voltage status. OCSET1 (Pin 11) This pin is a buffered 0.9V internal reference voltage. A resistor from this pin to ground sets the overcurrent threshold for the first controller. SOFT1, SOFT2 (Pin 12, 17) These pins provide soft-start function for their respective controllers. When the chip is enabled, the regulated 5µA pull-up current source charges the capacitor connected from the pin to ground. The output voltage of the converter follows the ramping voltage on the SOFT pin in the soft-start process with the SOFT pin voltage as reference. When the SOFT pin voltage is higher than 0.9V, the error amplifier will use the internal 0.9V reference to regulate output voltage. In the event of undervoltage and overcurrent shutdown, the soft-start pin is pulled down through a 2k resistor to ground to discharge the soft-start capacitor. DDR (Pin 13) When the DDR pin is low, the chip can be used as a dual switcher controller. The output voltage of the two channels can be programmed independently by VSENx pin resistor dividers. The PWM signals of Channel 1 and Channel 2 will be synchronized 180° out-of-phase. When the DDR pin is high, the chip transforms into a complete DDR memory solution. The OCSET2 pin becomes an input through a resistor divider tracking to VDDQ/2. The PG2/REF pin becomes the output of the VDDQ/2 buffered voltage. The VDDQ/2 voltage is also used as the reference to the error amplifier by the second channel. The channel phase-shift synchronization is determined by the VIN pin when DDR = 1 as described in VIN (Pin 14). VIN (Pin 14) This pin has multiple functions. When connected to the input voltage, it provides a feed-forward input to the oscillator for the rejection of input voltage variation. The ramp of the PWM comparator is proportional to the voltage on this pin (see Table 1 and Table 2 for details). While the DDR pin is high (in the DDR application) and when the VIN pin voltage is tied to 5V, it commands 90° out-of-phase channel synchronization, with the second channel lagging the first channel, to reduce inter-channel interference. While the DDR pin is high (in the DDR application) and when the VIN pin voltage is tied to ground, it commands in-phase channel synchronization. PG1 (Pin 15) PGOOD1 is an open drain output used to indicate the status of the output voltage. This pin is pulled low when the first channel output is out of ±11% of the set value. PG2/REF (Pin 16) This pin has a double function, depending on the mode of operation. When the chip is used as a dual channel PWM controller (DDR = 0), the pin provides an open drain PGOOD2 function for the second channel the same way as PG1. The pin is pulled low when the second channel output is out of ±11% of the set value. In DDR mode (DDR = 1), this pin is the output of the buffer amplifier that takes VDDQ/2 voltage applied to OCSET2 pin from the resistor divider. It can source a typical 10mA current. OCSET2 (Pin 18) In a dual channel application with DDR = 0, a resistor from this pin to ground sets the overcurrent threshold for the second channel controller. Its voltage is the buffered internal 0.9V reference. In the DDR application with DDR = 1, this pin connects to the center point of a resistor divider tracking the VDDQ/2. This voltage is then buffered by an amplifier voltage follower and sent to the PG2/REF pin. It sets the reference voltage of Channel 2 for its regulation. VCC (Pin 28) VCC provides the bias supply for the ISL6539. The supply to VCC should be locally bypassed using a ceramic capacitor. Typical Application Figures 3 and 4 show the application circuits of a dual channel DC/DC converter. The power supply in Figure 3 provides +V2.5 and +V1.8 voltages for memory and the graphics interface chipset from a 5.0VDC to 15VDC input rail. Figure 4 illustrates the application circuit for a DDR memory power solution. The power supply shown in Figure 4 generates +2.5V VDDQ voltage. The +1.25V VTT termination voltage tracks VDDQ/2 and is derived from +2.5V VDDQ. To complete the DDR memory power requirements, the +1.25V reference voltage is provided through the PG2 pin. In this application circuit shown, two output 220µF capacitors are used at the outputs.FN9144 Rev 6.00 Page 6 of 20 Apr 29, 2010

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ISL6539RS1 2.0k RS2 2.0k Q1 LO1 CO11 4.7µF D2 BAT54W RBT1 LO2 Q2 10µF CO21 220µF CO22 4.7 µF RSET1 100k CSOFT1 10k CFB1 0.01 F SOFT1 PG1 OCSET1 EN1 GND VSEN1 PGND1 LGATE1 ISEN1 PHASE1 UGATE1 BOOT1 GND VCC VIN PGND2 LGATE2 ISEN2 PHASE2 UGATE2 BOOT2 GND PG2 SOFT2 V1 (2.5V) V2 (1.8V) DDR EN2 VCC (5V) U1 FDS6912A FDS6912A 4.7µH CIN1 10µF CDC D1 BAT54W 0 CBT2RBT2 0 CIN2 0.01µF RFB11 17.8k RFB12 VIN CO13 220µF ISL6539 OCSET2 VSEN2 RFB21 10k RFB22 10k CFB2 CSOFT2 0.01µFRSET2 100k µ 0.01µF 4.7µF 4.7µH CB11 0.15µF 0.15µF FIGURE 3. TYPICAL APPLICATION CIRCUIT AS DUAL SWITCHER, VOUT1 = 2.5V, VOUT2 = 1.8V FIGURE 4. TYPICAL APPLICATION AS DDR MEMORY POWER SUPPLY, VOUT1 = 2.5V, VOUT2 = 1.25V RS1 2.0k RS2 1.0k Q1 LO1 4.6µF CO11 CIN1 CDC 4.7µF D1 BAT54W RBT1 0 CBT1 0.15µF 0.15µF RBT2 0 Q2 CO21 220µF CO22 4.7µF RSET1 100k CSOFT1 0.01µF RFB1 RFB12 10k CFB1 0.01µF SOFT1 PG1 OCSET1 EN1 GND VSEN1 PGND1 LGATE1 ISEN1 PHASE1 UGATE1 BOOT1 VCC VIN OCSET2_VDDQ/2 PG2_REF PGND2 LGATE2 ISEN2 PHASE2 UGATE2 BOOT2 VSEN2 GND SOFT2 VREF (VDDQ/2) RD1 10k VDDQ VDDQ/2 RD2 10k CF 0.1µF VDDQ (2.5V) VTT (1.25V) CREF DDR CO13 220µF EN2 VCC (5V) CSOFT2 (N/U) U1 FDS6912A FDS6912A 4.7µF 10µF D2 BAT54W LO2 1.5µH CIN2 4.7µF 17.8k GND VIN VDDQ 4.7µF 0.01µFISL6539 CBT2FN9144 Rev 6.00 Page 7 of 20 Apr 29, 2010

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F N 9 14 4 R e v 6 .0 0 P ag e 8 of 2 0 A pr 29, 2010 IS L6 5 39 MP 2 E DEAD-TIME VSEN2 1M .25pF 500k 300k + 0.9V ISEN2140 SAMPLE CURRENT PHASE2 PGND2 UGATE2 BOOT2 LGATE2 VCC EMULATION PLE TIMING + REFERENCE OCSET2 1/2.9 OCSET2 DDR = 0 DDR = 1 DDR VTT DDR = 0 DDR = 1 REFERENCE DDR VREF BUFFER AMP SOFT2 REF (200k, DDR = 1) - + - + - + - + Block Diagram ERROR AMP 1 VSEN1 300k PWM1 + 0.9V ISEN1 140 SAMPLE CURRENTSAMPLE CURRENT PHASE1 PGND1 UGATE1 BOOT1 LGATE1 VCC + 0.9V REFERENCE OCSET1 1/2.9 OCSET1 1/33.1 ISEN1 ERROR A ADAPTIV 16.7pF 1 PWM2 SAMPLE CURRENT DIODE V/I SAM 0.9V 1/33.1 ISEN2 DDRVIN VCC DUTY CYCLE RAMP GENERATOR PWM CHANNEL PHASE CONTROL OC2OC1 8 CLOCK CYCLES SAME STATE FOR REQUIRED TO LATCH OVERCURRENT FAULT 8 CLOCK CYCLES SAME STATE FOR REQUIRED TO LATCH OVERCURRENT FAULT VCCPG1 OV UV PGOOD DDR = 1 DDR = 0 1.25pF 500k 1M 16.7pF OV UV PGOOD ADAPTIVE DEAD-TIME DIODE EMULATION V/I SAMPLE TIMING OC1 DDR POR FAULT LATCH BIAS SUPPLIES REFERENCE ENABLE SOFT-START GNDEN1 EN2 REF/PG2 SOFT1 DDR MODE CONTROL OC2 REF 4.4k 4.4k - + - + - + - + - + - + DDR EN1 EN2 VIN CH1 CH2  0 1 1 5V  15.0V 180° 1 1 1 VIN = 5V 90° VIN = GND 0°

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ISL6539Theory of Operation Operation The ISL6539 is a dual channel PWM controller intended for use in power supplies for graphic chipsets, SDRAM, DDR DRAM, or other power applications. The IC integrates two control circuits for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistive divider. The synchronous buck converters can operate from either an unregulated DC source with a voltage ranging from 5.0V to 15V, or from a regulated system rail of 3.3V or 5V. In either operational mode the controller is biased from the +5V source. The controllers operate in the current mode with input voltage feed-forward which simplifies feedback loop compensation and rejects input voltage variation. An integrated feedback loop compensation dramatically reduces the number of external components. The ISL6539 has a special means to rearrange its internal architecture into a complete DDR solution. When the DDR pin is set high, the second channel can provide the capability to track the output voltage of the first channel. The buffered reference voltage required by DDR memory chips is also provided. Initialization The ISL6539 initializes if at least one of the enable pins is set high. The Power-On Reset (POR) function continually monitors the bias supply voltage on the VCC pin, and initiates soft-start operation when EN1 or EN2 is high after the input supply voltage exceeds 4.45V. Should this voltage drop lower than 4.14V, the POR disables the chip. Soft-Start When soft-start is initiated, the voltage on the SOFT pin of the enabled channel starts to ramp up gradually with the internal 5µA current charging the soft-start capacitor. The output voltage follows the soft-start voltage. When the SOFT pin voltage reaches 0.9V, the output voltage comes into regulation. When the SOFT voltage reaches 1.5V, the power good (PGOOD) is enabled. The soft-start process is depicted in Figure 5. Even though the soft-start pin voltage continues to rise after reaching 1.5V, this voltage does not affect the output voltage. The soft-start time (the time from the moment when EN becomes high to the moment when PGOOD is reported) is determined by Equation 1: The time it takes the output voltage to come into regulation can be obtained from Equation 2: During soft-start, before the PGOOD pin is enabled, the undervoltage protection is prohibited. The overvoltage and overcurrent protection functions are enabled. If the output capacitor has residue voltage before start-up, both lower and upper MOSFETs are in off-state until the soft-start capacitor charges equal the VSEN pin voltage. This will ensure the output voltage starts from its existing voltage level. Output Voltage Program The output voltage of either channel is set by a resistive divider from the output to ground. The center point of the divider is connected to the VSEN pin as shown in Figure 6. The output voltage value is determined by Equation 3. where 0.9V is the value of the internal reference. The VSEN pin voltage is also used by the controller for the power good function and to detect undervoltage and overvoltage conditions. Ch3 1.0V Ch2 2.0V Ch4 5.0V M1.00ms Ch1 5.0V 3 2 4 1 EN 0.9V 1.5V SOF T VOUT PGOOD FIGURE 5. START-UP TSOFT 1.5V Csoft 5A ----------------------------------= (EQ. 1) TRISE 0.6 TSOFT= (EQ. 2) VO 0.9V R1 R2+  R2 ---------------------------------------------= (EQ. 3)FN9144 Rev 6.00 Page 9 of 20 Apr 29, 2010

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