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ISL6553CB

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ISL6553CB

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Part Number ISL6553CB
Manufacturer Renesas Electronics America
Description IC REG CTRLR BUCK 16SOIC
Datasheet ISL6553CB Datasheet
Package 16-SOIC (0.154", 3.90mm Width)
In Stock 7,252 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # ISL6553CB (PMIC - Voltage Regulators - DC DC Switching Controllers) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ISL6553CB Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - DC DC Switching Controllers
Datasheet ISL6553CBDatasheet
Package16-SOIC (0.154", 3.90mm Width)
Series-
Output TypePWM Signal
FunctionStep-Down
Output ConfigurationPositive
TopologyBuck
Number of Outputs2
Output Phases2
Voltage - Supply (Vcc/Vdd)4.75 V ~ 5.25 V
Frequency - Switching50kHz ~ 1.5MHz
Duty Cycle (Max)-
Synchronous Rectifier-
Clock SyncNo
Serial Interfaces-
Control FeaturesEnable, Frequency Control, Power Good
Operating Temperature0°C ~ 70°C (TA)
Package / Case16-SOIC (0.154", 3.90mm Width)
Supplier Device Package16-SOIC

ISL6553CB Datasheet

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FN4931 Rev 1.00 August 2004 ISL6553 Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller DATASHEETNOT RECOMMENDED FOR NEW DESIGN S NO RECOMMENDED REPLACEMENT contact our Technica l Support Center at 1-888-INTERSIL or w ww.intersil.com/tscThe ISL6553 multi-phase PWM control IC together with its companion gate drivers, the HIP6601, HIP6602 or HIP6603 provides a precision voltage regulation system for advanced microprocessors. Multi-phase power conversion is a marked departure from earlier single phase converter configurations previously employed to satisfy the ever increasing current demands of modern microprocessors. Multi-phase converters, by distributing the power and load current results in smaller and lower cost transistors with fewer input and output capacitors. These reductions accrue from the higher effective conversion frequency with higher frequency ripple current due to the phase interleaving process of this topology. For example, a two phase converter operating at 350kHz will have a ripple frequency of 700kHz. Moreover, greater converter bandwidth of this design results in faster response to load transients. Outstanding features of this controller IC include programmable VID codes from the microprocessor that range from 1.05V to 1.825V with a system accuracy of 1%. Pull up currents on these VID pins eliminates the need for external pull up resistors. In addition “droop” compensation, used to reduce the overshoot or undershoot of the CORE voltage, is easily programmed with a single resistor. Another feature of this controller IC is the PGOOD monitor circuit which is held low until the CORE voltage increases, during its Soft-Start sequence, to within 10% of the programmed voltage. Over-voltage, 15% above programmed CORE voltage, results in the converter shutting down and turning the lower MOSFETs ON to clamp and protect the microprocessor. Under voltage is also detected and results in PGOOD low if the CORE voltage falls 10% below the programmed level. Over-current protection reduces the regulator RMS output current to 41% of the programmed over-current trip value. These features provide monitoring and protection for the microprocessor and power system. Features • Multi-Phase Power Conversion • Precision Channel Current Sharing - Loss Less Current Sampling - Uses rDS(ON) • Precision CORE Voltage Regulation - 1% System Accuracy Over Temperature • Microprocessor Voltage Identification Input - 5-Bit VID Input - 1.05V to 1.825V in 25mV Steps - Programmable “Droop” Voltage • Fast Transient Recovery Time • Over Current Protection • High Ripple Frequency, (Channel Frequency) Times Number Channels . . . . . . . . . . . . . . . . . .100kHz to 3MHz • Pb-free available Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Pinout ISL6553 (SOIC) TOP VIEW Ordering Information PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. # ISL6553CB 0 to 70 16 Ld SOIC M16.15 ISL6553CBZ (Note) 0 to 70 16 Ld SOIC (Pb-free) M16.15 ISL6553EVAL1 Evaluation Platform *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. VID3 VID2 VID1 VID0 VID25mV FS/DIS VSEN PGOOD PWM1 PWM2 VCC FB ISEN1 COMP ISEN2 GND 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 FN4931 Rev 1.00 Page 1 of 15 August 2004

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ISL6553Block Diagram Simplified Power System Diagram   D/A CURRENT CORRECTION OV LATCH POWER-ON RESET (POR) X1.15 SOFT- START AND FAULT LOGIC + - + - UV OVP + - E/A + - PWM PWM OC + - PWM1 PWM2 ISEN1 ISEN2 GND PGOOD VCC FB I_TRIP FS/EN S STATE I_TOT + - + - + + - CLOCK AND THREE VID3 VID2 VID1 VID0 VID25mV COMP VSEN GENERATOR SAWTOOTH +  X 0.9 SYNCHRONOUS ISL6553 MICROPROCESSOR VSEN VID RECTIFIED BUCK CHANNEL SYNCHRONOUS RECTIFIED BUCK CHANNEL PWM 1 PWM 2FN4931 Rev 1.00 Page 2 of 15 August 2004

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ISL6553Functional Pin Description VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3), VID0 (Pin 4) and VID25mV (Pin 5) Voltage Identification inputs from microprocessor. These pins respond to TTL and 3.3V logic signals. The ISL6553 decodes VID bits to establish the output voltage. See Table 1. COMP (Pin 6) Output of the internal error amplifier. Connect this pin to the external feedback and compensation network. FB (Pin 7) Inverting input of the internal error amplifier. FS/DIS (Pin 8) Channel frequency, FSW, select and disable. A resistor from this pin to ground sets the switching frequency of the converter. Pulling this pin to ground disables the converter and three states the PWM outputs. See Figure 10. GND (Pin 9) Bias and reference ground. All signals are referenced to this pin. VSEN (Pin 10) Power good monitor input. Connect to the microprocessor- CORE voltage. ISEN2 (Pin 11) and ISEN1 (Pin 14) Current sense inputs from the individual converter channel’s phase nodes. PWM2 (Pin 12) and PWM1 (Pin 13) PWM outputs for each driven channel in use. Connect these pins to the PWM input of a HIP6601/2/3 driver. PGOOD (Pin 15) Power good. This pin provides a logic-high signal when the microprocessor CORE voltage (VSEN pin) is within specified limits and Soft-Start has timed out. VCC (Pin 16) Bias supply. Connect this pin to a 5V supply. Typical Application - Two Phase Converter Using HIP6601 Gate Drivers VID3 VID2 VID1 VID0 VID25mV FS/DIS VSEN PGOOD PWM1 PWM2 VCC FB ISEN1 COMP ISEN2 GND 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 MAIN CONTROL ISL6553 VID2 VID25mV PGOOD FB +5V COMP PWM2 PWM1 ISEN2 ISEN1 VSEN DRIVER HIP6601PWM VCC BOOT UGATE PHASE LGATE VIN = +5V PVCC PWM VCC BOOT UGATE PHASE LGATE VIN = +5V DRIVER HIP6601 PVCC FS/DIS GND GND GND VCC +VCORE +12V +12V VID1 VID3 VID0FN4931 Rev 1.00 Page 3 of 15 August 2004

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ISL6553Typical Application - Two Phase Converter Using an HIP6602 Gate Driver MAIN CONTROL ISL6553 VID2 VID1 VID0 VID25mV FB +5V COMP PWM1 PWM2 ISEN2 VSEN FS/DIS ISEN1 GND VIN +12VBOOT2 UGATE2 PHASE2 LGATE2 BOOT1 UGATE1 PHASE1 LGATE1PWM1 PVCC +5V VCC VIN = +12V+12V DUAL DRIVER HIP6602 PGOOD GND VCC +VCORE L01 L02 PWM2 VID3FN4931 Rev 1.00 Page 4 of 15 August 2004

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ISL6553Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V Input, Output, or I/O Voltage . . . . . . . . . GND -0.3V to VVCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD Recommended Operating Conditions Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Thermal Information Thermal Resistance (Typical, Note 1) JA ( oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS INPUT SUPPLY POWER Input Supply Current RT = 100k, Active and Disabled Maximum Limit - 10 15 mA POR (Power-On Reset) Threshold VCC Rising 4.25 4.38 4.5 V VCC Falling 3.75 3.88 4.00 V REFERENCE AND DAC DAC Voltage Accuracy -1 - 1 % DAC Pin Input Low Voltage Threshold - - 0.8 V DAC Pin Input High Voltage Threshold 2.0 - - V VID Pull-Up VIDx = 0V or VIDx = 3V 10 20 40 A OSCILLATOR Frequency, FSW RT = 100k, 1% 245 275 305 kHz Adjustment Range See Figure 10 0.05 - 1.5 MHz Disable Voltage Maximum Voltage at FS/DIS to Disable Controller. IFS/DIS = 1mA - - 1.0 V ERROR AMPLIFIER DC Gain RL = 10K to GND - 72 - dB Gain-Bandwidth Product CL = 100pF, RL = 10K to GND - 18 - MHz Slew Rate CL = 100pF, Load = 400A - 5.3 - V/s Maximum Output Voltage RL = 10K to GND, Load = 400A 3.6 4.1 - V Minimum Output Voltage RL = 10K to GND, Load = -400A - 0.16 0.5 V ISEN Full Scale Input Current - 50 - A Over-Current Trip Level - 82.5 - A POWER GOOD MONITOR Under-Voltage Threshold VSEN Rising - 0.92 - VDAC Under-Voltage Threshold VSEN Falling - 0.90 - VDAC PGOOD Low Output Voltage IPGOOD = 4mA - 0.18 0.4 V PROTECTION Over-Voltage Threshold VSEN Rising 1.12 1.15 1.2 VDAC Percent Over-Voltage Hysteresis VSEN Falling after Over-Voltage - 2 - %FN4931 Rev 1.00 Page 5 of 15 August 2004

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ISL6553Operation Figure 1 shows a simplified diagram of the voltage regulation and current control loops. Both voltage and current feedback are used to precisely regulate voltage and tightly control output currents, IL1 and IL2, of the two power channels. The voltage loop comprises the Error Amplifier, Comparators, gate drivers and output MOSFETs. The Error Amplifier is essentially connected as a voltage follower that has as an input, the Programmable Reference DAC and an output that is the CORE voltage. Voltage Loop Feedback from the CORE voltage is applied via resistor RIN to the inverting input of the error amplifier. This signal can drive the error amplifier output either high or low, depending upon the CORE voltage. Low CORE voltage makes the amplifier output move towards a higher output voltage level. Amplifier output voltage is applied to the positive inputs of the comparators via the correction summing networks. Out-of- phase sawtooth signals are applied to the two comparators inverting inputs. Increasing error amplifier voltage results in increased comparator output duty cycle. This increased duty cycle signal is passed through the PWM circuit with no phase reversal and on to the HIP6601, again with no phase reversal for gate drive to the upper MOSFETs, Q1 and Q3. Increased duty cycle or ON time for the MOSFET transistors results in increased output voltage to compensate for the low output voltage sensed. Current Loop The current control loop works in a similar fashion to the voltage control loop, but with current control information applied individually to each channel’s comparator. The information used for this control is the voltage that is developed across rDS(ON) of each lower MOSFET, Q2 and Q4, when they are conducting. A single resistor converts and scales the voltage across the MOSFETs to a current that is applied to the current sensing circuit within the ISL6553. Output from these sensing circuits is applied to the current averaging circuit. Each PWM channel receives the difference current signal from the summing circuit that compares the average sensed current to the individual channel current. When a power channel’s current is greater than the average current, the signal applied via the FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6553 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER CHANNEL REGULATOR CURRENT SENSING COMPARATOR PWM CIRCUIT + RISEN1 + CORRECTION ERROR AMPLIFIER FB REFERENCE ISEN1 RIN VCORE Q3 Q4 L2 PHASE PWM1 IL2 DAC ISL6553 COUT RLOAD VIN HIP6601 - Q1 Q2 L1 PHASE IL1 VIN HIP6601 CURRENT SENSING COMPARATOR PWM CIRCUITCORRECTION PWM2 - I AVERAGE + + + - PROGRAMMABLE RISEN2ISEN2 - - - - + + CURRENT AVERAGING     FN4931 Rev 1.00 Page 6 of 15 August 2004

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ISL6553summing correction circuit to the comparator, reduces the output pulse width of the comparator to compensate for the detected “above average” current in that channel. Droop Compensation In addition to control of each power channel’s output current, the average channel current is also used to provide CORE voltage “droop” compensation. Average full channel current is defined as 50A. By selecting an input resistor, RIN, the amount of voltage droop required at full load current can be programmed. The average current driven into the FB pin results in a voltage increase across resistor RIN that is in the direction to make the error amplifier “see” a higher voltage at the inverting input, resulting in the error amplifier adjusting the output voltage lower. The voltage developed across RIN is equal to the “droop” voltage. See the “Current Sensing and Balancing” section for more details. Applications and Converter Start-Up Each PWM power channel’s current is regulated. This enables the PWM channels to accurately share the load current for enhanced reliability. The HIP6601, HIP6602 or HIP6603 MOSFET driver interfaces with the ISL6553. For more information, see the HIP6601, HIP6602 or HIP6603 data sheets [1] [2]. The ISL6553 controls the two PWM power channels 180 degrees out of phase. Figure 2 shows the out of phase relationship between the two PWM channels. Power supply ripple frequency is determined by the channel frequency, FSW, multiplied by the number of active channels. For example, if the channel frequency is set to 250kHz, the ripple frequency is 500kHz. The IC monitors and precisely regulates the CORE voltage of a microprocessor. After initial start-up, the controller also provides protection for the load and the power supply. The following section discusses these features. Initialization The ISL6553 usually operates from an ATX power supply. Many functions are initiated by the rising supply voltage to the VCC pin of the ISL6553. Oscillator, sawtooth generator, soft- start and other functions are initialized during this interval. These circuits are controlled by POR, Power-On Reset. During this interval, the PWM outputs are driven to a three state condition that makes these outputs essentially open. This state results in no gate drive to the output MOSFETs. Once the VCC voltage reaches 4.375V (+125mV), a voltage level to insure proper internal function, the PWM outputs are enabled and the soft-start sequence is initiated. If for any reason, the VCC voltage drops below 3.875V (+125mV). The POR circuit shuts the converter down and again three states the PWM outputs. Soft-Start After the POR function is completed with VCC reaching 4.375V, the soft-start sequence is initiated. Soft-Start, by its slow rise in CORE voltage from zero, avoids an over-current condition by slowly charging the discharged output capacitors. This voltage rise is initiated by an internal DAC that slowly raises the reference voltage to the error amplifier input. The voltage rise is controlled by the oscillator frequency and the DAC within the ISL6553, therefore, the output voltage is effectively regulated as it rises to the final programmed CORE voltage value. For the first 32 PWM switching cycles, the DAC output remains inhibited and the PWM outputs remain three stated. From the 33rd cycle and for another, approximately 150 cycles the PWM output remains low, clamping the lower output MOSFETs to ground, see Figure 3. The time variability is due to the error amplifier, sawtooth generator and comparators moving into their active regions. After this short interval, the PWM outputs are enabled and increment the PWM pulse width from zero duty cycle to operational pulse width, thus allowing the output voltage to slowly reach the CORE voltage. The CORE voltage will reach its programmed value before the 2048 cycles, but the PGOOD output will not be initiated until the 2048th PWM switching cycle. The Soft-Start time or delay time, DT = 2048/FSW. For an oscillator frequency, FSW, of 200kHz, the first 32 cycles or 160s, the PWM outputs are held in a three state level as explained above. After this period and a short interval described above, the PWM outputs are initiated and the voltage rises in 10.08ms, for a total delay time DT of 10.24ms. Figure 3 shows the start-up sequence as initiated by a fast rising 5V supply, VCC, applied to the ISL6553. Note the short rise to the three state level in PWM 1 output during first 32 PWM cycles. Figure 4 shows the waveforms when the regulator is operating at 200kHz. Note that the Soft-Start duration is a function of the channel frequency as explained previously. Also note the pulses on the COMP terminal. These pulses are the current correction signal feeding into the comparator input (see the Block Diagram ). Figure 5 shows the regulator operating from an ATX supply. In this figure, note the slight rise in PGOOD as the 5V supply rises. The PGOOD output stage is made up of NMOS and PMOS transistors. On the rising VCC, the PMOS device PWM 1 PWM 2 FIGURE 2. TWO PHASE PWM OUTPUT AT 500kHzFN4931 Rev 1.00 Page 7 of 15 August 2004

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ISL6553becomes active slightly before the NMOS transistor pulls “down”, generating the slight rise in the PGOOD voltage. Note that Figure 5 shows the 12V gate driver voltage available before the 5V supply to the ISL6553 has reached its threshold level. If conditions were reversed and the 5V supply was to rise first, the start-up sequence would be different. In this case the ISL6553 will sense an over-current condition due to charging the output capacitors. The supply will then restart and go through the normal Soft-Start cycle. . Fault Protection The ISL6553 protects the microprocessor and the entire power system from damaging stress levels. Within the ISL6553 both over-voltage and over-current circuits are incorporated to protect the load and regulator. Over-Voltage The VSEN pin is connected to the microprocessor CORE voltage. A CORE over-voltage condition is detected when the VSEN pin goes more than 15% above the programmed VID level. The over-voltage condition is latched, disabling normal PWM operation, and causing PGOOD to go low. The latch can only be reset by lowering and returning VCC high to initiate a POR and Soft-Start sequence. During a latched over-voltage, the PWM outputs will be driven either low or three state, depending upon the VSEN input. PWM outputs are driven low when the VSEN pin detects that the CORE voltage is 15% above the programmed VID level. This condition drives the PWM outputs low, resulting in the lower or synchronous rectifier MOSFETs to conduct and shunt the CORE voltage to ground to protect the load. If after this event, the CORE voltage falls below the over- voltage limit (plus some hysteresis), the PWM outputs will three state. The HIP6601 family drivers pass the three state information along, and shuts off both upper and lower MOSFETs. This prevents “dumping” of the output capacitors back through the lower MOSFETs, avoiding a possibly destructive ringing of the capacitors and output inductors. If the conditions that caused the over-voltage still persist, the PWM outputs will be cycled between three state and VCORE clamped to ground, as a hysteretic shunt regulator. PWM 1 PGOOD VCORE 5V OUTPUT VCC VIN = 12V DELAY TIME FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT 500kHz PGOOD VCORE 5V V COMP VCC VIN = 12V DELAY TIME FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT 200kHz 12V ATX SUPPLY PGOOD 5 V ATX VCORE SUPPLY ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN” FREQUENCY 200kHz VIN = 5V, CORE LOAD CURRENT = 31A FIGURE 5. SUPPLY POWERED BY ATX SUPPLYFN4931 Rev 1.00 Page 8 of 15 August 2004

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ISL6553Under-Voltage The VSEN pin also detects when the CORE voltage falls more than 10% below the VID programmed level. This causes PGOOD to go low, but has no other effect on operation and is not latched. There is also hysteresis in this detection point. Over-Current In the event of an over-current condition, the over-current protection circuit reduces the RMS current delivered to 41% of the current limit. When an over-current condition is detected, the controller forces all PWM outputs into a three state mode. This condition results in the gate driver removing drive to the output stages. The ISL6553 goes into a wait delay timing cycle that is equal to the Soft-Start ramp time. PGOOD also goes “low” during this time due to VSEN going below its threshold voltage. To lower the average output dissipation, the Soft-Start initial wait time is increased from 32 to 2048 cycles, then the Soft-Start ramp is initiated. At a PWM frequency of 200kHz, for instance, an over-current detection would cause a dead time of 10.24ms, then a ramp of 10.08ms. At the end of the delay, PWM outputs are restarted and the Soft-Start ramp is initiated. If a short is present at that time, the cycle is repeated. This is the hiccup mode. Figure 6 shows the supply shorted under operation and the hiccup operating mode described above. Note that due to the high short circuit current, over-current is detected before completion of the start-up sequence so the delay is not quite as long as the normal Soft-Start cycle. CORE Voltage Programming The voltage identification pins (VID25mV, VID0, VID1, VID2 and VID3) set the CORE output voltage. Each VID pin is pulled to VCC by an internal 20A current source and accepts open- collector/open-drain/open-switch-to-ground or standard low- voltage TTL or CMOS signals. Table 1 shows the nominal DAC voltage as a function of the VID codes. The power supply system is 1% accurate over the operating temperature and voltage range. PGOOD SHORT 50A/DIV. CURRENT ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN” SUPPLY FREQUENCY = 200kHz, V IN = 12V HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY CORE LOAD CURRENT = 31A, 5V LOAD = 5A SHORT APPLIED HERE FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP TABLE 1. VOLTAGE IDENTIFICATION CODES VOLTAGE IDENTIFICATION CODE AT PROCESSOR PINS VCC(CORE) (VDC)VID25mV VID3 VID2 VID1 VID0 0 0 1 0 0 1.05 1 0 1 0 0 1.075 0 0 0 1 1 1.10 1 0 0 1 1 1.125 0 0 0 1 0 1.15 1 0 0 1 0 1.175 0 0 0 0 1 1.20 1 0 0 0 1 1.225 0 0 0 0 0 1.25 1 0 0 0 0 1.275 0 1 1 1 1 1.30 1 1 1 1 1 1.325 0 1 1 1 0 1.35 1 1 1 1 0 1.375 0 1 1 0 1 1.40 1 1 1 0 1 1.425 0 1 1 0 0 1.45 1 1 1 0 0 1.475 0 1 0 1 1 1.50 1 1 0 1 1 1.525 0 1 0 1 0 1.55 1 1 0 1 0 1.575 0 1 0 0 1 1.60 1 1 0 0 1 1.625 0 1 0 0 0 1.65 1 1 0 0 0 1.675 0 0 1 1 1 1.70 1 0 1 1 1 1.725 0 0 1 1 0 1.75 1 0 1 1 0 1.775 0 0 1 0 1 1.80 1 0 1 0 1 1.825FN4931 Rev 1.00 Page 9 of 15 August 2004

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November 16, 2020

Great dealing with you Guys. Thanks for a very prompt delivery.

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November 15, 2020

Items arrived well pakaged, reasonable postage and as described. Top seller

Cami*****ella

November 14, 2020

They worked great. Not much to say - as far as I can tell they adhere to the specs, and did the job I needed them to. Good transistors for higher current situations.

Juelz *****araman

November 13, 2020

Parts received and tested, all can work, thank you

Benn*****Guzman

November 11, 2020

Good service, and great value for money I am pleased with the item of ISL6553CB.

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October 31, 2020

Sure appreciate your service high standard, expertise and skills. Thanks Much!!!

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October 16, 2020

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October 16, 2020

Most of the reviews for this product were positive so I took a chance.

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